drivers/clk/mediatek/clk-mt6795-infracfg.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2022 Collabora Ltd.
   4  * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   5  */
   6
   7 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
   8 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11 #include "clk-cpumux.h"
  12 #include "clk-gate.h"
  13 #include "clk-mtk.h"
  14 #include "reset.h"
  15
  16 #define GATE_ICG(_id, _name, _parent, _shift)                   \
  17                 GATE_MTK(_id, _name, _parent, &infra_cg_regs,   \
  18                          _shift, &mtk_clk_gate_ops_no_setclr)
  19
  20 static const struct mtk_gate_regs infra_cg_regs = {
  21         .set_ofs = 0x0040,
  22         .clr_ofs = 0x0044,
  23         .sta_ofs = 0x0048,
  24 };
  25
  26 static const char * const ca53_c0_parents[] = {
  27         "clk26m",
  28         "armca53pll",
  29         "mainpll",
  30         "univpll"
  31 };
  32
  33 static const char * const ca53_c1_parents[] = {
  34         "clk26m",
  35         "armca53pll",
  36         "mainpll",
  37         "univpll"
  38 };
  39
  40 static const struct mtk_composite cpu_muxes[] = {
  41         MUX(CLK_INFRA_CA53_C0_SEL, "infra_ca53_c0_sel", ca53_c0_parents, 0x00, 0, 2),
  42         MUX(CLK_INFRA_CA53_C1_SEL, "infra_ca53_c1_sel", ca53_c1_parents, 0x00, 2, 2),
  43 };
  44
  45 static const struct mtk_gate infra_gates[] = {
  46         GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
  47         GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
  48         GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
  49         GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
  50         GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
  51         GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
  52         GATE_ICG(CLK_INFRA_MD1MCU, "infra_md1mcu", "clk26m", 9),
  53         GATE_ICG(CLK_INFRA_MD1BUS, "infra_md1bus", "axi_sel", 10),
  54         GATE_ICG(CLK_INFRA_MD1DBB, "infra_dbb", "axi_sel", 11),
  55         GATE_ICG(CLK_INFRA_DEVICE_APC, "infra_devapc", "clk26m", 12),
  56         GATE_ICG(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 13),
  57         GATE_ICG(CLK_INFRA_MD1LTE, "infra_md1lte", "axi_sel", 14),
  58         GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
  59         GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
  60 };
  61
  62 static u16 infra_ao_rst_ofs[] = { 0x30, 0x34 };
  63
  64 static u16 infra_ao_idx_map[] = {
  65         [MT6795_INFRA_RST0_SCPSYS_RST]    = 0 * RST_NR_PER_BANK + 5,
  66         [MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7,
  67         [MT6795_INFRA_RST1_MIPI_DSI_RST]  = 1 * RST_NR_PER_BANK + 4,
  68         [MT6795_INFRA_RST1_MIPI_CSI_RST]  = 1 * RST_NR_PER_BANK + 7,
  69         [MT6795_INFRA_RST1_MM_IOMMU_RST]  = 1 * RST_NR_PER_BANK + 15,
  70 };
  71
  72 static const struct mtk_clk_rst_desc clk_rst_desc = {
  73         .version = MTK_RST_SET_CLR,
  74         .rst_bank_ofs = infra_ao_rst_ofs,
  75         .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
  76         .rst_idx_map = infra_ao_idx_map,
  77         .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
  78 };
  79
  80 static const struct of_device_id of_match_clk_mt6795_infracfg[] = {
  81         { .compatible = "mediatek,mt6795-infracfg" },
  82         { /* sentinel */ }
  83 };
  84 MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_infracfg);
  85
  86 static int clk_mt6795_infracfg_probe(struct platform_device *pdev)
  87 {
  88         struct clk_hw_onecell_data *clk_data;
  89         struct device_node *node = pdev->dev.of_node;
  90         void __iomem *base;
  91         int ret;
  92
  93         base = devm_platform_ioremap_resource(pdev, 0);
  94         if (IS_ERR(base))
  95                 return PTR_ERR(base);
  96
  97         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  98         if (!clk_data)
  99                 return -ENOMEM;
 100
 101         ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 102         if (ret)
 103                 goto free_clk_data;
 104
 105         ret = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
 106                                      ARRAY_SIZE(infra_gates), clk_data);
 107         if (ret)
 108                 goto free_clk_data;
 109
 110         ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
 111                                         ARRAY_SIZE(cpu_muxes), clk_data);
 112         if (ret)
 113                 goto unregister_gates;
 114
 115         ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 116         if (ret)
 117                 goto unregister_cpumuxes;
 118
 119         return 0;
 120
 121 unregister_cpumuxes:
 122         mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
 123 unregister_gates:
 124         mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
 125 free_clk_data:
 126         mtk_free_clk_data(clk_data);
 127         return ret;
 128 }
 129
 130 static void clk_mt6795_infracfg_remove(struct platform_device *pdev)
 131 {
 132         struct device_node *node = pdev->dev.of_node;
 133         struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
 134
 135         of_clk_del_provider(node);
 136         mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
 137         mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
 138         mtk_free_clk_data(clk_data);
 139 }
 140
 141 static struct platform_driver clk_mt6795_infracfg_drv = {
 142         .driver = {
 143                 .name = "clk-mt6795-infracfg",
 144                 .of_match_table = of_match_clk_mt6795_infracfg,
 145         },
 146         .probe = clk_mt6795_infracfg_probe,
 147         .remove_new = clk_mt6795_infracfg_remove,
 148 };
 149 module_platform_driver(clk_mt6795_infracfg_drv);
 150
 151 MODULE_DESCRIPTION("MediaTek MT6795 infracfg clocks driver");
 152 MODULE_LICENSE("GPL");