drivers/clk/mediatek/clk-mt2701.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Shunli Wang <shunli.wang@mediatek.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/mod_devicetable.h>
   9 #include <linux/platform_device.h>
  10
  11 #include "clk-cpumux.h"
  12 #include "clk-gate.h"
  13 #include "clk-mtk.h"
  14 #include "clk-pll.h"
  15
  16 #include <dt-bindings/clock/mt2701-clk.h>
  17
  18 /*
  19  * For some clocks, we don't care what their actual rates are. And these
  20  * clocks may change their rate on different products or different scenarios.
  21  * So we model these clocks' rate as 0, to denote it's not an actual rate.
  22  */
  23 #define DUMMY_RATE              0
  24
  25 static DEFINE_SPINLOCK(mt2701_clk_lock);
  26
  27 static const struct mtk_fixed_clk top_fixed_clks[] = {
  28         FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
  29                 108 * MHZ),
  30         FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
  31                 400 * MHZ),
  32         FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
  33                 295750000),
  34         FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
  35                 340 * MHZ),
  36         FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
  37                 340 * MHZ),
  38         FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
  39                 340 * MHZ),
  40         FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
  41                 27 * MHZ),
  42         FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
  43                 416 * MHZ),
  44         FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
  45                 143 * MHZ),
  46         FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
  47                 27 * MHZ),
  48         FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
  49                 DUMMY_RATE),
  50         FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
  51                 DUMMY_RATE),
  52         FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
  53                 DUMMY_RATE),
  54 };
  55
  56 static const struct mtk_fixed_factor top_fixed_divs[] = {
  57         FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
  58         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  59         FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  60         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  61         FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  62         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  63         FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  64         FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  65         FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  66         FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  67         FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  68         FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  69         FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  70         FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  71         FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  72         FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  73
  74         FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
  75         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  76         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  77         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  78         FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  79         FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
  80         FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
  81         FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
  82         FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
  83         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
  84         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
  85         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
  86         FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
  87         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
  88         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
  89         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
  90         FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
  91         FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
  92         FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
  93         FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
  94         FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
  95
  96         FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
  97         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  98         FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
  99         FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
 100
 101         FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
 102         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
 103
 104         FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
 105         FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
 106         FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
 107
 108         FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
 109         FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
 110         FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
 111
 112         FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
 113         FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
 114         FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
 115
 116         FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
 117         FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
 118         FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
 119
 120         FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
 121         FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
 122         FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
 123
 124         FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
 125
 126         FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
 127         FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
 128         FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
 129         FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
 130         FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
 131
 132         FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
 133         FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
 134         FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
 135         FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
 136         FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
 137         FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
 138         FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
 139         FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
 140         FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
 141 };
 142
 143 static const char * const axi_parents[] = {
 144         "clk26m",
 145         "syspll1_d2",
 146         "syspll_d5",
 147         "syspll1_d4",
 148         "univpll_d5",
 149         "univpll2_d2",
 150         "mmpll_d2",
 151         "dmpll_d2"
 152 };
 153
 154 static const char * const mem_parents[] = {
 155         "clk26m",
 156         "dmpll_ck"
 157 };
 158
 159 static const char * const ddrphycfg_parents[] = {
 160         "clk26m",
 161         "syspll1_d8"
 162 };
 163
 164 static const char * const mm_parents[] = {
 165         "clk26m",
 166         "vencpll_ck",
 167         "syspll1_d2",
 168         "syspll1_d4",
 169         "univpll_d5",
 170         "univpll1_d2",
 171         "univpll2_d2",
 172         "dmpll_ck"
 173 };
 174
 175 static const char * const pwm_parents[] = {
 176         "clk26m",
 177         "univpll2_d4",
 178         "univpll3_d2",
 179         "univpll1_d4",
 180 };
 181
 182 static const char * const vdec_parents[] = {
 183         "clk26m",
 184         "vdecpll_ck",
 185         "syspll_d5",
 186         "syspll1_d4",
 187         "univpll_d5",
 188         "univpll2_d2",
 189         "vencpll_ck",
 190         "msdcpll_d2",
 191         "mmpll_d2"
 192 };
 193
 194 static const char * const mfg_parents[] = {
 195         "clk26m",
 196         "mmpll_ck",
 197         "dmpll_x2_ck",
 198         "msdcpll_ck",
 199         "clk26m",
 200         "syspll_d3",
 201         "univpll_d3",
 202         "univpll1_d2"
 203 };
 204
 205 static const char * const camtg_parents[] = {
 206         "clk26m",
 207         "univpll_d26",
 208         "univpll2_d2",
 209         "syspll3_d2",
 210         "syspll3_d4",
 211         "msdcpll_d2",
 212         "mmpll_d2"
 213 };
 214
 215 static const char * const uart_parents[] = {
 216         "clk26m",
 217         "univpll2_d8"
 218 };
 219
 220 static const char * const spi_parents[] = {
 221         "clk26m",
 222         "syspll3_d2",
 223         "syspll4_d2",
 224         "univpll2_d4",
 225         "univpll1_d8"
 226 };
 227
 228 static const char * const usb20_parents[] = {
 229         "clk26m",
 230         "univpll1_d8",
 231         "univpll3_d4"
 232 };
 233
 234 static const char * const msdc30_parents[] = {
 235         "clk26m",
 236         "msdcpll_d2",
 237         "syspll2_d2",
 238         "syspll1_d4",
 239         "univpll1_d4",
 240         "univpll2_d4"
 241 };
 242
 243 static const char * const aud_intbus_parents[] = {
 244         "clk26m",
 245         "syspll1_d4",
 246         "syspll3_d2",
 247         "syspll4_d2",
 248         "univpll3_d2",
 249         "univpll2_d4"
 250 };
 251
 252 static const char * const pmicspi_parents[] = {
 253         "clk26m",
 254         "syspll1_d8",
 255         "syspll2_d4",
 256         "syspll4_d2",
 257         "syspll3_d4",
 258         "syspll2_d8",
 259         "syspll1_d16",
 260         "univpll3_d4",
 261         "univpll_d26",
 262         "dmpll_d2",
 263         "dmpll_d4"
 264 };
 265
 266 static const char * const scp_parents[] = {
 267         "clk26m",
 268         "syspll1_d8",
 269         "dmpll_d2",
 270         "dmpll_d4"
 271 };
 272
 273 static const char * const dpi0_parents[] = {
 274         "clk26m",
 275         "mipipll",
 276         "mipipll_d2",
 277         "mipipll_d4",
 278         "clk26m",
 279         "tvdpll_ck",
 280         "tvdpll_d2",
 281         "tvdpll_d4"
 282 };
 283
 284 static const char * const dpi1_parents[] = {
 285         "clk26m",
 286         "tvdpll_ck",
 287         "tvdpll_d2",
 288         "tvdpll_d4"
 289 };
 290
 291 static const char * const tve_parents[] = {
 292         "clk26m",
 293         "mipipll",
 294         "mipipll_d2",
 295         "mipipll_d4",
 296         "clk26m",
 297         "tvdpll_ck",
 298         "tvdpll_d2",
 299         "tvdpll_d4"
 300 };
 301
 302 static const char * const hdmi_parents[] = {
 303         "clk26m",
 304         "hdmipll_ck",
 305         "hdmipll_d2",
 306         "hdmipll_d3"
 307 };
 308
 309 static const char * const apll_parents[] = {
 310         "clk26m",
 311         "audpll",
 312         "audpll_d4",
 313         "audpll_d8",
 314         "audpll_d16",
 315         "audpll_d24",
 316         "clk26m",
 317         "clk26m"
 318 };
 319
 320 static const char * const rtc_parents[] = {
 321         "32k_internal",
 322         "32k_external",
 323         "clk26m",
 324         "univpll3_d8"
 325 };
 326
 327 static const char * const nfi2x_parents[] = {
 328         "clk26m",
 329         "syspll2_d2",
 330         "syspll_d7",
 331         "univpll3_d2",
 332         "syspll2_d4",
 333         "univpll3_d4",
 334         "syspll4_d4",
 335         "clk26m"
 336 };
 337
 338 static const char * const emmc_hclk_parents[] = {
 339         "clk26m",
 340         "syspll1_d2",
 341         "syspll1_d4",
 342         "syspll2_d2"
 343 };
 344
 345 static const char * const flash_parents[] = {
 346         "clk26m_d8",
 347         "clk26m",
 348         "syspll2_d8",
 349         "syspll3_d4",
 350         "univpll3_d4",
 351         "syspll4_d2",
 352         "syspll2_d4",
 353         "univpll2_d4"
 354 };
 355
 356 static const char * const di_parents[] = {
 357         "clk26m",
 358         "tvd2pll_ck",
 359         "tvd2pll_d2",
 360         "clk26m"
 361 };
 362
 363 static const char * const nr_osd_parents[] = {
 364         "clk26m",
 365         "vencpll_ck",
 366         "syspll1_d2",
 367         "syspll1_d4",
 368         "univpll_d5",
 369         "univpll1_d2",
 370         "univpll2_d2",
 371         "dmpll_ck"
 372 };
 373
 374 static const char * const hdmirx_bist_parents[] = {
 375         "clk26m",
 376         "syspll_d3",
 377         "clk26m",
 378         "syspll1_d16",
 379         "syspll4_d2",
 380         "syspll1_d4",
 381         "vencpll_ck",
 382         "clk26m"
 383 };
 384
 385 static const char * const intdir_parents[] = {
 386         "clk26m",
 387         "mmpll_ck",
 388         "syspll_d2",
 389         "univpll_d2"
 390 };
 391
 392 static const char * const asm_parents[] = {
 393         "clk26m",
 394         "univpll2_d4",
 395         "univpll2_d2",
 396         "syspll_d5"
 397 };
 398
 399 static const char * const ms_card_parents[] = {
 400         "clk26m",
 401         "univpll3_d8",
 402         "syspll4_d4"
 403 };
 404
 405 static const char * const ethif_parents[] = {
 406         "clk26m",
 407         "syspll1_d2",
 408         "syspll_d5",
 409         "syspll1_d4",
 410         "univpll_d5",
 411         "univpll1_d2",
 412         "dmpll_ck",
 413         "dmpll_d2"
 414 };
 415
 416 static const char * const hdmirx_parents[] = {
 417         "clk26m",
 418         "univpll_d52"
 419 };
 420
 421 static const char * const cmsys_parents[] = {
 422         "clk26m",
 423         "syspll1_d2",
 424         "univpll1_d2",
 425         "univpll_d5",
 426         "syspll_d5",
 427         "syspll2_d2",
 428         "syspll1_d4",
 429         "syspll3_d2",
 430         "syspll2_d4",
 431         "syspll1_d8",
 432         "clk26m",
 433         "clk26m",
 434         "clk26m",
 435         "clk26m",
 436         "clk26m"
 437 };
 438
 439 static const char * const clk_8bdac_parents[] = {
 440         "32k_internal",
 441         "8bdac_ck",
 442         "clk26m",
 443         "clk26m"
 444 };
 445
 446 static const char * const aud2dvd_parents[] = {
 447         "a1sys_hp_ck",
 448         "a2sys_hp_ck"
 449 };
 450
 451 static const char * const padmclk_parents[] = {
 452         "clk26m",
 453         "univpll_d26",
 454         "univpll_d52",
 455         "univpll_d108",
 456         "univpll2_d8",
 457         "univpll2_d16",
 458         "univpll2_d32"
 459 };
 460
 461 static const char * const aud_mux_parents[] = {
 462         "clk26m",
 463         "aud1pll_98m_ck",
 464         "aud2pll_90m_ck",
 465         "hadds2pll_98m",
 466         "audio_ext1_ck",
 467         "audio_ext2_ck"
 468 };
 469
 470 static const char * const aud_src_parents[] = {
 471         "aud_mux1_sel",
 472         "aud_mux2_sel"
 473 };
 474
 475 static const char * const cpu_parents[] = {
 476         "clk26m",
 477         "armpll",
 478         "mainpll",
 479         "mmpll"
 480 };
 481
 482 static const struct mtk_composite cpu_muxes[] __initconst = {
 483         MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
 484 };
 485
 486 static const struct mtk_composite top_muxes[] = {
 487         MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 488                 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
 489         MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
 490                 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
 491         MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
 492                 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
 493         MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
 494                 0x0040, 24, 3, 31),
 495
 496         MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
 497                 0x0050, 0, 2, 7),
 498         MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
 499                 0x0050, 8, 4, 15),
 500         MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
 501                 0x0050, 16, 3, 23),
 502         MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
 503                 0x0050, 24, 3, 31),
 504         MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
 505                 0x0060, 0, 1, 7),
 506
 507         MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
 508                 0x0060, 8, 3, 15),
 509         MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
 510                 0x0060, 16, 2, 23),
 511         MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
 512                 0x0060, 24, 3, 31),
 513
 514         MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
 515                 0x0070, 0, 3, 7),
 516         MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
 517                 0x0070, 8, 3, 15),
 518         MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
 519                 0x0070, 16, 1, 23),
 520         MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
 521                 0x0070, 24, 3, 31),
 522
 523         MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
 524                 0x0080, 0, 4, 7),
 525         MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
 526                 0x0080, 8, 2, 15),
 527         MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
 528                 0x0080, 16, 3, 23),
 529         MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
 530                 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
 531
 532         MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
 533                 0x0090, 0, 3, 7),
 534         MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
 535                 0x0090, 8, 2, 15),
 536         MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
 537                 0x0090, 16, 3, 23),
 538
 539         MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
 540                 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
 541         MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
 542                 0x00A0, 8, 3, 15),
 543         MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
 544                 0x00A0, 24, 2, 31),
 545
 546         MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
 547                 0x00B0, 0, 3, 7),
 548         MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
 549                 0x00B0, 8, 2, 15),
 550         MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
 551                 0x00B0, 16, 3, 23),
 552         MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
 553                 0x00B0, 24, 3, 31),
 554
 555         MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
 556                 hdmirx_bist_parents, 0x00C0, 0, 3, 7),
 557         MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
 558                 0x00C0, 8, 2, 15),
 559         MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
 560                 0x00C0, 16, 2, 23),
 561         MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
 562                 0x00C0, 24, 3, 31),
 563
 564         MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
 565                 0x00D0, 0, 2, 7),
 566         MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
 567                 0x00D0, 16, 2, 23),
 568         MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
 569                 0x00D0, 24, 3, 31),
 570
 571         MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
 572                 0x00E0, 0, 1, 7),
 573         MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
 574                 0x00E0, 8, 3, 15),
 575         MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
 576                 0x00E0, 16, 4, 23),
 577
 578         MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
 579                 0x00E0, 24, 3, 31),
 580         MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
 581                 0x00F0, 0, 3, 7),
 582         MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
 583                 0x00F0, 8, 2, 15),
 584         MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
 585                 0x00F0, 16, 1, 23),
 586
 587         MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
 588                 0x0100, 0, 3),
 589
 590         MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
 591                 0x012c, 0, 3),
 592         MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
 593                 0x012c, 3, 3),
 594         MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
 595                 0x012c, 6, 3),
 596         MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
 597                 0x012c, 15, 1, 23),
 598         MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
 599                 0x012c, 16, 1, 24),
 600         MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
 601                 0x012c, 17, 1, 25),
 602         MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
 603                 0x012c, 18, 1, 26),
 604         MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
 605                 0x012c, 19, 1, 27),
 606         MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
 607                 0x012c, 20, 1, 28),
 608 };
 609
 610 static const struct mtk_clk_divider top_adj_divs[] = {
 611         DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
 612                 0x0120, 0, 8),
 613         DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
 614                 0x0120, 8, 8),
 615         DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
 616                 0x0120, 16, 8),
 617         DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
 618                 0x0120, 24, 8),
 619         DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
 620                 0x0124, 0, 8),
 621         DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
 622                 0x0124, 8, 8),
 623         DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
 624                 0x0124, 16, 8),
 625         DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
 626                 0x0124, 24, 8),
 627         DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
 628                 0x0128, 0, 8),
 629         DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
 630                 0x0128, 8, 8),
 631 };
 632
 633 static const struct mtk_gate_regs top_aud_cg_regs = {
 634         .sta_ofs = 0x012C,
 635 };
 636
 637 #define GATE_TOP_AUD(_id, _name, _parent, _shift)                       \
 638         GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
 639
 640 static const struct mtk_gate top_clks[] = {
 641         GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
 642                 21),
 643         GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
 644                 22),
 645         GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
 646                 23),
 647         GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
 648                 24),
 649         GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
 650                 25),
 651         GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
 652                 26),
 653         GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
 654                 27),
 655         GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
 656                 28),
 657 };
 658
 659 static int mtk_topckgen_init(struct platform_device *pdev)
 660 {
 661         struct clk_hw_onecell_data *clk_data;
 662         void __iomem *base;
 663         struct device_node *node = pdev->dev.of_node;
 664
 665         base = devm_platform_ioremap_resource(pdev, 0);
 666         if (IS_ERR(base))
 667                 return PTR_ERR(base);
 668
 669         clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
 670         if (!clk_data)
 671                 return -ENOMEM;
 672
 673         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 674                                                                 clk_data);
 675
 676         mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
 677                                                                 clk_data);
 678
 679         mtk_clk_register_composites(&pdev->dev, top_muxes,
 680                                     ARRAY_SIZE(top_muxes), base,
 681                                     &mt2701_clk_lock, clk_data);
 682
 683         mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_divs),
 684                                 base, &mt2701_clk_lock, clk_data);
 685
 686         mtk_clk_register_gates(&pdev->dev, node, top_clks,
 687                                ARRAY_SIZE(top_clks), clk_data);
 688
 689         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 690 }
 691
 692 static const struct mtk_gate_regs infra_cg_regs = {
 693         .set_ofs = 0x0040,
 694         .clr_ofs = 0x0044,
 695         .sta_ofs = 0x0048,
 696 };
 697
 698 #define GATE_ICG(_id, _name, _parent, _shift)                           \
 699         GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 700
 701 static const struct mtk_gate infra_clks[] = {
 702         GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
 703         GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
 704         GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
 705         GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
 706         GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
 707         GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
 708         GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
 709         GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
 710         GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
 711         GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
 712         GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
 713         GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
 714         GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
 715         GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
 716         GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
 717         GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
 718         GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
 719         GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
 720 };
 721
 722 static const struct mtk_fixed_factor infra_fixed_divs[] = {
 723         FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 724 };
 725
 726 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
 727 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
 728
 729 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
 730         /* infrasys */
 731         {
 732                 .version = MTK_RST_SIMPLE,
 733                 .rst_bank_ofs = infrasys_rst_ofs,
 734                 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
 735         },
 736         /* pericfg */
 737         {
 738                 .version = MTK_RST_SIMPLE,
 739                 .rst_bank_ofs = pericfg_rst_ofs,
 740                 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
 741         },
 742 };
 743
 744 static struct clk_hw_onecell_data *infra_clk_data;
 745
 746 static void __init mtk_infrasys_init_early(struct device_node *node)
 747 {
 748         int r, i;
 749
 750         if (!infra_clk_data) {
 751                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 752                 if (!infra_clk_data)
 753                         return;
 754
 755                 for (i = 0; i < CLK_INFRA_NR; i++)
 756                         infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
 757         }
 758
 759         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 760                                                 infra_clk_data);
 761
 762         mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
 763                                   infra_clk_data);
 764
 765         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
 766                                    infra_clk_data);
 767         if (r)
 768                 pr_err("%s(): could not register clock provider: %d\n",
 769                         __func__, r);
 770 }
 771 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
 772                         mtk_infrasys_init_early);
 773
 774 static int mtk_infrasys_init(struct platform_device *pdev)
 775 {
 776         int r, i;
 777         struct device_node *node = pdev->dev.of_node;
 778
 779         if (!infra_clk_data) {
 780                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 781                 if (!infra_clk_data)
 782                         return -ENOMEM;
 783         } else {
 784                 for (i = 0; i < CLK_INFRA_NR; i++) {
 785                         if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
 786                                 infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
 787                 }
 788         }
 789
 790         mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 791                                ARRAY_SIZE(infra_clks), infra_clk_data);
 792         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 793                                                 infra_clk_data);
 794
 795         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
 796                                    infra_clk_data);
 797         if (r)
 798                 return r;
 799
 800         mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 801
 802         return 0;
 803 }
 804
 805 static const struct mtk_gate_regs peri0_cg_regs = {
 806         .set_ofs = 0x0008,
 807         .clr_ofs = 0x0010,
 808         .sta_ofs = 0x0018,
 809 };
 810
 811 static const struct mtk_gate_regs peri1_cg_regs = {
 812         .set_ofs = 0x000c,
 813         .clr_ofs = 0x0014,
 814         .sta_ofs = 0x001c,
 815 };
 816
 817 #define GATE_PERI0(_id, _name, _parent, _shift)                         \
 818         GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 819
 820 #define GATE_PERI1(_id, _name, _parent, _shift)                         \
 821         GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 822
 823 static const struct mtk_gate peri_clks[] = {
 824         GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
 825         GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
 826         GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
 827         GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
 828         GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
 829         GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
 830         GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
 831         GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
 832         GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
 833         GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
 834         GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
 835         GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
 836         GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
 837         GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
 838         GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
 839         GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
 840         GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
 841         GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
 842         GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
 843         GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
 844         GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
 845         GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
 846         GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
 847         GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
 848         GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
 849         GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
 850         GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
 851         GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
 852         GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
 853         GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
 854         GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
 855         GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
 856
 857         GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
 858         GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
 859         GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
 860         GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
 861         GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
 862         GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
 863         GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
 864         GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
 865         GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
 866         GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
 867         GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
 868         GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
 869 };
 870
 871 static const char * const uart_ck_sel_parents[] = {
 872         "clk26m",
 873         "uart_sel",
 874 };
 875
 876 static const struct mtk_composite peri_muxs[] = {
 877         MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
 878                 0x40c, 0, 1),
 879         MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
 880                 0x40c, 1, 1),
 881         MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
 882                 0x40c, 2, 1),
 883         MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
 884                 0x40c, 3, 1),
 885 };
 886
 887 static int mtk_pericfg_init(struct platform_device *pdev)
 888 {
 889         struct clk_hw_onecell_data *clk_data;
 890         void __iomem *base;
 891         int r;
 892         struct device_node *node = pdev->dev.of_node;
 893
 894         base = devm_platform_ioremap_resource(pdev, 0);
 895         if (IS_ERR(base))
 896                 return PTR_ERR(base);
 897
 898         clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
 899         if (!clk_data)
 900                 return -ENOMEM;
 901
 902         mtk_clk_register_gates(&pdev->dev, node, peri_clks,
 903                                ARRAY_SIZE(peri_clks), clk_data);
 904
 905         mtk_clk_register_composites(&pdev->dev, peri_muxs,
 906                                     ARRAY_SIZE(peri_muxs), base,
 907                                     &mt2701_clk_lock, clk_data);
 908
 909         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 910         if (r)
 911                 return r;
 912
 913         mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 914
 915         return 0;
 916 }
 917
 918 #define MT8590_PLL_FMAX         (2000 * MHZ)
 919 #define CON0_MT8590_RST_BAR     BIT(27)
 920
 921 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
 922                         _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) {  \
 923                 .id = _id,                                              \
 924                 .name = _name,                                          \
 925                 .reg = _reg,                                            \
 926                 .pwr_reg = _pwr_reg,                                    \
 927                 .en_mask = _en_mask,                                    \
 928                 .flags = _flags,                                        \
 929                 .rst_bar_mask = CON0_MT8590_RST_BAR,                    \
 930                 .fmax = MT8590_PLL_FMAX,                                \
 931                 .pcwbits = _pcwbits,                                    \
 932                 .pd_reg = _pd_reg,                                      \
 933                 .pd_shift = _pd_shift,                                  \
 934                 .tuner_reg = _tuner_reg,                                \
 935                 .pcw_reg = _pcw_reg,                                    \
 936                 .pcw_shift = _pcw_shift,                                \
 937         }
 938
 939 static const struct mtk_pll_data apmixed_plls[] = {
 940         PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
 941                         PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
 942         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
 943                   HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
 944         PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
 945                   HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
 946         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
 947                                 21, 0x230, 4, 0x0, 0x234, 0),
 948         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
 949                                 21, 0x240, 4, 0x0, 0x244, 0),
 950         PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
 951                                 21, 0x250, 4, 0x0, 0x254, 0),
 952         PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
 953                                 31, 0x270, 4, 0x0, 0x274, 0),
 954         PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
 955                                 31, 0x280, 4, 0x0, 0x284, 0),
 956         PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
 957                                 31, 0x290, 4, 0x0, 0x294, 0),
 958         PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
 959                                 31, 0x2a0, 4, 0x0, 0x2a4, 0),
 960         PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
 961                                 31, 0x2b0, 4, 0x0, 0x2b4, 0),
 962         PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
 963                                 31, 0x2c0, 4, 0x0, 0x2c4, 0),
 964         PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
 965                                 21, 0x2d0, 4, 0x0, 0x2d4, 0),
 966 };
 967
 968 static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
 969         FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
 970 };
 971
 972 static int mtk_apmixedsys_init(struct platform_device *pdev)
 973 {
 974         struct clk_hw_onecell_data *clk_data;
 975         struct device_node *node = pdev->dev.of_node;
 976
 977         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
 978         if (!clk_data)
 979                 return -ENOMEM;
 980
 981         mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
 982                                                                 clk_data);
 983         mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
 984                                                                 clk_data);
 985
 986         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 987 }
 988
 989 static const struct of_device_id of_match_clk_mt2701[] = {
 990         {
 991                 .compatible = "mediatek,mt2701-topckgen",
 992                 .data = mtk_topckgen_init,
 993         }, {
 994                 .compatible = "mediatek,mt2701-infracfg",
 995                 .data = mtk_infrasys_init,
 996         }, {
 997                 .compatible = "mediatek,mt2701-pericfg",
 998                 .data = mtk_pericfg_init,
 999         }, {
1000                 .compatible = "mediatek,mt2701-apmixedsys",
1001                 .data = mtk_apmixedsys_init,
1002         }, {
1003                 /* sentinel */
1004         }
1005 };
1006 MODULE_DEVICE_TABLE(of, of_match_clk_mt2701);
1007
1008 static int clk_mt2701_probe(struct platform_device *pdev)
1009 {
1010         int (*clk_init)(struct platform_device *);
1011         int r;
1012
1013         clk_init = of_device_get_match_data(&pdev->dev);
1014         if (!clk_init)
1015                 return -EINVAL;
1016
1017         r = clk_init(pdev);
1018         if (r)
1019                 dev_err(&pdev->dev,
1020                         "could not register clock provider: %s: %d\n",
1021                         pdev->name, r);
1022
1023         return r;
1024 }
1025
1026 static struct platform_driver clk_mt2701_drv = {
1027         .probe = clk_mt2701_probe,
1028         .driver = {
1029                 .name = "clk-mt2701",
1030                 .of_match_table = of_match_clk_mt2701,
1031         },
1032 };
1033
1034 static int __init clk_mt2701_init(void)
1035 {
1036         return platform_driver_register(&clk_mt2701_drv);
1037 }
1038
1039 arch_initcall(clk_mt2701_init);
1040 MODULE_LICENSE("GPL");