1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx SoCs TCU clocks driver
4 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
8 #include <linux/clk-provider.h>
9 #include <linux/clockchips.h>
10 #include <linux/mfd/ingenic-tcu.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/regmap.h>
13 #include <linux/slab.h>
14 #include <linux/syscore_ops.h>
16 #include <dt-bindings/clock/ingenic,tcu.h>
18 /* 8 channels max + watchdog + OST */
19 #define TCU_CLK_COUNT 10
22 #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt
30 struct ingenic_soc_info {
31 unsigned int num_channels;
36 struct ingenic_tcu_clk_info {
37 struct clk_init_data init_data;
42 struct ingenic_tcu_clk {
45 struct ingenic_tcu *tcu;
46 const struct ingenic_tcu_clk_info *info;
50 const struct ingenic_soc_info *soc_info;
54 struct clk_hw_onecell_data *clocks;
57 static struct ingenic_tcu *ingenic_tcu;
59 static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw)
61 return container_of(hw, struct ingenic_tcu_clk, hw);
64 static int ingenic_tcu_enable(struct clk_hw *hw)
66 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
67 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
68 struct ingenic_tcu *tcu = tcu_clk->tcu;
70 regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
75 static void ingenic_tcu_disable(struct clk_hw *hw)
77 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
78 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
79 struct ingenic_tcu *tcu = tcu_clk->tcu;
81 regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
84 static int ingenic_tcu_is_enabled(struct clk_hw *hw)
86 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
87 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
90 regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value);
92 return !(value & BIT(info->gate_bit));
95 static bool ingenic_tcu_enable_regs(struct clk_hw *hw)
97 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
98 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
99 struct ingenic_tcu *tcu = tcu_clk->tcu;
100 bool enabled = false;
103 * According to the programming manual, a timer channel's registers can
104 * only be accessed when the channel's stop bit is clear.
106 enabled = !!ingenic_tcu_is_enabled(hw);
107 regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
112 static void ingenic_tcu_disable_regs(struct clk_hw *hw)
114 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
115 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
116 struct ingenic_tcu *tcu = tcu_clk->tcu;
118 regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
121 static u8 ingenic_tcu_get_parent(struct clk_hw *hw)
123 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
124 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
125 unsigned int val = 0;
128 ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val);
129 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
131 return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1;
134 static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx)
136 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
137 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
141 was_enabled = ingenic_tcu_enable_regs(hw);
143 ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
144 TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx));
145 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
148 ingenic_tcu_disable_regs(hw);
153 static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw,
154 unsigned long parent_rate)
156 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
157 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
158 unsigned int prescale;
161 ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale);
162 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
164 prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB;
166 return parent_rate >> (prescale * 2);
169 static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
173 for (prescale = 0; prescale < 5; prescale++)
174 if ((rate >> (prescale * 2)) <= req_rate)
177 return 5; /* /1024 divider */
180 static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
181 unsigned long *parent_rate)
183 unsigned long rate = *parent_rate;
189 prescale = ingenic_tcu_get_prescale(rate, req_rate);
191 return rate >> (prescale * 2);
194 static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
195 unsigned long parent_rate)
197 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
198 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
199 u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate);
203 was_enabled = ingenic_tcu_enable_regs(hw);
205 ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
206 TCU_TCSR_PRESCALE_MASK,
207 prescale << TCU_TCSR_PRESCALE_LSB);
208 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
211 ingenic_tcu_disable_regs(hw);
216 static const struct clk_ops ingenic_tcu_clk_ops = {
217 .get_parent = ingenic_tcu_get_parent,
218 .set_parent = ingenic_tcu_set_parent,
220 .recalc_rate = ingenic_tcu_recalc_rate,
221 .round_rate = ingenic_tcu_round_rate,
222 .set_rate = ingenic_tcu_set_rate,
224 .enable = ingenic_tcu_enable,
225 .disable = ingenic_tcu_disable,
226 .is_enabled = ingenic_tcu_is_enabled,
229 static const char * const ingenic_tcu_timer_parents[] = {
230 [TCU_PARENT_PCLK] = "pclk",
231 [TCU_PARENT_RTC] = "rtc",
232 [TCU_PARENT_EXT] = "ext",
235 #define DEF_TIMER(_name, _gate_bit, _tcsr) \
239 .parent_names = ingenic_tcu_timer_parents, \
240 .num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\
241 .ops = &ingenic_tcu_clk_ops, \
242 .flags = CLK_SET_RATE_UNGATE, \
244 .gate_bit = _gate_bit, \
247 static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = {
248 [TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)),
249 [TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)),
250 [TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)),
251 [TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)),
252 [TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)),
253 [TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)),
254 [TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)),
255 [TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)),
258 static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info =
259 DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR);
260 static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info =
261 DEF_TIMER("ost", 15, TCU_REG_OST_TCSR);
264 static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
265 unsigned int idx, enum tcu_clk_parent parent,
266 const struct ingenic_tcu_clk_info *info,
267 struct clk_hw_onecell_data *clocks)
269 struct ingenic_tcu_clk *tcu_clk;
272 tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
276 tcu_clk->hw.init = &info->init_data;
278 tcu_clk->info = info;
281 /* Reset channel and clock divider, set default parent */
282 ingenic_tcu_enable_regs(&tcu_clk->hw);
283 regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
284 ingenic_tcu_disable_regs(&tcu_clk->hw);
286 err = clk_hw_register(NULL, &tcu_clk->hw);
292 clocks->hws[idx] = &tcu_clk->hw;
297 static const struct ingenic_soc_info jz4740_soc_info = {
303 static const struct ingenic_soc_info jz4725b_soc_info = {
309 static const struct ingenic_soc_info jz4770_soc_info = {
312 .has_tcu_clk = false,
315 static const struct ingenic_soc_info x1000_soc_info = {
317 .has_ost = false, /* X1000 has OST, but it not belong TCU */
318 .has_tcu_clk = false,
321 static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
322 { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
323 { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
324 { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
325 { .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, },
329 static int __init ingenic_tcu_probe(struct device_node *np)
331 const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
332 struct ingenic_tcu *tcu;
337 map = device_node_to_regmap(np);
341 tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
346 tcu->soc_info = id->data;
348 if (tcu->soc_info->has_tcu_clk) {
349 tcu->clk = of_clk_get_by_name(np, "tcu");
350 if (IS_ERR(tcu->clk)) {
351 ret = PTR_ERR(tcu->clk);
352 pr_crit("Cannot get TCU clock\n");
356 ret = clk_prepare_enable(tcu->clk);
358 pr_crit("Unable to enable TCU clock\n");
363 tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT),
367 goto err_clk_disable;
370 tcu->clocks->num = TCU_CLK_COUNT;
372 for (i = 0; i < tcu->soc_info->num_channels; i++) {
373 ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT,
374 &ingenic_tcu_clk_info[i],
377 pr_crit("cannot register clock %d\n", i);
378 goto err_unregister_timer_clocks;
383 * We set EXT as the default parent clock for all the TCU clocks
384 * except for the watchdog one, where we set the RTC clock as the
385 * parent. Since the EXT and PCLK are much faster than the RTC clock,
386 * the watchdog would kick after a maximum time of 5s, and we might
387 * want a slower kicking time.
389 ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC,
390 &ingenic_tcu_watchdog_clk_info,
393 pr_crit("cannot register watchdog clock\n");
394 goto err_unregister_timer_clocks;
397 if (tcu->soc_info->has_ost) {
398 ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST,
400 &ingenic_tcu_ost_clk_info,
403 pr_crit("cannot register ost clock\n");
404 goto err_unregister_watchdog_clock;
408 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks);
410 pr_crit("cannot add OF clock provider\n");
411 goto err_unregister_ost_clock;
418 err_unregister_ost_clock:
419 if (tcu->soc_info->has_ost)
420 clk_hw_unregister(tcu->clocks->hws[i + 1]);
421 err_unregister_watchdog_clock:
422 clk_hw_unregister(tcu->clocks->hws[i]);
423 err_unregister_timer_clocks:
424 for (i = 0; i < tcu->clocks->num; i++)
425 if (tcu->clocks->hws[i])
426 clk_hw_unregister(tcu->clocks->hws[i]);
429 if (tcu->soc_info->has_tcu_clk)
430 clk_disable_unprepare(tcu->clk);
432 if (tcu->soc_info->has_tcu_clk)
439 static int __maybe_unused tcu_pm_suspend(void)
441 struct ingenic_tcu *tcu = ingenic_tcu;
444 clk_disable(tcu->clk);
449 static void __maybe_unused tcu_pm_resume(void)
451 struct ingenic_tcu *tcu = ingenic_tcu;
454 clk_enable(tcu->clk);
457 static struct syscore_ops __maybe_unused tcu_pm_ops = {
458 .suspend = tcu_pm_suspend,
459 .resume = tcu_pm_resume,
462 static void __init ingenic_tcu_init(struct device_node *np)
464 int ret = ingenic_tcu_probe(np);
467 pr_crit("Failed to initialize TCU clocks: %d\n", ret);
469 if (IS_ENABLED(CONFIG_PM_SLEEP))
470 register_syscore_ops(&tcu_pm_ops);
473 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
474 CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
475 CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
476 CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);