1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ4725B SoC CGU driver
5 * Copyright (C) 2018 Paul Cercueil
6 * Author: Paul Cercueil <paul@crapouillou.net>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
13 #include <dt-bindings/clock/jz4725b-cgu.h>
18 /* CGU register offsets */
19 #define CGU_REG_CPCCR 0x00
20 #define CGU_REG_LCR 0x04
21 #define CGU_REG_CPPCR 0x10
22 #define CGU_REG_CLKGR 0x20
23 #define CGU_REG_OPCR 0x24
24 #define CGU_REG_I2SCDR 0x60
25 #define CGU_REG_LPCDR 0x64
26 #define CGU_REG_MSCCDR 0x68
27 #define CGU_REG_SSICDR 0x74
28 #define CGU_REG_CIMCDR 0x78
30 /* bits within the LCR register */
31 #define LCR_SLEEP BIT(0)
33 static struct ingenic_cgu *cgu;
35 static const s8 pll_od_encoding[4] = {
39 static const u8 jz4725b_cgu_cpccr_div_table[] = {
43 static const u8 jz4725b_cgu_pll_half_div_table[] = {
47 static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
51 [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
52 [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
69 .od_encoding = pll_od_encoding,
71 .bypass_reg = CGU_REG_CPPCR,
77 /* Muxes & dividers */
79 [JZ4725B_CLK_PLL_HALF] = {
80 "pll half", CGU_CLK_DIV,
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
83 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
84 jz4725b_cgu_pll_half_div_table,
88 [JZ4725B_CLK_CCLK] = {
90 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
92 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
93 jz4725b_cgu_cpccr_div_table,
97 [JZ4725B_CLK_HCLK] = {
99 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
101 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
102 jz4725b_cgu_cpccr_div_table,
106 [JZ4725B_CLK_PCLK] = {
108 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
110 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
111 jz4725b_cgu_cpccr_div_table,
115 [JZ4725B_CLK_MCLK] = {
117 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
119 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
120 jz4725b_cgu_cpccr_div_table,
124 [JZ4725B_CLK_IPU] = {
125 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
126 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
128 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
129 jz4725b_cgu_cpccr_div_table,
131 .gate = { CGU_REG_CLKGR, 13 },
134 [JZ4725B_CLK_LCD] = {
135 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
136 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
137 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
138 .gate = { CGU_REG_CLKGR, 9 },
141 [JZ4725B_CLK_I2S] = {
142 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
143 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
144 .mux = { CGU_REG_CPCCR, 31, 1 },
145 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
148 [JZ4725B_CLK_SPI] = {
149 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
150 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
151 .mux = { CGU_REG_SSICDR, 31, 1 },
152 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
153 .gate = { CGU_REG_CLKGR, 4 },
156 [JZ4725B_CLK_MMC_MUX] = {
157 "mmc_mux", CGU_CLK_DIV,
158 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
159 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
162 [JZ4725B_CLK_UDC] = {
163 "udc", CGU_CLK_MUX | CGU_CLK_DIV,
164 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
165 .mux = { CGU_REG_CPCCR, 29, 1 },
166 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
169 /* Gate-only clocks */
171 [JZ4725B_CLK_UART] = {
172 "uart", CGU_CLK_GATE,
173 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
174 .gate = { CGU_REG_CLKGR, 0 },
177 [JZ4725B_CLK_DMA] = {
179 .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
180 .gate = { CGU_REG_CLKGR, 12 },
183 [JZ4725B_CLK_ADC] = {
185 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
186 .gate = { CGU_REG_CLKGR, 7 },
189 [JZ4725B_CLK_I2C] = {
191 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
192 .gate = { CGU_REG_CLKGR, 3 },
195 [JZ4725B_CLK_AIC] = {
197 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
198 .gate = { CGU_REG_CLKGR, 5 },
201 [JZ4725B_CLK_MMC0] = {
202 "mmc0", CGU_CLK_GATE,
203 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
204 .gate = { CGU_REG_CLKGR, 6 },
207 [JZ4725B_CLK_MMC1] = {
208 "mmc1", CGU_CLK_GATE,
209 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
210 .gate = { CGU_REG_CLKGR, 16 },
213 [JZ4725B_CLK_BCH] = {
215 .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
216 .gate = { CGU_REG_CLKGR, 11 },
219 [JZ4725B_CLK_TCU] = {
221 .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
222 .gate = { CGU_REG_CLKGR, 1 },
225 [JZ4725B_CLK_EXT512] = {
226 "ext/512", CGU_CLK_FIXDIV,
227 .parents = { JZ4725B_CLK_EXT },
229 /* Doc calls it EXT512, but it seems to be /256... */
233 [JZ4725B_CLK_RTC] = {
235 .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
236 .mux = { CGU_REG_OPCR, 2, 1},
239 [JZ4725B_CLK_UDC_PHY] = {
240 "udc_phy", CGU_CLK_GATE,
241 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
242 .gate = { CGU_REG_OPCR, 6, true },
246 static void __init jz4725b_cgu_init(struct device_node *np)
250 cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
251 ARRAY_SIZE(jz4725b_cgu_clocks), np);
253 pr_err("%s: failed to initialise CGU\n", __func__);
257 retval = ingenic_cgu_register_clocks(cgu);
259 pr_err("%s: failed to register CGU Clocks\n", __func__);
261 ingenic_cgu_register_syscore_ops(cgu);
263 CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);