1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/slab.h>
6 #include <linux/spinlock.h>
9 DEFINE_SPINLOCK(imx_ccm_lock);
11 void __init imx_check_clocks(struct clk *clks[], unsigned int count)
15 for (i = 0; i < count; i++)
17 pr_err("i.MX clk %u: register failed with %ld\n",
21 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
23 struct of_phandle_args phandle;
24 struct clk *clk = ERR_PTR(-ENODEV);
27 path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
29 return ERR_PTR(-ENOMEM);
31 phandle.np = of_find_node_by_path(path);
35 clk = of_clk_get_from_provider(&phandle);
36 of_node_put(phandle.np);
41 struct clk * __init imx_obtain_fixed_clock(
42 const char *name, unsigned long rate)
46 clk = imx_obtain_fixed_clock_from_dt(name);
48 clk = imx_clk_fixed(name, rate);
53 * This fixups the register CCM_CSCMR1 write value.
54 * The write/read/divider values of the aclk_podf field
55 * of that register have the relationship described by
56 * the following table:
58 * write value read value divider
66 * 3b'111 3b'001 2(default)
68 * That's why we do the xor operation below.
70 #define CSCMR1_FIXUP 0x00600000
72 void imx_cscmr1_fixup(u32 *val)
78 static int imx_keep_uart_clocks __initdata;
79 static struct clk ** const *imx_uart_clocks __initdata;
81 static int __init imx_keep_uart_clocks_param(char *str)
83 imx_keep_uart_clocks = 1;
87 __setup_param("earlycon", imx_keep_uart_earlycon,
88 imx_keep_uart_clocks_param, 0);
89 __setup_param("earlyprintk", imx_keep_uart_earlyprintk,
90 imx_keep_uart_clocks_param, 0);
92 void __init imx_register_uart_clocks(struct clk ** const clks[])
94 if (imx_keep_uart_clocks) {
97 imx_uart_clocks = clks;
98 for (i = 0; imx_uart_clocks[i]; i++)
99 clk_prepare_enable(*imx_uart_clocks[i]);
103 static int __init imx_clk_disable_uart(void)
105 if (imx_keep_uart_clocks && imx_uart_clocks) {
108 for (i = 0; imx_uart_clocks[i]; i++)
109 clk_disable_unprepare(*imx_uart_clocks[i]);
114 late_initcall_sync(imx_clk_disable_uart);