2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
24 #define PLL_VF610_NUM_OFFSET 0x20
25 #define PLL_VF610_DENOM_OFFSET 0x30
27 #define BM_PLL_POWER (0x1 << 12)
28 #define BM_PLL_LOCK (0x1 << 31)
29 #define IMX7_ENET_PLL_POWER (0x1 << 5)
30 #define IMX7_DDR_PLL_POWER (0x1 << 20)
33 * struct clk_pllv3 - IMX PLL clock version 3
34 * @clk_hw: clock source
35 * @base: base address of PLL registers
36 * @power_bit: pll power bit mask
37 * @powerup_set: set power_bit to power up the PLL
38 * @div_mask: mask of divider bits
39 * @div_shift: shift of divider bits
41 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
42 * is actually a multiplier, and always sits at bit 0.
51 unsigned long ref_clock;
54 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
56 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
58 unsigned long timeout = jiffies + msecs_to_jiffies(10);
59 u32 val = readl_relaxed(pll->base) & pll->power_bit;
61 /* No need to wait for lock when pll is not powered up */
62 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
65 /* Wait for PLL to lock */
67 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
69 if (time_after(jiffies, timeout))
71 usleep_range(50, 500);
74 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
77 static int clk_pllv3_prepare(struct clk_hw *hw)
79 struct clk_pllv3 *pll = to_clk_pllv3(hw);
82 val = readl_relaxed(pll->base);
84 val |= pll->power_bit;
86 val &= ~pll->power_bit;
87 writel_relaxed(val, pll->base);
89 return clk_pllv3_wait_lock(pll);
92 static void clk_pllv3_unprepare(struct clk_hw *hw)
94 struct clk_pllv3 *pll = to_clk_pllv3(hw);
97 val = readl_relaxed(pll->base);
99 val &= ~pll->power_bit;
101 val |= pll->power_bit;
102 writel_relaxed(val, pll->base);
105 static int clk_pllv3_is_prepared(struct clk_hw *hw)
107 struct clk_pllv3 *pll = to_clk_pllv3(hw);
109 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
115 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
116 unsigned long parent_rate)
118 struct clk_pllv3 *pll = to_clk_pllv3(hw);
119 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
121 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
124 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
125 unsigned long *prate)
127 unsigned long parent_rate = *prate;
129 return (rate >= parent_rate * 22) ? parent_rate * 22 :
133 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
134 unsigned long parent_rate)
136 struct clk_pllv3 *pll = to_clk_pllv3(hw);
139 if (rate == parent_rate * 22)
141 else if (rate == parent_rate * 20)
146 val = readl_relaxed(pll->base);
147 val &= ~(pll->div_mask << pll->div_shift);
148 val |= (div << pll->div_shift);
149 writel_relaxed(val, pll->base);
151 return clk_pllv3_wait_lock(pll);
154 static const struct clk_ops clk_pllv3_ops = {
155 .prepare = clk_pllv3_prepare,
156 .unprepare = clk_pllv3_unprepare,
157 .is_prepared = clk_pllv3_is_prepared,
158 .recalc_rate = clk_pllv3_recalc_rate,
159 .round_rate = clk_pllv3_round_rate,
160 .set_rate = clk_pllv3_set_rate,
163 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
164 unsigned long parent_rate)
166 struct clk_pllv3 *pll = to_clk_pllv3(hw);
167 u32 div = readl_relaxed(pll->base) & pll->div_mask;
169 return parent_rate * div / 2;
172 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
173 unsigned long *prate)
175 unsigned long parent_rate = *prate;
176 unsigned long min_rate = parent_rate * 54 / 2;
177 unsigned long max_rate = parent_rate * 108 / 2;
182 else if (rate < min_rate)
184 div = rate * 2 / parent_rate;
186 return parent_rate * div / 2;
189 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
190 unsigned long parent_rate)
192 struct clk_pllv3 *pll = to_clk_pllv3(hw);
193 unsigned long min_rate = parent_rate * 54 / 2;
194 unsigned long max_rate = parent_rate * 108 / 2;
197 if (rate < min_rate || rate > max_rate)
200 div = rate * 2 / parent_rate;
201 val = readl_relaxed(pll->base);
202 val &= ~pll->div_mask;
204 writel_relaxed(val, pll->base);
206 return clk_pllv3_wait_lock(pll);
209 static const struct clk_ops clk_pllv3_sys_ops = {
210 .prepare = clk_pllv3_prepare,
211 .unprepare = clk_pllv3_unprepare,
212 .is_prepared = clk_pllv3_is_prepared,
213 .recalc_rate = clk_pllv3_sys_recalc_rate,
214 .round_rate = clk_pllv3_sys_round_rate,
215 .set_rate = clk_pllv3_sys_set_rate,
218 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
219 unsigned long parent_rate)
221 struct clk_pllv3 *pll = to_clk_pllv3(hw);
222 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
223 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
224 u32 div = readl_relaxed(pll->base) & pll->div_mask;
225 u64 temp64 = (u64)parent_rate;
230 return parent_rate * div + (unsigned long)temp64;
233 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
234 unsigned long *prate)
236 unsigned long parent_rate = *prate;
237 unsigned long min_rate = parent_rate * 27;
238 unsigned long max_rate = parent_rate * 54;
240 u32 mfn, mfd = 1000000;
241 u32 max_mfd = 0x3FFFFFFF;
246 else if (rate < min_rate)
249 if (parent_rate <= max_mfd)
252 div = rate / parent_rate;
253 temp64 = (u64) (rate - div * parent_rate);
255 do_div(temp64, parent_rate);
258 temp64 = (u64)parent_rate;
262 return parent_rate * div + (unsigned long)temp64;
265 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
266 unsigned long parent_rate)
268 struct clk_pllv3 *pll = to_clk_pllv3(hw);
269 unsigned long min_rate = parent_rate * 27;
270 unsigned long max_rate = parent_rate * 54;
272 u32 mfn, mfd = 1000000;
273 u32 max_mfd = 0x3FFFFFFF;
276 if (rate < min_rate || rate > max_rate)
279 if (parent_rate <= max_mfd)
282 div = rate / parent_rate;
283 temp64 = (u64) (rate - div * parent_rate);
285 do_div(temp64, parent_rate);
288 val = readl_relaxed(pll->base);
289 val &= ~pll->div_mask;
291 writel_relaxed(val, pll->base);
292 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
293 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
295 return clk_pllv3_wait_lock(pll);
298 static const struct clk_ops clk_pllv3_av_ops = {
299 .prepare = clk_pllv3_prepare,
300 .unprepare = clk_pllv3_unprepare,
301 .is_prepared = clk_pllv3_is_prepared,
302 .recalc_rate = clk_pllv3_av_recalc_rate,
303 .round_rate = clk_pllv3_av_round_rate,
304 .set_rate = clk_pllv3_av_set_rate,
307 struct clk_pllv3_vf610_mf {
308 u32 mfi; /* integer part, can be 20 or 22 */
309 u32 mfn; /* numerator, 30-bit value */
310 u32 mfd; /* denominator, 30-bit value, must be less than mfn */
313 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
314 struct clk_pllv3_vf610_mf mf)
318 temp64 = parent_rate;
320 do_div(temp64, mf.mfd);
322 return (parent_rate * mf.mfi) + temp64;
325 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
326 unsigned long parent_rate, unsigned long rate)
328 struct clk_pllv3_vf610_mf mf;
331 mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
332 mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */
334 if (rate <= parent_rate * mf.mfi)
336 else if (rate >= parent_rate * (mf.mfi + 1))
339 /* rate = parent_rate * (mfi + mfn/mfd) */
340 temp64 = rate - parent_rate * mf.mfi;
342 do_div(temp64, parent_rate);
349 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
350 unsigned long parent_rate)
352 struct clk_pllv3 *pll = to_clk_pllv3(hw);
353 struct clk_pllv3_vf610_mf mf;
355 mf.mfn = readl_relaxed(pll->base + PLL_VF610_NUM_OFFSET);
356 mf.mfd = readl_relaxed(pll->base + PLL_VF610_DENOM_OFFSET);
357 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
359 return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
362 static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
363 unsigned long *prate)
365 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
367 return clk_pllv3_vf610_mf_to_rate(*prate, mf);
370 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate)
373 struct clk_pllv3 *pll = to_clk_pllv3(hw);
374 struct clk_pllv3_vf610_mf mf =
375 clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
378 val = readl_relaxed(pll->base);
380 val &= ~pll->div_mask; /* clear bit for mfi=20 */
382 val |= pll->div_mask; /* set bit for mfi=22 */
383 writel_relaxed(val, pll->base);
385 writel_relaxed(mf.mfn, pll->base + PLL_VF610_NUM_OFFSET);
386 writel_relaxed(mf.mfd, pll->base + PLL_VF610_DENOM_OFFSET);
388 return clk_pllv3_wait_lock(pll);
391 static const struct clk_ops clk_pllv3_vf610_ops = {
392 .prepare = clk_pllv3_prepare,
393 .unprepare = clk_pllv3_unprepare,
394 .is_prepared = clk_pllv3_is_prepared,
395 .recalc_rate = clk_pllv3_vf610_recalc_rate,
396 .round_rate = clk_pllv3_vf610_round_rate,
397 .set_rate = clk_pllv3_vf610_set_rate,
400 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
401 unsigned long parent_rate)
403 struct clk_pllv3 *pll = to_clk_pllv3(hw);
405 return pll->ref_clock;
408 static const struct clk_ops clk_pllv3_enet_ops = {
409 .prepare = clk_pllv3_prepare,
410 .unprepare = clk_pllv3_unprepare,
411 .is_prepared = clk_pllv3_is_prepared,
412 .recalc_rate = clk_pllv3_enet_recalc_rate,
415 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
416 const char *parent_name, void __iomem *base,
419 struct clk_pllv3 *pll;
420 const struct clk_ops *ops;
422 struct clk_init_data init;
424 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
426 return ERR_PTR(-ENOMEM);
428 pll->power_bit = BM_PLL_POWER;
432 ops = &clk_pllv3_sys_ops;
434 case IMX_PLLV3_SYS_VF610:
435 ops = &clk_pllv3_vf610_ops;
437 case IMX_PLLV3_USB_VF610:
440 ops = &clk_pllv3_ops;
441 pll->powerup_set = true;
444 ops = &clk_pllv3_av_ops;
446 case IMX_PLLV3_ENET_IMX7:
447 pll->power_bit = IMX7_ENET_PLL_POWER;
448 pll->ref_clock = 1000000000;
449 ops = &clk_pllv3_enet_ops;
452 pll->ref_clock = 500000000;
453 ops = &clk_pllv3_enet_ops;
455 case IMX_PLLV3_DDR_IMX7:
456 pll->power_bit = IMX7_DDR_PLL_POWER;
457 ops = &clk_pllv3_av_ops;
460 ops = &clk_pllv3_ops;
463 pll->div_mask = div_mask;
468 init.parent_names = &parent_name;
469 init.num_parents = 1;
471 pll->hw.init = &init;
473 clk = clk_register(NULL, &pll->hw);