2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_LOCK (0x1 << 31)
26 #define IMX7_ENET_PLL_POWER (0x1 << 5)
29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source
31 * @base: base address of PLL registers
32 * @power_bit: pll power bit mask
33 * @powerup_set: set power_bit to power up the PLL
34 * @div_mask: mask of divider bits
35 * @div_shift: shift of divider bits
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
38 * is actually a multiplier, and always sits at bit 0.
47 unsigned long ref_clock;
50 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
52 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
54 unsigned long timeout = jiffies + msecs_to_jiffies(10);
55 u32 val = readl_relaxed(pll->base) & pll->power_bit;
57 /* No need to wait for lock when pll is not powered up */
58 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
61 /* Wait for PLL to lock */
63 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
65 if (time_after(jiffies, timeout))
67 usleep_range(50, 500);
70 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
73 static int clk_pllv3_prepare(struct clk_hw *hw)
75 struct clk_pllv3 *pll = to_clk_pllv3(hw);
78 val = readl_relaxed(pll->base);
80 val |= pll->power_bit;
82 val &= ~pll->power_bit;
83 writel_relaxed(val, pll->base);
85 return clk_pllv3_wait_lock(pll);
88 static void clk_pllv3_unprepare(struct clk_hw *hw)
90 struct clk_pllv3 *pll = to_clk_pllv3(hw);
93 val = readl_relaxed(pll->base);
95 val &= ~pll->power_bit;
97 val |= pll->power_bit;
98 writel_relaxed(val, pll->base);
101 static int clk_pllv3_is_prepared(struct clk_hw *hw)
103 struct clk_pllv3 *pll = to_clk_pllv3(hw);
105 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
111 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
112 unsigned long parent_rate)
114 struct clk_pllv3 *pll = to_clk_pllv3(hw);
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
117 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
120 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
121 unsigned long *prate)
123 unsigned long parent_rate = *prate;
125 return (rate >= parent_rate * 22) ? parent_rate * 22 :
129 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
130 unsigned long parent_rate)
132 struct clk_pllv3 *pll = to_clk_pllv3(hw);
135 if (rate == parent_rate * 22)
137 else if (rate == parent_rate * 20)
142 val = readl_relaxed(pll->base);
143 val &= ~(pll->div_mask << pll->div_shift);
144 val |= (div << pll->div_shift);
145 writel_relaxed(val, pll->base);
147 return clk_pllv3_wait_lock(pll);
150 static const struct clk_ops clk_pllv3_ops = {
151 .prepare = clk_pllv3_prepare,
152 .unprepare = clk_pllv3_unprepare,
153 .is_prepared = clk_pllv3_is_prepared,
154 .recalc_rate = clk_pllv3_recalc_rate,
155 .round_rate = clk_pllv3_round_rate,
156 .set_rate = clk_pllv3_set_rate,
159 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
160 unsigned long parent_rate)
162 struct clk_pllv3 *pll = to_clk_pllv3(hw);
163 u32 div = readl_relaxed(pll->base) & pll->div_mask;
165 return parent_rate * div / 2;
168 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
169 unsigned long *prate)
171 unsigned long parent_rate = *prate;
172 unsigned long min_rate = parent_rate * 54 / 2;
173 unsigned long max_rate = parent_rate * 108 / 2;
178 else if (rate < min_rate)
180 div = rate * 2 / parent_rate;
182 return parent_rate * div / 2;
185 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
186 unsigned long parent_rate)
188 struct clk_pllv3 *pll = to_clk_pllv3(hw);
189 unsigned long min_rate = parent_rate * 54 / 2;
190 unsigned long max_rate = parent_rate * 108 / 2;
193 if (rate < min_rate || rate > max_rate)
196 div = rate * 2 / parent_rate;
197 val = readl_relaxed(pll->base);
198 val &= ~pll->div_mask;
200 writel_relaxed(val, pll->base);
202 return clk_pllv3_wait_lock(pll);
205 static const struct clk_ops clk_pllv3_sys_ops = {
206 .prepare = clk_pllv3_prepare,
207 .unprepare = clk_pllv3_unprepare,
208 .is_prepared = clk_pllv3_is_prepared,
209 .recalc_rate = clk_pllv3_sys_recalc_rate,
210 .round_rate = clk_pllv3_sys_round_rate,
211 .set_rate = clk_pllv3_sys_set_rate,
214 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
215 unsigned long parent_rate)
217 struct clk_pllv3 *pll = to_clk_pllv3(hw);
218 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
219 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
220 u32 div = readl_relaxed(pll->base) & pll->div_mask;
221 u64 temp64 = (u64)parent_rate;
226 return parent_rate * div + (unsigned long)temp64;
229 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
230 unsigned long *prate)
232 unsigned long parent_rate = *prate;
233 unsigned long min_rate = parent_rate * 27;
234 unsigned long max_rate = parent_rate * 54;
236 u32 mfn, mfd = 1000000;
241 else if (rate < min_rate)
244 div = rate / parent_rate;
245 temp64 = (u64) (rate - div * parent_rate);
247 do_div(temp64, parent_rate);
250 temp64 = (u64)parent_rate;
254 return parent_rate * div + (unsigned long)temp64;
257 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
258 unsigned long parent_rate)
260 struct clk_pllv3 *pll = to_clk_pllv3(hw);
261 unsigned long min_rate = parent_rate * 27;
262 unsigned long max_rate = parent_rate * 54;
264 u32 mfn, mfd = 1000000;
267 if (rate < min_rate || rate > max_rate)
270 div = rate / parent_rate;
271 temp64 = (u64) (rate - div * parent_rate);
273 do_div(temp64, parent_rate);
276 val = readl_relaxed(pll->base);
277 val &= ~pll->div_mask;
279 writel_relaxed(val, pll->base);
280 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
281 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
283 return clk_pllv3_wait_lock(pll);
286 static const struct clk_ops clk_pllv3_av_ops = {
287 .prepare = clk_pllv3_prepare,
288 .unprepare = clk_pllv3_unprepare,
289 .is_prepared = clk_pllv3_is_prepared,
290 .recalc_rate = clk_pllv3_av_recalc_rate,
291 .round_rate = clk_pllv3_av_round_rate,
292 .set_rate = clk_pllv3_av_set_rate,
295 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
296 unsigned long parent_rate)
298 struct clk_pllv3 *pll = to_clk_pllv3(hw);
300 return pll->ref_clock;
303 static const struct clk_ops clk_pllv3_enet_ops = {
304 .prepare = clk_pllv3_prepare,
305 .unprepare = clk_pllv3_unprepare,
306 .is_prepared = clk_pllv3_is_prepared,
307 .recalc_rate = clk_pllv3_enet_recalc_rate,
310 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
311 const char *parent_name, void __iomem *base,
314 struct clk_pllv3 *pll;
315 const struct clk_ops *ops;
317 struct clk_init_data init;
319 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
321 return ERR_PTR(-ENOMEM);
323 pll->power_bit = BM_PLL_POWER;
327 ops = &clk_pllv3_sys_ops;
329 case IMX_PLLV3_USB_VF610:
332 ops = &clk_pllv3_ops;
333 pll->powerup_set = true;
336 ops = &clk_pllv3_av_ops;
338 case IMX_PLLV3_ENET_IMX7:
339 pll->power_bit = IMX7_ENET_PLL_POWER;
340 pll->ref_clock = 1000000000;
341 ops = &clk_pllv3_enet_ops;
344 pll->ref_clock = 500000000;
345 ops = &clk_pllv3_enet_ops;
348 ops = &clk_pllv3_ops;
351 pll->div_mask = div_mask;
356 init.parent_names = &parent_name;
357 init.num_parents = 1;
359 pll->hw.init = &init;
361 clk = clk_register(NULL, &pll->hw);