drivers/clk/hisilicon/clk-hi3620.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Hisilicon Hi3620 clock driver
   4  *
   5  * Copyright (c) 2012-2013 Hisilicon Limited.
   6  * Copyright (c) 2012-2013 Linaro Limited.
   7  *
   8  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
   9  *         Xin Li <li.xin@linaro.org>
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/slab.h>
  18
  19 #include <dt-bindings/clock/hi3620-clock.h>
  20
  21 #include "clk.h"
  22
  23 /* clock parent list */
  24 static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
  25 static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
  26 static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
  27 static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
  28 static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
  29 static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
  30 static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
  31 static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
  32 static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
  33 static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
  34 static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
  35 static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
  36 static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
  37 static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
  38 static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
  39 static const char *const spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
  40 static const char *const spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
  41 static const char *const spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
  42 /* share axi parent */
  43 static const char *const saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
  44 static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
  45 static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
  46 static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", };
  47 static const char *const mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
  48 static const char *const mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
  49 static const char *const g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
  50 static const char *const venc_mux_p[] __initconst = { "armpll2", "armpll3", };
  51 static const char *const vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
  52 static const char *const vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
  53 static const char *const edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
  54 static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
  55                                              "armpll3", "armpll5", };
  56 static const char *const edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
  57 static const char *const ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
  58                                              "armpll3", "armpll5", };
  59 static const char *const rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
  60 static const char *const mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
  61 static const char *const mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
  62
  63
  64 /* fixed rate clocks */
  65 static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = {
  66         { HI3620_OSC32K,   "osc32k",   NULL, 0, 32768, },
  67         { HI3620_OSC26M,   "osc26m",   NULL, 0, 26000000, },
  68         { HI3620_PCLK,     "pclk",     NULL, 0, 26000000, },
  69         { HI3620_PLL_ARM0, "armpll0",  NULL, 0, 1600000000, },
  70         { HI3620_PLL_ARM1, "armpll1",  NULL, 0, 1600000000, },
  71         { HI3620_PLL_PERI, "armpll2",  NULL, 0, 1440000000, },
  72         { HI3620_PLL_USB,  "armpll3",  NULL, 0, 1440000000, },
  73         { HI3620_PLL_HDMI, "armpll4",  NULL, 0, 1188000000, },
  74         { HI3620_PLL_GPU,  "armpll5",  NULL, 0, 1300000000, },
  75 };
  76
  77 /* fixed factor clocks */
  78 static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdata = {
  79         { HI3620_RCLK_TCXO,   "rclk_tcxo",   "osc26m",   1, 4,  0, },
  80         { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2",  1, 30, 0, },
  81         { HI3620_RCLK_PICO,   "rclk_pico",   "hsic_div", 1, 40, 0, },
  82 };
  83
  84 static struct hisi_mux_clock hi3620_mux_clks[] __initdata = {
  85         { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0,     15, 2, 0,                   },
  86         { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0,     17, 2, 0,                   },
  87         { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0,     19, 2, 0,                   },
  88         { HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0,     21, 2, 0,                   },
  89         { HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x18,  0,  2, 0,                   },
  90         { HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x18,  2,  2, 0,                   },
  91         { HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x18,  4,  2, 0,                   },
  92         { HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x18,  6,  2, 0,                   },
  93         { HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x18,  8,  2, 0,                   },
  94         { HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x18,  10, 2, 0,                   },
  95         { HI3620_UART0_MUX,  "uart0_mux",  uart0_mux_p,  ARRAY_SIZE(uart0_mux_p),  CLK_SET_RATE_PARENT, 0x100, 7,  1, CLK_MUX_HIWORD_MASK, },
  96         { HI3620_UART1_MUX,  "uart1_mux",  uart1_mux_p,  ARRAY_SIZE(uart1_mux_p),  CLK_SET_RATE_PARENT, 0x100, 8,  1, CLK_MUX_HIWORD_MASK, },
  97         { HI3620_UART2_MUX,  "uart2_mux",  uart2_mux_p,  ARRAY_SIZE(uart2_mux_p),  CLK_SET_RATE_PARENT, 0x100, 9,  1, CLK_MUX_HIWORD_MASK, },
  98         { HI3620_UART3_MUX,  "uart3_mux",  uart3_mux_p,  ARRAY_SIZE(uart3_mux_p),  CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },
  99         { HI3620_UART4_MUX,  "uart4_mux",  uart4_mux_p,  ARRAY_SIZE(uart4_mux_p),  CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },
 100         { HI3620_SPI0_MUX,   "spi0_mux",   spi0_mux_p,   ARRAY_SIZE(spi0_mux_p),   CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },
 101         { HI3620_SPI1_MUX,   "spi1_mux",   spi1_mux_p,   ARRAY_SIZE(spi1_mux_p),   CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },
 102         { HI3620_SPI2_MUX,   "spi2_mux",   spi2_mux_p,   ARRAY_SIZE(spi2_mux_p),   CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },
 103         { HI3620_SAXI_MUX,   "saxi_mux",   saxi_mux_p,   ARRAY_SIZE(saxi_mux_p),   CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },
 104         { HI3620_PWM0_MUX,   "pwm0_mux",   pwm0_mux_p,   ARRAY_SIZE(pwm0_mux_p),   CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },
 105         { HI3620_PWM1_MUX,   "pwm1_mux",   pwm1_mux_p,   ARRAY_SIZE(pwm1_mux_p),   CLK_SET_RATE_PARENT, 0x104, 11, 1, CLK_MUX_HIWORD_MASK, },
 106         { HI3620_SD_MUX,     "sd_mux",     sd_mux_p,     ARRAY_SIZE(sd_mux_p),     CLK_SET_RATE_PARENT, 0x108, 4,  1, CLK_MUX_HIWORD_MASK, },
 107         { HI3620_MMC1_MUX,   "mmc1_mux",   mmc1_mux_p,   ARRAY_SIZE(mmc1_mux_p),   CLK_SET_RATE_PARENT, 0x108, 9,  1, CLK_MUX_HIWORD_MASK, },
 108         { HI3620_MMC1_MUX2,  "mmc1_mux2",  mmc1_mux2_p,  ARRAY_SIZE(mmc1_mux2_p),  CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, },
 109         { HI3620_G2D_MUX,    "g2d_mux",    g2d_mux_p,    ARRAY_SIZE(g2d_mux_p),    CLK_SET_RATE_PARENT, 0x10c, 5,  1, CLK_MUX_HIWORD_MASK, },
 110         { HI3620_VENC_MUX,   "venc_mux",   venc_mux_p,   ARRAY_SIZE(venc_mux_p),   CLK_SET_RATE_PARENT, 0x10c, 11, 1, CLK_MUX_HIWORD_MASK, },
 111         { HI3620_VDEC_MUX,   "vdec_mux",   vdec_mux_p,   ARRAY_SIZE(vdec_mux_p),   CLK_SET_RATE_PARENT, 0x110, 5,  1, CLK_MUX_HIWORD_MASK, },
 112         { HI3620_VPP_MUX,    "vpp_mux",    vpp_mux_p,    ARRAY_SIZE(vpp_mux_p),    CLK_SET_RATE_PARENT, 0x110, 11, 1, CLK_MUX_HIWORD_MASK, },
 113         { HI3620_EDC0_MUX,   "edc0_mux",   edc0_mux_p,   ARRAY_SIZE(edc0_mux_p),   CLK_SET_RATE_PARENT, 0x114, 6,  1, CLK_MUX_HIWORD_MASK, },
 114         { HI3620_LDI0_MUX,   "ldi0_mux",   ldi0_mux_p,   ARRAY_SIZE(ldi0_mux_p),   CLK_SET_RATE_PARENT, 0x114, 13, 2, CLK_MUX_HIWORD_MASK, },
 115         { HI3620_EDC1_MUX,   "edc1_mux",   edc1_mux_p,   ARRAY_SIZE(edc1_mux_p),   CLK_SET_RATE_PARENT, 0x118, 6,  1, CLK_MUX_HIWORD_MASK, },
 116         { HI3620_LDI1_MUX,   "ldi1_mux",   ldi1_mux_p,   ARRAY_SIZE(ldi1_mux_p),   CLK_SET_RATE_PARENT, 0x118, 14, 2, CLK_MUX_HIWORD_MASK, },
 117         { HI3620_RCLK_HSIC,  "rclk_hsic",  rclk_hsic_p,  ARRAY_SIZE(rclk_hsic_p),  CLK_SET_RATE_PARENT, 0x130, 2,  1, CLK_MUX_HIWORD_MASK, },
 118         { HI3620_MMC2_MUX,   "mmc2_mux",   mmc2_mux_p,   ARRAY_SIZE(mmc2_mux_p),   CLK_SET_RATE_PARENT, 0x140, 4,  1, CLK_MUX_HIWORD_MASK, },
 119         { HI3620_MMC3_MUX,   "mmc3_mux",   mmc3_mux_p,   ARRAY_SIZE(mmc3_mux_p),   CLK_SET_RATE_PARENT, 0x140, 9,  1, CLK_MUX_HIWORD_MASK, },
 120 };
 121
 122 static struct hisi_divider_clock hi3620_div_clks[] __initdata = {
 123         { HI3620_SHAREAXI_DIV, "saxi_div",   "saxi_mux",  0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
 124         { HI3620_CFGAXI_DIV,   "cfgaxi_div", "saxi_div",  0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
 125         { HI3620_SD_DIV,       "sd_div",     "sd_mux",    0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
 126         { HI3620_MMC1_DIV,     "mmc1_div",   "mmc1_mux",  0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
 127         { HI3620_HSIC_DIV,     "hsic_div",   "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
 128         { HI3620_MMC2_DIV,     "mmc2_div",   "mmc2_mux",  0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
 129         { HI3620_MMC3_DIV,     "mmc3_div",   "mmc3_mux",  0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
 130 };
 131
 132 static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = {
 133         { HI3620_TIMERCLK01,   "timerclk01",   "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, },
 134         { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo",    CLK_SET_RATE_PARENT, 0x20, 1, 0, },
 135         { HI3620_TIMERCLK23,   "timerclk23",   "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
 136         { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo",    CLK_SET_RATE_PARENT, 0x20, 3, 0, },
 137         { HI3620_RTCCLK,       "rtcclk",       "pclk",         CLK_SET_RATE_PARENT, 0x20, 5, 0, },
 138         { HI3620_KPC_CLK,      "kpc_clk",      "pclk",         CLK_SET_RATE_PARENT, 0x20, 6, 0, },
 139         { HI3620_GPIOCLK0,     "gpioclk0",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 8, 0, },
 140         { HI3620_GPIOCLK1,     "gpioclk1",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 9, 0, },
 141         { HI3620_GPIOCLK2,     "gpioclk2",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 10, 0, },
 142         { HI3620_GPIOCLK3,     "gpioclk3",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 11, 0, },
 143         { HI3620_GPIOCLK4,     "gpioclk4",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 12, 0, },
 144         { HI3620_GPIOCLK5,     "gpioclk5",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 13, 0, },
 145         { HI3620_GPIOCLK6,     "gpioclk6",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 14, 0, },
 146         { HI3620_GPIOCLK7,     "gpioclk7",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 15, 0, },
 147         { HI3620_GPIOCLK8,     "gpioclk8",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 16, 0, },
 148         { HI3620_GPIOCLK9,     "gpioclk9",     "pclk",         CLK_SET_RATE_PARENT, 0x20, 17, 0, },
 149         { HI3620_GPIOCLK10,    "gpioclk10",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 18, 0, },
 150         { HI3620_GPIOCLK11,    "gpioclk11",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 19, 0, },
 151         { HI3620_GPIOCLK12,    "gpioclk12",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 20, 0, },
 152         { HI3620_GPIOCLK13,    "gpioclk13",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 21, 0, },
 153         { HI3620_GPIOCLK14,    "gpioclk14",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 22, 0, },
 154         { HI3620_GPIOCLK15,    "gpioclk15",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 23, 0, },
 155         { HI3620_GPIOCLK16,    "gpioclk16",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 24, 0, },
 156         { HI3620_GPIOCLK17,    "gpioclk17",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 25, 0, },
 157         { HI3620_GPIOCLK18,    "gpioclk18",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 26, 0, },
 158         { HI3620_GPIOCLK19,    "gpioclk19",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 27, 0, },
 159         { HI3620_GPIOCLK20,    "gpioclk20",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 28, 0, },
 160         { HI3620_GPIOCLK21,    "gpioclk21",    "pclk",         CLK_SET_RATE_PARENT, 0x20, 29, 0, },
 161         { HI3620_DPHY0_CLK,    "dphy0_clk",    "osc26m",       CLK_SET_RATE_PARENT, 0x30, 15, 0, },
 162         { HI3620_DPHY1_CLK,    "dphy1_clk",    "osc26m",       CLK_SET_RATE_PARENT, 0x30, 16, 0, },
 163         { HI3620_DPHY2_CLK,    "dphy2_clk",    "osc26m",       CLK_SET_RATE_PARENT, 0x30, 17, 0, },
 164         { HI3620_USBPHY_CLK,   "usbphy_clk",   "rclk_pico",    CLK_SET_RATE_PARENT, 0x30, 24, 0, },
 165         { HI3620_ACP_CLK,      "acp_clk",      "rclk_cfgaxi",  CLK_SET_RATE_PARENT, 0x30, 28, 0, },
 166         { HI3620_TIMERCLK45,   "timerclk45",   "rclk_tcxo",    CLK_SET_RATE_PARENT, 0x40, 3, 0, },
 167         { HI3620_TIMERCLK67,   "timerclk67",   "rclk_tcxo",    CLK_SET_RATE_PARENT, 0x40, 4, 0, },
 168         { HI3620_TIMERCLK89,   "timerclk89",   "rclk_tcxo",    CLK_SET_RATE_PARENT, 0x40, 5, 0, },
 169         { HI3620_PWMCLK0,      "pwmclk0",      "pwm0_mux",     CLK_SET_RATE_PARENT, 0x40, 7, 0, },
 170         { HI3620_PWMCLK1,      "pwmclk1",      "pwm1_mux",     CLK_SET_RATE_PARENT, 0x40, 8, 0, },
 171         { HI3620_UARTCLK0,     "uartclk0",     "uart0_mux",    CLK_SET_RATE_PARENT, 0x40, 16, 0, },
 172         { HI3620_UARTCLK1,     "uartclk1",     "uart1_mux",    CLK_SET_RATE_PARENT, 0x40, 17, 0, },
 173         { HI3620_UARTCLK2,     "uartclk2",     "uart2_mux",    CLK_SET_RATE_PARENT, 0x40, 18, 0, },
 174         { HI3620_UARTCLK3,     "uartclk3",     "uart3_mux",    CLK_SET_RATE_PARENT, 0x40, 19, 0, },
 175         { HI3620_UARTCLK4,     "uartclk4",     "uart4_mux",    CLK_SET_RATE_PARENT, 0x40, 20, 0, },
 176         { HI3620_SPICLK0,      "spiclk0",      "spi0_mux",     CLK_SET_RATE_PARENT, 0x40, 21, 0, },
 177         { HI3620_SPICLK1,      "spiclk1",      "spi1_mux",     CLK_SET_RATE_PARENT, 0x40, 22, 0, },
 178         { HI3620_SPICLK2,      "spiclk2",      "spi2_mux",     CLK_SET_RATE_PARENT, 0x40, 23, 0, },
 179         { HI3620_I2CCLK0,      "i2cclk0",      "pclk",         CLK_SET_RATE_PARENT, 0x40, 24, 0, },
 180         { HI3620_I2CCLK1,      "i2cclk1",      "pclk",         CLK_SET_RATE_PARENT, 0x40, 25, 0, },
 181         { HI3620_SCI_CLK,      "sci_clk",      "osc26m",       CLK_SET_RATE_PARENT, 0x40, 26, 0, },
 182         { HI3620_I2CCLK2,      "i2cclk2",      "pclk",         CLK_SET_RATE_PARENT, 0x40, 28, 0, },
 183         { HI3620_I2CCLK3,      "i2cclk3",      "pclk",         CLK_SET_RATE_PARENT, 0x40, 29, 0, },
 184         { HI3620_DDRC_PER_CLK, "ddrc_per_clk", "rclk_cfgaxi",  CLK_SET_RATE_PARENT, 0x50, 9, 0, },
 185         { HI3620_DMAC_CLK,     "dmac_clk",     "rclk_cfgaxi",  CLK_SET_RATE_PARENT, 0x50, 10, 0, },
 186         { HI3620_USB2DVC_CLK,  "usb2dvc_clk",  "rclk_cfgaxi",  CLK_SET_RATE_PARENT, 0x50, 17, 0, },
 187         { HI3620_SD_CLK,       "sd_clk",       "sd_div",       CLK_SET_RATE_PARENT, 0x50, 20, 0, },
 188         { HI3620_MMC_CLK1,     "mmc_clk1",     "mmc1_mux2",    CLK_SET_RATE_PARENT, 0x50, 21, 0, },
 189         { HI3620_MMC_CLK2,     "mmc_clk2",     "mmc2_div",     CLK_SET_RATE_PARENT, 0x50, 22, 0, },
 190         { HI3620_MMC_CLK3,     "mmc_clk3",     "mmc3_div",     CLK_SET_RATE_PARENT, 0x50, 23, 0, },
 191         { HI3620_MCU_CLK,      "mcu_clk",      "acp_clk",      CLK_SET_RATE_PARENT, 0x50, 24, 0, },
 192 };
 193
 194 static void __init hi3620_clk_init(struct device_node *np)
 195 {
 196         struct hisi_clock_data *clk_data;
 197
 198         clk_data = hisi_clk_init(np, HI3620_NR_CLKS);
 199         if (!clk_data)
 200                 return;
 201
 202         hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
 203                                      ARRAY_SIZE(hi3620_fixed_rate_clks),
 204                                      clk_data);
 205         hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
 206                                        ARRAY_SIZE(hi3620_fixed_factor_clks),
 207                                        clk_data);
 208         hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
 209                               clk_data);
 210         hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
 211                                   clk_data);
 212         hisi_clk_register_gate_sep(hi3620_separated_gate_clks,
 213                                    ARRAY_SIZE(hi3620_separated_gate_clks),
 214                                    clk_data);
 215 }
 216 CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
 217
 218 struct hisi_mmc_clock {
 219         unsigned int            id;
 220         const char              *name;
 221         const char              *parent_name;
 222         unsigned long           flags;
 223         u32                     clken_reg;
 224         u32                     clken_bit;
 225         u32                     div_reg;
 226         u32                     div_off;
 227         u32                     div_bits;
 228         u32                     drv_reg;
 229         u32                     drv_off;
 230         u32                     drv_bits;
 231         u32                     sam_reg;
 232         u32                     sam_off;
 233         u32                     sam_bits;
 234 };
 235
 236 struct clk_mmc {
 237         struct clk_hw   hw;
 238         u32             id;
 239         void __iomem    *clken_reg;
 240         u32             clken_bit;
 241         void __iomem    *div_reg;
 242         u32             div_off;
 243         u32             div_bits;
 244         void __iomem    *drv_reg;
 245         u32             drv_off;
 246         u32             drv_bits;
 247         void __iomem    *sam_reg;
 248         u32             sam_off;
 249         u32             sam_bits;
 250 };
 251
 252 #define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw)
 253
 254 static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata = {
 255         { HI3620_SD_CIUCLK,     "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4},
 256         { HI3620_MMC_CIUCLK1,   "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4},
 257         { HI3620_MMC_CIUCLK2,   "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4},
 258         { HI3620_MMC_CIUCLK3,   "mmc_bclk3", "mmc_clk3", CLK_SET_RATE_PARENT, 0x1fc, 4, 0x1fc, 5, 3, 0x1fc, 8, 4, 0x1fc, 12, 4},
 259 };
 260
 261 static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
 262                        unsigned long parent_rate)
 263 {
 264         switch (parent_rate) {
 265         case 26000000:
 266                 return 13000000;
 267         case 180000000:
 268                 return 25000000;
 269         case 360000000:
 270                 return 50000000;
 271         case 720000000:
 272                 return 100000000;
 273         case 1440000000:
 274                 return 180000000;
 275         default:
 276                 return parent_rate;
 277         }
 278 }
 279
 280 static int mmc_clk_determine_rate(struct clk_hw *hw,
 281                                   struct clk_rate_request *req)
 282 {
 283         struct clk_mmc *mclk = to_mmc(hw);
 284
 285         if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) {
 286                 req->rate = 13000000;
 287                 req->best_parent_rate = 26000000;
 288         } else if (req->rate <= 26000000) {
 289                 req->rate = 25000000;
 290                 req->best_parent_rate = 180000000;
 291         } else if (req->rate <= 52000000) {
 292                 req->rate = 50000000;
 293                 req->best_parent_rate = 360000000;
 294         } else if (req->rate <= 100000000) {
 295                 req->rate = 100000000;
 296                 req->best_parent_rate = 720000000;
 297         } else {
 298                 /* max is 180M */
 299                 req->rate = 180000000;
 300                 req->best_parent_rate = 1440000000;
 301         }
 302         return -EINVAL;
 303 }
 304
 305 static u32 mmc_clk_delay(u32 val, u32 para, u32 off, u32 len)
 306 {
 307         u32 i;
 308
 309         for (i = 0; i < len; i++) {
 310                 if (para % 2)
 311                         val |= 1 << (off + i);
 312                 else
 313                         val &= ~(1 << (off + i));
 314                 para = para >> 1;
 315         }
 316
 317         return val;
 318 }
 319
 320 static int mmc_clk_set_timing(struct clk_hw *hw, unsigned long rate)
 321 {
 322         struct clk_mmc *mclk = to_mmc(hw);
 323         unsigned long flags;
 324         u32 sam, drv, div, val;
 325         static DEFINE_SPINLOCK(mmc_clk_lock);
 326
 327         switch (rate) {
 328         case 13000000:
 329                 sam = 3;
 330                 drv = 1;
 331                 div = 1;
 332                 break;
 333         case 25000000:
 334                 sam = 13;
 335                 drv = 6;
 336                 div = 6;
 337                 break;
 338         case 50000000:
 339                 sam = 3;
 340                 drv = 6;
 341                 div = 6;
 342                 break;
 343         case 100000000:
 344                 sam = 6;
 345                 drv = 4;
 346                 div = 6;
 347                 break;
 348         case 180000000:
 349                 sam = 6;
 350                 drv = 4;
 351                 div = 7;
 352                 break;
 353         default:
 354                 return -EINVAL;
 355         }
 356
 357         spin_lock_irqsave(&mmc_clk_lock, flags);
 358
 359         val = readl_relaxed(mclk->clken_reg);
 360         val &= ~(1 << mclk->clken_bit);
 361         writel_relaxed(val, mclk->clken_reg);
 362
 363         val = readl_relaxed(mclk->sam_reg);
 364         val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits);
 365         writel_relaxed(val, mclk->sam_reg);
 366
 367         val = readl_relaxed(mclk->drv_reg);
 368         val = mmc_clk_delay(val, drv, mclk->drv_off, mclk->drv_bits);
 369         writel_relaxed(val, mclk->drv_reg);
 370
 371         val = readl_relaxed(mclk->div_reg);
 372         val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits);
 373         writel_relaxed(val, mclk->div_reg);
 374
 375         val = readl_relaxed(mclk->clken_reg);
 376         val |= 1 << mclk->clken_bit;
 377         writel_relaxed(val, mclk->clken_reg);
 378
 379         spin_unlock_irqrestore(&mmc_clk_lock, flags);
 380
 381         return 0;
 382 }
 383
 384 static int mmc_clk_prepare(struct clk_hw *hw)
 385 {
 386         struct clk_mmc *mclk = to_mmc(hw);
 387         unsigned long rate;
 388
 389         if (mclk->id == HI3620_MMC_CIUCLK1)
 390                 rate = 13000000;
 391         else
 392                 rate = 25000000;
 393
 394         return mmc_clk_set_timing(hw, rate);
 395 }
 396
 397 static int mmc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 398                              unsigned long parent_rate)
 399 {
 400         return mmc_clk_set_timing(hw, rate);
 401 }
 402
 403 static const struct clk_ops clk_mmc_ops = {
 404         .prepare = mmc_clk_prepare,
 405         .determine_rate = mmc_clk_determine_rate,
 406         .set_rate = mmc_clk_set_rate,
 407         .recalc_rate = mmc_clk_recalc_rate,
 408 };
 409
 410 static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk,
 411                         void __iomem *base, struct device_node *np)
 412 {
 413         struct clk_mmc *mclk;
 414         struct clk *clk;
 415         struct clk_init_data init;
 416
 417         mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
 418         if (!mclk)
 419                 return ERR_PTR(-ENOMEM);
 420
 421         init.name = mmc_clk->name;
 422         init.ops = &clk_mmc_ops;
 423         init.flags = mmc_clk->flags;
 424         init.parent_names = (mmc_clk->parent_name ? &mmc_clk->parent_name : NULL);
 425         init.num_parents = (mmc_clk->parent_name ? 1 : 0);
 426         mclk->hw.init = &init;
 427
 428         mclk->id = mmc_clk->id;
 429         mclk->clken_reg = base + mmc_clk->clken_reg;
 430         mclk->clken_bit = mmc_clk->clken_bit;
 431         mclk->div_reg = base + mmc_clk->div_reg;
 432         mclk->div_off = mmc_clk->div_off;
 433         mclk->div_bits = mmc_clk->div_bits;
 434         mclk->drv_reg = base + mmc_clk->drv_reg;
 435         mclk->drv_off = mmc_clk->drv_off;
 436         mclk->drv_bits = mmc_clk->drv_bits;
 437         mclk->sam_reg = base + mmc_clk->sam_reg;
 438         mclk->sam_off = mmc_clk->sam_off;
 439         mclk->sam_bits = mmc_clk->sam_bits;
 440
 441         clk = clk_register(NULL, &mclk->hw);
 442         if (WARN_ON(IS_ERR(clk)))
 443                 kfree(mclk);
 444         return clk;
 445 }
 446
 447 static void __init hi3620_mmc_clk_init(struct device_node *node)
 448 {
 449         void __iomem *base;
 450         int i, num = ARRAY_SIZE(hi3620_mmc_clks);
 451         struct clk_onecell_data *clk_data;
 452
 453         if (!node) {
 454                 pr_err("failed to find pctrl node in DTS\n");
 455                 return;
 456         }
 457
 458         base = of_iomap(node, 0);
 459         if (!base) {
 460                 pr_err("failed to map pctrl\n");
 461                 return;
 462         }
 463
 464         clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
 465         if (WARN_ON(!clk_data))
 466                 return;
 467
 468         clk_data->clks = kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL);
 469         if (!clk_data->clks) {
 470                 kfree(clk_data);
 471                 return;
 472         }
 473
 474         for (i = 0; i < num; i++) {
 475                 struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i];
 476                 clk_data->clks[mmc_clk->id] =
 477                         hisi_register_clk_mmc(mmc_clk, base, node);
 478         }
 479
 480         clk_data->clk_num = num;
 481         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 482 }
 483
 484 CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_clk_init);