1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
8 #include <linux/clk-provider.h>
9 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/of_address.h>
13 #include <linux/slab.h>
15 static DEFINE_SPINLOCK(clklock);
17 #define MAX_FREQ 33333333
18 #define MIN_FREQ 8000000
26 #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
28 static unsigned long pll_recalc_rate(struct clk_hw *hw,
29 unsigned long parent_rate)
31 struct pll_clock *pll_clock = to_pll_clock(hw);
32 int mul = 1 << (readb(pll_clock->pllcr) & 3);
34 return parent_rate * mul;
37 static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
48 for (i = 0; i < 3; i++)
49 offset[i] = abs(rate - (*prate * (1 << i)));
50 for (i = 0; i < 3; i++)
54 m = (offset[i] < offset[m])?i:m;
56 return *prate * (1 << m);
59 static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
60 unsigned long parent_rate)
65 struct pll_clock *pll_clock = to_pll_clock(hw);
67 pll = ((rate / parent_rate) / 2) & 0x03;
68 spin_lock_irqsave(&clklock, flags);
69 val = readb(pll_clock->sckcr);
71 writeb(val, pll_clock->sckcr);
72 val = readb(pll_clock->pllcr);
75 writeb(val, pll_clock->pllcr);
76 spin_unlock_irqrestore(&clklock, flags);
80 static const struct clk_ops pll_ops = {
81 .recalc_rate = pll_recalc_rate,
82 .round_rate = pll_round_rate,
83 .set_rate = pll_set_rate,
86 static void __init h8s2678_pll_clk_setup(struct device_node *node)
88 unsigned int num_parents;
89 const char *clk_name = node->name;
90 const char *parent_name;
91 struct pll_clock *pll_clock;
92 struct clk_init_data init;
95 num_parents = of_clk_get_parent_count(node);
97 pr_err("%s: no parent found\n", clk_name);
102 pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
106 pll_clock->sckcr = of_iomap(node, 0);
107 if (pll_clock->sckcr == NULL) {
108 pr_err("%s: failed to map divide register\n", clk_name);
112 pll_clock->pllcr = of_iomap(node, 1);
113 if (pll_clock->pllcr == NULL) {
114 pr_err("%s: failed to map multiply register\n", clk_name);
118 parent_name = of_clk_get_parent_name(node, 0);
119 init.name = clk_name;
122 init.parent_names = &parent_name;
123 init.num_parents = 1;
124 pll_clock->hw.init = &init;
126 ret = clk_hw_register(NULL, &pll_clock->hw);
128 pr_err("%s: failed to register %s div clock (%d)\n",
129 __func__, clk_name, ret);
133 of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
137 iounmap(pll_clock->pllcr);
139 iounmap(pll_clock->sckcr);
144 CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
145 h8s2678_pll_clk_setup);