1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
5 * Copyright (C) 2018 David Lechner <david@lechnology.com>
8 #include <linux/clk-provider.h>
10 #include <linux/clkdev.h>
11 #include <linux/init.h>
12 #include <linux/mfd/da8xx-cfgchip.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_device.h>
16 #include <linux/platform_data/clk-da8xx-cfgchip.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
21 /* --- Gate clocks --- */
23 #define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1)
25 struct da8xx_cfgchip_gate_clk_info {
32 struct da8xx_cfgchip_gate_clk {
34 struct regmap *regmap;
39 #define to_da8xx_cfgchip_gate_clk(_hw) \
40 container_of((_hw), struct da8xx_cfgchip_gate_clk, hw)
42 static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw)
44 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask);
49 static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw)
51 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
53 regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0);
56 static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw)
58 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
61 regmap_read(clk->regmap, clk->reg, &val);
63 return !!(val & clk->mask);
66 static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw,
67 unsigned long parent_rate)
69 /* this clock divides by 4.5 */
70 return parent_rate * 2 / 9;
73 static const struct clk_ops da8xx_cfgchip_gate_clk_ops = {
74 .enable = da8xx_cfgchip_gate_clk_enable,
75 .disable = da8xx_cfgchip_gate_clk_disable,
76 .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
79 static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = {
80 .enable = da8xx_cfgchip_gate_clk_enable,
81 .disable = da8xx_cfgchip_gate_clk_disable,
82 .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
83 .recalc_rate = da8xx_cfgchip_div4p5_recalc_rate,
86 static struct da8xx_cfgchip_gate_clk * __init
87 da8xx_cfgchip_gate_clk_register(struct device *dev,
88 const struct da8xx_cfgchip_gate_clk_info *info,
89 struct regmap *regmap)
92 const char *parent_name;
93 struct da8xx_cfgchip_gate_clk *gate;
94 struct clk_init_data init;
97 parent = devm_clk_get(dev, NULL);
99 return ERR_CAST(parent);
101 parent_name = __clk_get_name(parent);
103 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
105 return ERR_PTR(-ENOMEM);
107 init.name = info->name;
108 if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5)
109 init.ops = &da8xx_cfgchip_div4p5_clk_ops;
111 init.ops = &da8xx_cfgchip_gate_clk_ops;
112 init.parent_names = &parent_name;
113 init.num_parents = 1;
116 gate->hw.init = &init;
117 gate->regmap = regmap;
118 gate->reg = info->cfgchip;
119 gate->mask = info->bit;
121 ret = devm_clk_hw_register(dev, &gate->hw);
128 static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = {
129 .name = "ehrpwm_tbclk",
130 .cfgchip = CFGCHIP(1),
131 .bit = CFGCHIP1_TBCLKSYNC,
134 static int __init da8xx_cfgchip_register_tbclk(struct device *dev,
135 struct regmap *regmap)
137 struct da8xx_cfgchip_gate_clk *gate;
139 gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info,
142 return PTR_ERR(gate);
144 clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0");
145 clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1");
150 static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = {
152 .cfgchip = CFGCHIP(3),
153 .bit = CFGCHIP3_DIV45PENA,
154 .flags = DA8XX_GATE_CLOCK_IS_DIV4P5,
157 static int __init da8xx_cfgchip_register_div4p5(struct device *dev,
158 struct regmap *regmap)
160 struct da8xx_cfgchip_gate_clk *gate;
162 gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);
164 return PTR_ERR(gate);
170 of_da8xx_cfgchip_gate_clk_init(struct device *dev,
171 const struct da8xx_cfgchip_gate_clk_info *info,
172 struct regmap *regmap)
174 struct da8xx_cfgchip_gate_clk *gate;
176 gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap);
178 return PTR_ERR(gate);
180 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate);
183 static int __init of_da8xx_tbclksync_init(struct device *dev,
184 struct regmap *regmap)
186 return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap);
189 static int __init of_da8xx_div4p5ena_init(struct device *dev,
190 struct regmap *regmap)
192 return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap);
195 /* --- MUX clocks --- */
197 struct da8xx_cfgchip_mux_clk_info {
205 struct da8xx_cfgchip_mux_clk {
207 struct regmap *regmap;
212 #define to_da8xx_cfgchip_mux_clk(_hw) \
213 container_of((_hw), struct da8xx_cfgchip_mux_clk, hw)
215 static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index)
217 struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
218 unsigned int val = index ? clk->mask : 0;
220 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val);
223 static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw)
225 struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
228 regmap_read(clk->regmap, clk->reg, &val);
230 return (val & clk->mask) ? 1 : 0;
233 static const struct clk_ops da8xx_cfgchip_mux_clk_ops = {
234 .set_parent = da8xx_cfgchip_mux_clk_set_parent,
235 .get_parent = da8xx_cfgchip_mux_clk_get_parent,
238 static struct da8xx_cfgchip_mux_clk * __init
239 da8xx_cfgchip_mux_clk_register(struct device *dev,
240 const struct da8xx_cfgchip_mux_clk_info *info,
241 struct regmap *regmap)
243 const char * const parent_names[] = { info->parent0, info->parent1 };
244 struct da8xx_cfgchip_mux_clk *mux;
245 struct clk_init_data init;
248 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
250 return ERR_PTR(-ENOMEM);
252 init.name = info->name;
253 init.ops = &da8xx_cfgchip_mux_clk_ops;
254 init.parent_names = parent_names;
255 init.num_parents = 2;
258 mux->hw.init = &init;
259 mux->regmap = regmap;
260 mux->reg = info->cfgchip;
261 mux->mask = info->bit;
263 ret = devm_clk_hw_register(dev, &mux->hw);
270 static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = {
272 .parent0 = "pll0_sysclk3",
274 .cfgchip = CFGCHIP(3),
275 .bit = CFGCHIP3_EMA_CLKSRC,
278 static int __init da8xx_cfgchip_register_async1(struct device *dev,
279 struct regmap *regmap)
281 struct da8xx_cfgchip_mux_clk *mux;
283 mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap);
287 clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0");
292 static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = {
294 .parent0 = "pll0_sysclk2",
295 .parent1 = "pll1_sysclk2",
296 .cfgchip = CFGCHIP(3),
297 .bit = CFGCHIP3_ASYNC3_CLKSRC,
300 static int __init da850_cfgchip_register_async3(struct device *dev,
301 struct regmap *regmap)
303 struct da8xx_cfgchip_mux_clk *mux;
304 struct clk_hw *parent;
306 mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap);
310 clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1");
312 /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */
313 parent = clk_hw_get_parent_by_index(&mux->hw, 1);
315 clk_set_parent(mux->hw.clk, parent->clk);
317 dev_warn(dev, "Failed to find async3 parent clock\n");
323 of_da8xx_cfgchip_init_mux_clock(struct device *dev,
324 const struct da8xx_cfgchip_mux_clk_info *info,
325 struct regmap *regmap)
327 struct da8xx_cfgchip_mux_clk *mux;
329 mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap);
333 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw);
336 static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap)
338 return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap);
341 static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap)
343 return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap);
346 /* --- USB 2.0 PHY clock --- */
348 struct da8xx_usb0_clk48 {
351 struct regmap *regmap;
354 #define to_da8xx_usb0_clk48(_hw) \
355 container_of((_hw), struct da8xx_usb0_clk48, hw)
357 static int da8xx_usb0_clk48_prepare(struct clk_hw *hw)
359 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
361 /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0
362 * PHY clock enable, but since clk_prepare() can't be called in an
363 * atomic context (i.e. in clk_enable()), we have to prepare it here.
365 return clk_prepare(usb0->fck);
368 static void da8xx_usb0_clk48_unprepare(struct clk_hw *hw)
370 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
372 clk_unprepare(usb0->fck);
375 static int da8xx_usb0_clk48_enable(struct clk_hw *hw)
377 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
378 unsigned int mask, val;
381 /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled
382 * temporaily. It can be turned back off once the PLL is locked.
384 clk_enable(usb0->fck);
386 /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
387 * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used.
389 mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON;
390 val = CFGCHIP2_PHY_PLLON;
392 regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
393 ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val,
394 val & CFGCHIP2_PHYCLKGD, 0, 500000);
396 clk_disable(usb0->fck);
401 static void da8xx_usb0_clk48_disable(struct clk_hw *hw)
403 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
406 val = CFGCHIP2_PHYPWRDN;
407 regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val);
410 static int da8xx_usb0_clk48_is_enabled(struct clk_hw *hw)
412 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
415 regmap_read(usb0->regmap, CFGCHIP(2), &val);
417 return !!(val & CFGCHIP2_PHYCLKGD);
420 static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
421 unsigned long parent_rate)
423 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
424 unsigned int mask, val;
426 /* The parent clock rate must be one of the following */
427 mask = CFGCHIP2_REFFREQ_MASK;
428 switch (parent_rate) {
430 val = CFGCHIP2_REFFREQ_12MHZ;
433 val = CFGCHIP2_REFFREQ_13MHZ;
436 val = CFGCHIP2_REFFREQ_19_2MHZ;
439 val = CFGCHIP2_REFFREQ_20MHZ;
442 val = CFGCHIP2_REFFREQ_24MHZ;
445 val = CFGCHIP2_REFFREQ_26MHZ;
448 val = CFGCHIP2_REFFREQ_38_4MHZ;
451 val = CFGCHIP2_REFFREQ_40MHZ;
454 val = CFGCHIP2_REFFREQ_48MHZ;
460 regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
462 /* USB 2.0 PLL always supplies 48MHz */
466 static long da8xx_usb0_clk48_round_rate(struct clk_hw *hw, unsigned long rate,
467 unsigned long *parent_rate)
472 static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index)
474 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
476 return regmap_write_bits(usb0->regmap, CFGCHIP(2),
477 CFGCHIP2_USB2PHYCLKMUX,
478 index ? CFGCHIP2_USB2PHYCLKMUX : 0);
481 static u8 da8xx_usb0_clk48_get_parent(struct clk_hw *hw)
483 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
486 regmap_read(usb0->regmap, CFGCHIP(2), &val);
488 return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0;
491 static const struct clk_ops da8xx_usb0_clk48_ops = {
492 .prepare = da8xx_usb0_clk48_prepare,
493 .unprepare = da8xx_usb0_clk48_unprepare,
494 .enable = da8xx_usb0_clk48_enable,
495 .disable = da8xx_usb0_clk48_disable,
496 .is_enabled = da8xx_usb0_clk48_is_enabled,
497 .recalc_rate = da8xx_usb0_clk48_recalc_rate,
498 .round_rate = da8xx_usb0_clk48_round_rate,
499 .set_parent = da8xx_usb0_clk48_set_parent,
500 .get_parent = da8xx_usb0_clk48_get_parent,
503 static struct da8xx_usb0_clk48 *
504 da8xx_cfgchip_register_usb0_clk48(struct device *dev,
505 struct regmap *regmap)
507 const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
509 struct da8xx_usb0_clk48 *usb0;
510 struct clk_init_data init;
513 fck_clk = devm_clk_get(dev, "fck");
514 if (IS_ERR(fck_clk)) {
515 if (PTR_ERR(fck_clk) != -EPROBE_DEFER)
516 dev_err(dev, "Missing fck clock\n");
517 return ERR_CAST(fck_clk);
520 usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL);
522 return ERR_PTR(-ENOMEM);
524 init.name = "usb0_clk48";
525 init.ops = &da8xx_usb0_clk48_ops;
526 init.parent_names = parent_names;
527 init.num_parents = 2;
529 usb0->hw.init = &init;
531 usb0->regmap = regmap;
533 ret = devm_clk_hw_register(dev, &usb0->hw);
540 /* --- USB 1.1 PHY clock --- */
542 struct da8xx_usb1_clk48 {
544 struct regmap *regmap;
547 #define to_da8xx_usb1_clk48(_hw) \
548 container_of((_hw), struct da8xx_usb1_clk48, hw)
550 static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index)
552 struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
554 return regmap_write_bits(usb1->regmap, CFGCHIP(2),
555 CFGCHIP2_USB1PHYCLKMUX,
556 index ? CFGCHIP2_USB1PHYCLKMUX : 0);
559 static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw)
561 struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
564 regmap_read(usb1->regmap, CFGCHIP(2), &val);
566 return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0;
569 static const struct clk_ops da8xx_usb1_clk48_ops = {
570 .set_parent = da8xx_usb1_clk48_set_parent,
571 .get_parent = da8xx_usb1_clk48_get_parent,
575 * da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock
576 * @regmap: The CFGCHIP regmap
578 static struct da8xx_usb1_clk48 *
579 da8xx_cfgchip_register_usb1_clk48(struct device *dev,
580 struct regmap *regmap)
582 const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
583 struct da8xx_usb1_clk48 *usb1;
584 struct clk_init_data init;
587 usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);
589 return ERR_PTR(-ENOMEM);
591 init.name = "usb1_clk48";
592 init.ops = &da8xx_usb1_clk48_ops;
593 init.parent_names = parent_names;
594 init.num_parents = 2;
596 usb1->hw.init = &init;
597 usb1->regmap = regmap;
599 ret = devm_clk_hw_register(dev, &usb1->hw);
606 static int da8xx_cfgchip_register_usb_phy_clk(struct device *dev,
607 struct regmap *regmap)
609 struct da8xx_usb0_clk48 *usb0;
610 struct da8xx_usb1_clk48 *usb1;
611 struct clk_hw *parent;
613 usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
615 return PTR_ERR(usb0);
618 * All existing boards use pll0_auxclk as the parent and new boards
619 * should use device tree, so hard-coding the value (1) here.
621 parent = clk_hw_get_parent_by_index(&usb0->hw, 1);
623 clk_set_parent(usb0->hw.clk, parent->clk);
625 dev_warn(dev, "Failed to find usb0 parent clock\n");
627 usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
629 return PTR_ERR(usb1);
632 * All existing boards use usb0_clk48 as the parent and new boards
633 * should use device tree, so hard-coding the value (0) here.
635 parent = clk_hw_get_parent_by_index(&usb1->hw, 0);
637 clk_set_parent(usb1->hw.clk, parent->clk);
639 dev_warn(dev, "Failed to find usb1 parent clock\n");
641 clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy");
642 clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy");
647 static int of_da8xx_usb_phy_clk_init(struct device *dev, struct regmap *regmap)
649 struct clk_hw_onecell_data *clk_data;
650 struct da8xx_usb0_clk48 *usb0;
651 struct da8xx_usb1_clk48 *usb1;
653 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, 2),
660 usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
662 if (PTR_ERR(usb0) == -EPROBE_DEFER)
663 return -EPROBE_DEFER;
665 dev_warn(dev, "Failed to register usb0_clk48 (%ld)\n",
668 clk_data->hws[0] = ERR_PTR(-ENOENT);
670 clk_data->hws[0] = &usb0->hw;
673 usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
675 if (PTR_ERR(usb1) == -EPROBE_DEFER)
676 return -EPROBE_DEFER;
678 dev_warn(dev, "Failed to register usb1_clk48 (%ld)\n",
681 clk_data->hws[1] = ERR_PTR(-ENOENT);
683 clk_data->hws[1] = &usb1->hw;
686 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
689 /* --- platform device --- */
691 static const struct of_device_id da8xx_cfgchip_of_match[] = {
693 .compatible = "ti,da830-tbclksync",
694 .data = of_da8xx_tbclksync_init,
697 .compatible = "ti,da830-div4p5ena",
698 .data = of_da8xx_div4p5ena_init,
701 .compatible = "ti,da850-async1-clksrc",
702 .data = of_da850_async1_init,
705 .compatible = "ti,da850-async3-clksrc",
706 .data = of_da850_async3_init,
709 .compatible = "ti,da830-usb-phy-clocks",
710 .data = of_da8xx_usb_phy_clk_init,
715 static const struct platform_device_id da8xx_cfgchip_id_table[] = {
717 .name = "da830-tbclksync",
718 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk,
721 .name = "da830-div4p5ena",
722 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5,
725 .name = "da850-async1-clksrc",
726 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1,
729 .name = "da850-async3-clksrc",
730 .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3,
733 .name = "da830-usb-phy-clks",
734 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_usb_phy_clk,
739 typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap);
741 static int da8xx_cfgchip_probe(struct platform_device *pdev)
743 struct device *dev = &pdev->dev;
744 struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data;
745 const struct of_device_id *of_id;
746 da8xx_cfgchip_init clk_init = NULL;
747 struct regmap *regmap = NULL;
749 of_id = of_match_device(da8xx_cfgchip_of_match, dev);
751 struct device_node *parent;
753 clk_init = of_id->data;
754 parent = of_get_parent(dev->of_node);
755 regmap = syscon_node_to_regmap(parent);
757 } else if (pdev->id_entry && pdata) {
758 clk_init = (void *)pdev->id_entry->driver_data;
759 regmap = pdata->cfgchip;
763 dev_err(dev, "unable to find driver data\n");
767 if (IS_ERR_OR_NULL(regmap)) {
768 dev_err(dev, "no regmap for CFGCHIP syscon\n");
769 return regmap ? PTR_ERR(regmap) : -ENOENT;
772 return clk_init(dev, regmap);
775 static struct platform_driver da8xx_cfgchip_driver = {
776 .probe = da8xx_cfgchip_probe,
778 .name = "da8xx-cfgchip-clk",
779 .of_match_table = da8xx_cfgchip_of_match,
781 .id_table = da8xx_cfgchip_id_table,
784 static int __init da8xx_cfgchip_driver_init(void)
786 return platform_driver_register(&da8xx_cfgchip_driver);
789 /* has to be postcore_initcall because PSC devices depend on the async3 clock */
790 postcore_initcall(da8xx_cfgchip_driver_init);