GNU Linux-libre 4.4.289-gnu1
[releases.git] / drivers / clk / clk-wm831x.c
1 /*
2  * WM831x clock control
3  *
4  * Copyright 2011-2 Wolfson Microelectronics PLC.
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  *  This program is free software; you can redistribute  it and/or modify it
9  *  under  the terms of  the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the  License, or (at your
11  *  option) any later version.
12  *
13  */
14
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/platform_device.h>
20 #include <linux/mfd/wm831x/core.h>
21
22 struct wm831x_clk {
23         struct wm831x *wm831x;
24         struct clk_hw xtal_hw;
25         struct clk_hw fll_hw;
26         struct clk_hw clkout_hw;
27         struct clk *xtal;
28         struct clk *fll;
29         struct clk *clkout;
30         bool xtal_ena;
31 };
32
33 static int wm831x_xtal_is_prepared(struct clk_hw *hw)
34 {
35         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
36                                                   xtal_hw);
37
38         return clkdata->xtal_ena;
39 }
40
41 static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
42                                              unsigned long parent_rate)
43 {
44         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
45                                                   xtal_hw);
46
47         if (clkdata->xtal_ena)
48                 return 32768;
49         else
50                 return 0;
51 }
52
53 static const struct clk_ops wm831x_xtal_ops = {
54         .is_prepared = wm831x_xtal_is_prepared,
55         .recalc_rate = wm831x_xtal_recalc_rate,
56 };
57
58 static struct clk_init_data wm831x_xtal_init = {
59         .name = "xtal",
60         .ops = &wm831x_xtal_ops,
61         .flags = CLK_IS_ROOT,
62 };
63
64 static const unsigned long wm831x_fll_auto_rates[] = {
65          2048000,
66         11289600,
67         12000000,
68         12288000,
69         19200000,
70         22579600,
71         24000000,
72         24576000,
73 };
74
75 static int wm831x_fll_is_prepared(struct clk_hw *hw)
76 {
77         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
78                                                   fll_hw);
79         struct wm831x *wm831x = clkdata->wm831x;
80         int ret;
81
82         ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
83         if (ret < 0) {
84                 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
85                         ret);
86                 return true;
87         }
88
89         return (ret & WM831X_FLL_ENA) != 0;
90 }
91
92 static int wm831x_fll_prepare(struct clk_hw *hw)
93 {
94         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
95                                                   fll_hw);
96         struct wm831x *wm831x = clkdata->wm831x;
97         int ret;
98
99         ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
100                               WM831X_FLL_ENA, WM831X_FLL_ENA);
101         if (ret != 0)
102                 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
103
104         usleep_range(2000, 2000);
105
106         return ret;
107 }
108
109 static void wm831x_fll_unprepare(struct clk_hw *hw)
110 {
111         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
112                                                   fll_hw);
113         struct wm831x *wm831x = clkdata->wm831x;
114         int ret;
115
116         ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
117         if (ret != 0)
118                 dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
119 }
120
121 static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
122                                             unsigned long parent_rate)
123 {
124         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
125                                                   fll_hw);
126         struct wm831x *wm831x = clkdata->wm831x;
127         int ret;
128
129         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
130         if (ret < 0) {
131                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
132                         ret);
133                 return 0;
134         }
135
136         if (ret & WM831X_FLL_AUTO)
137                 return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
138
139         dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
140
141         return 0;
142 }
143
144 static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
145                                   unsigned long *unused)
146 {
147         int best = 0;
148         int i;
149
150         for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
151                 if (abs(wm831x_fll_auto_rates[i] - rate) <
152                     abs(wm831x_fll_auto_rates[best] - rate))
153                         best = i;
154
155         return wm831x_fll_auto_rates[best];
156 }
157
158 static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
159                                unsigned long parent_rate)
160 {
161         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
162                                                   fll_hw);
163         struct wm831x *wm831x = clkdata->wm831x;
164         int i;
165
166         for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
167                 if (wm831x_fll_auto_rates[i] == rate)
168                         break;
169         if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
170                 return -EINVAL;
171
172         if (wm831x_fll_is_prepared(hw))
173                 return -EPERM;
174
175         return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
176                                WM831X_FLL_AUTO_FREQ_MASK, i);
177 }
178
179 static const char *wm831x_fll_parents[] = {
180         "xtal",
181         "clkin",
182 };
183
184 static u8 wm831x_fll_get_parent(struct clk_hw *hw)
185 {
186         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
187                                                   fll_hw);
188         struct wm831x *wm831x = clkdata->wm831x;
189         int ret;
190
191         /* AUTO mode is always clocked from the crystal */
192         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
193         if (ret < 0) {
194                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
195                         ret);
196                 return 0;
197         }
198
199         if (ret & WM831X_FLL_AUTO)
200                 return 0;
201
202         ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
203         if (ret < 0) {
204                 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
205                         ret);
206                 return 0;
207         }
208
209         switch (ret & WM831X_FLL_CLK_SRC_MASK) {
210         case 0:
211                 return 0;
212         case 1:
213                 return 1;
214         default:
215                 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
216                         ret & WM831X_FLL_CLK_SRC_MASK);
217                 return 0;
218         }
219 }
220
221 static const struct clk_ops wm831x_fll_ops = {
222         .is_prepared = wm831x_fll_is_prepared,
223         .prepare = wm831x_fll_prepare,
224         .unprepare = wm831x_fll_unprepare,
225         .round_rate = wm831x_fll_round_rate,
226         .recalc_rate = wm831x_fll_recalc_rate,
227         .set_rate = wm831x_fll_set_rate,
228         .get_parent = wm831x_fll_get_parent,
229 };
230
231 static struct clk_init_data wm831x_fll_init = {
232         .name = "fll",
233         .ops = &wm831x_fll_ops,
234         .parent_names = wm831x_fll_parents,
235         .num_parents = ARRAY_SIZE(wm831x_fll_parents),
236         .flags = CLK_SET_RATE_GATE,
237 };
238
239 static int wm831x_clkout_is_prepared(struct clk_hw *hw)
240 {
241         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
242                                                   clkout_hw);
243         struct wm831x *wm831x = clkdata->wm831x;
244         int ret;
245
246         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
247         if (ret < 0) {
248                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
249                         ret);
250                 return false;
251         }
252
253         return (ret & WM831X_CLKOUT_ENA) != 0;
254 }
255
256 static int wm831x_clkout_prepare(struct clk_hw *hw)
257 {
258         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
259                                                   clkout_hw);
260         struct wm831x *wm831x = clkdata->wm831x;
261         int ret;
262
263         ret = wm831x_reg_unlock(wm831x);
264         if (ret != 0) {
265                 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
266                 return ret;
267         }
268
269         ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
270                               WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
271         if (ret != 0)
272                 dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
273
274         wm831x_reg_lock(wm831x);
275
276         return ret;
277 }
278
279 static void wm831x_clkout_unprepare(struct clk_hw *hw)
280 {
281         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
282                                                   clkout_hw);
283         struct wm831x *wm831x = clkdata->wm831x;
284         int ret;
285
286         ret = wm831x_reg_unlock(wm831x);
287         if (ret != 0) {
288                 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
289                 return;
290         }
291
292         ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
293                               WM831X_CLKOUT_ENA, 0);
294         if (ret != 0)
295                 dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
296
297         wm831x_reg_lock(wm831x);
298 }
299
300 static const char *wm831x_clkout_parents[] = {
301         "fll",
302         "xtal",
303 };
304
305 static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
306 {
307         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
308                                                   clkout_hw);
309         struct wm831x *wm831x = clkdata->wm831x;
310         int ret;
311
312         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
313         if (ret < 0) {
314                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
315                         ret);
316                 return 0;
317         }
318
319         if (ret & WM831X_CLKOUT_SRC)
320                 return 1;
321         else
322                 return 0;
323 }
324
325 static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
326 {
327         struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
328                                                   clkout_hw);
329         struct wm831x *wm831x = clkdata->wm831x;
330
331         return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
332                                WM831X_CLKOUT_SRC,
333                                parent << WM831X_CLKOUT_SRC_SHIFT);
334 }
335
336 static const struct clk_ops wm831x_clkout_ops = {
337         .is_prepared = wm831x_clkout_is_prepared,
338         .prepare = wm831x_clkout_prepare,
339         .unprepare = wm831x_clkout_unprepare,
340         .get_parent = wm831x_clkout_get_parent,
341         .set_parent = wm831x_clkout_set_parent,
342 };
343
344 static struct clk_init_data wm831x_clkout_init = {
345         .name = "clkout",
346         .ops = &wm831x_clkout_ops,
347         .parent_names = wm831x_clkout_parents,
348         .num_parents = ARRAY_SIZE(wm831x_clkout_parents),
349         .flags = CLK_SET_RATE_PARENT,
350 };
351
352 static int wm831x_clk_probe(struct platform_device *pdev)
353 {
354         struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
355         struct wm831x_clk *clkdata;
356         int ret;
357
358         clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
359         if (!clkdata)
360                 return -ENOMEM;
361
362         clkdata->wm831x = wm831x;
363
364         /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
365         ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
366         if (ret < 0) {
367                 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
368                         ret);
369                 return ret;
370         }
371         clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
372
373         clkdata->xtal_hw.init = &wm831x_xtal_init;
374         clkdata->xtal = devm_clk_register(&pdev->dev, &clkdata->xtal_hw);
375         if (IS_ERR(clkdata->xtal))
376                 return PTR_ERR(clkdata->xtal);
377
378         clkdata->fll_hw.init = &wm831x_fll_init;
379         clkdata->fll = devm_clk_register(&pdev->dev, &clkdata->fll_hw);
380         if (IS_ERR(clkdata->fll))
381                 return PTR_ERR(clkdata->fll);
382
383         clkdata->clkout_hw.init = &wm831x_clkout_init;
384         clkdata->clkout = devm_clk_register(&pdev->dev, &clkdata->clkout_hw);
385         if (IS_ERR(clkdata->clkout))
386                 return PTR_ERR(clkdata->clkout);
387
388         platform_set_drvdata(pdev, clkdata);
389
390         return 0;
391 }
392
393 static struct platform_driver wm831x_clk_driver = {
394         .probe = wm831x_clk_probe,
395         .driver         = {
396                 .name   = "wm831x-clk",
397         },
398 };
399
400 module_platform_driver(wm831x_clk_driver);
401
402 /* Module information */
403 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
404 MODULE_DESCRIPTION("WM831x clock driver");
405 MODULE_LICENSE("GPL");
406 MODULE_ALIAS("platform:wm831x-clk");