GNU Linux-libre 4.4.289-gnu1
[releases.git] / drivers / clk / clk-si5351.c
1 /*
2  * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
3  *
4  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5  * Rabeeh Khoury <rabeeh@solid-run.com>
6  *
7  * References:
8  * [1] "Si5351A/B/C Data Sheet"
9  *     http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
10  * [2] "Manually Generating an Si5351 Register Map"
11  *     http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
12  *
13  * This program is free software; you can redistribute  it and/or modify it
14  * under  the terms of  the GNU General  Public License as published by the
15  * Free Software Foundation;  either version 2 of the  License, or (at your
16  * option) any later version.
17  */
18
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/errno.h>
26 #include <linux/rational.h>
27 #include <linux/i2c.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_data/si5351.h>
30 #include <linux/regmap.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <asm/div64.h>
34
35 #include "clk-si5351.h"
36
37 struct si5351_driver_data;
38
39 struct si5351_parameters {
40         unsigned long   p1;
41         unsigned long   p2;
42         unsigned long   p3;
43         int             valid;
44 };
45
46 struct si5351_hw_data {
47         struct clk_hw                   hw;
48         struct si5351_driver_data       *drvdata;
49         struct si5351_parameters        params;
50         unsigned char                   num;
51 };
52
53 struct si5351_driver_data {
54         enum si5351_variant     variant;
55         struct i2c_client       *client;
56         struct regmap           *regmap;
57         struct clk_onecell_data onecell;
58
59         struct clk              *pxtal;
60         const char              *pxtal_name;
61         struct clk_hw           xtal;
62         struct clk              *pclkin;
63         const char              *pclkin_name;
64         struct clk_hw           clkin;
65
66         struct si5351_hw_data   pll[2];
67         struct si5351_hw_data   *msynth;
68         struct si5351_hw_data   *clkout;
69 };
70
71 static const char * const si5351_input_names[] = {
72         "xtal", "clkin"
73 };
74 static const char * const si5351_pll_names[] = {
75         "si5351_plla", "si5351_pllb", "si5351_vxco"
76 };
77 static const char * const si5351_msynth_names[] = {
78         "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
79 };
80 static const char * const si5351_clkout_names[] = {
81         "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
82 };
83
84 /*
85  * Si5351 i2c regmap
86  */
87 static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
88 {
89         u32 val;
90         int ret;
91
92         ret = regmap_read(drvdata->regmap, reg, &val);
93         if (ret) {
94                 dev_err(&drvdata->client->dev,
95                         "unable to read from reg%02x\n", reg);
96                 return 0;
97         }
98
99         return (u8)val;
100 }
101
102 static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
103                                    u8 reg, u8 count, u8 *buf)
104 {
105         return regmap_bulk_read(drvdata->regmap, reg, buf, count);
106 }
107
108 static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
109                                    u8 reg, u8 val)
110 {
111         return regmap_write(drvdata->regmap, reg, val);
112 }
113
114 static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
115                                     u8 reg, u8 count, const u8 *buf)
116 {
117         return regmap_raw_write(drvdata->regmap, reg, buf, count);
118 }
119
120 static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
121                                   u8 reg, u8 mask, u8 val)
122 {
123         return regmap_update_bits(drvdata->regmap, reg, mask, val);
124 }
125
126 static inline u8 si5351_msynth_params_address(int num)
127 {
128         if (num > 5)
129                 return SI5351_CLK6_PARAMETERS + (num - 6);
130         return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
131 }
132
133 static void si5351_read_parameters(struct si5351_driver_data *drvdata,
134                                    u8 reg, struct si5351_parameters *params)
135 {
136         u8 buf[SI5351_PARAMETERS_LENGTH];
137
138         switch (reg) {
139         case SI5351_CLK6_PARAMETERS:
140         case SI5351_CLK7_PARAMETERS:
141                 buf[0] = si5351_reg_read(drvdata, reg);
142                 params->p1 = buf[0];
143                 params->p2 = 0;
144                 params->p3 = 1;
145                 break;
146         default:
147                 si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
148                 params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
149                 params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
150                 params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
151         }
152         params->valid = 1;
153 }
154
155 static void si5351_write_parameters(struct si5351_driver_data *drvdata,
156                                     u8 reg, struct si5351_parameters *params)
157 {
158         u8 buf[SI5351_PARAMETERS_LENGTH];
159
160         switch (reg) {
161         case SI5351_CLK6_PARAMETERS:
162         case SI5351_CLK7_PARAMETERS:
163                 buf[0] = params->p1 & 0xff;
164                 si5351_reg_write(drvdata, reg, buf[0]);
165                 break;
166         default:
167                 buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
168                 buf[1] = params->p3 & 0xff;
169                 /* save rdiv and divby4 */
170                 buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
171                 buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
172                 buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
173                 buf[4] = params->p1 & 0xff;
174                 buf[5] = ((params->p3 & 0xf0000) >> 12) |
175                         ((params->p2 & 0xf0000) >> 16);
176                 buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
177                 buf[7] = params->p2 & 0xff;
178                 si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
179         }
180 }
181
182 static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
183 {
184         switch (reg) {
185         case SI5351_DEVICE_STATUS:
186         case SI5351_INTERRUPT_STATUS:
187         case SI5351_PLL_RESET:
188                 return true;
189         }
190         return false;
191 }
192
193 static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
194 {
195         /* reserved registers */
196         if (reg >= 4 && reg <= 8)
197                 return false;
198         if (reg >= 10 && reg <= 14)
199                 return false;
200         if (reg >= 173 && reg <= 176)
201                 return false;
202         if (reg >= 178 && reg <= 182)
203                 return false;
204         /* read-only */
205         if (reg == SI5351_DEVICE_STATUS)
206                 return false;
207         return true;
208 }
209
210 static const struct regmap_config si5351_regmap_config = {
211         .reg_bits = 8,
212         .val_bits = 8,
213         .cache_type = REGCACHE_RBTREE,
214         .max_register = 187,
215         .writeable_reg = si5351_regmap_is_writeable,
216         .volatile_reg = si5351_regmap_is_volatile,
217 };
218
219 /*
220  * Si5351 xtal clock input
221  */
222 static int si5351_xtal_prepare(struct clk_hw *hw)
223 {
224         struct si5351_driver_data *drvdata =
225                 container_of(hw, struct si5351_driver_data, xtal);
226         si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
227                         SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
228         return 0;
229 }
230
231 static void si5351_xtal_unprepare(struct clk_hw *hw)
232 {
233         struct si5351_driver_data *drvdata =
234                 container_of(hw, struct si5351_driver_data, xtal);
235         si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
236                         SI5351_XTAL_ENABLE, 0);
237 }
238
239 static const struct clk_ops si5351_xtal_ops = {
240         .prepare = si5351_xtal_prepare,
241         .unprepare = si5351_xtal_unprepare,
242 };
243
244 /*
245  * Si5351 clkin clock input (Si5351C only)
246  */
247 static int si5351_clkin_prepare(struct clk_hw *hw)
248 {
249         struct si5351_driver_data *drvdata =
250                 container_of(hw, struct si5351_driver_data, clkin);
251         si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
252                         SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
253         return 0;
254 }
255
256 static void si5351_clkin_unprepare(struct clk_hw *hw)
257 {
258         struct si5351_driver_data *drvdata =
259                 container_of(hw, struct si5351_driver_data, clkin);
260         si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
261                         SI5351_CLKIN_ENABLE, 0);
262 }
263
264 /*
265  * CMOS clock source constraints:
266  * The input frequency range of the PLL is 10Mhz to 40MHz.
267  * If CLKIN is >40MHz, the input divider must be used.
268  */
269 static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
270                                               unsigned long parent_rate)
271 {
272         struct si5351_driver_data *drvdata =
273                 container_of(hw, struct si5351_driver_data, clkin);
274         unsigned long rate;
275         unsigned char idiv;
276
277         rate = parent_rate;
278         if (parent_rate > 160000000) {
279                 idiv = SI5351_CLKIN_DIV_8;
280                 rate /= 8;
281         } else if (parent_rate > 80000000) {
282                 idiv = SI5351_CLKIN_DIV_4;
283                 rate /= 4;
284         } else if (parent_rate > 40000000) {
285                 idiv = SI5351_CLKIN_DIV_2;
286                 rate /= 2;
287         } else {
288                 idiv = SI5351_CLKIN_DIV_1;
289         }
290
291         si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
292                         SI5351_CLKIN_DIV_MASK, idiv);
293
294         dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
295                 __func__, (1 << (idiv >> 6)), rate);
296
297         return rate;
298 }
299
300 static const struct clk_ops si5351_clkin_ops = {
301         .prepare = si5351_clkin_prepare,
302         .unprepare = si5351_clkin_unprepare,
303         .recalc_rate = si5351_clkin_recalc_rate,
304 };
305
306 /*
307  * Si5351 vxco clock input (Si5351B only)
308  */
309
310 static int si5351_vxco_prepare(struct clk_hw *hw)
311 {
312         struct si5351_hw_data *hwdata =
313                 container_of(hw, struct si5351_hw_data, hw);
314
315         dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
316
317         return 0;
318 }
319
320 static void si5351_vxco_unprepare(struct clk_hw *hw)
321 {
322 }
323
324 static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
325                                              unsigned long parent_rate)
326 {
327         return 0;
328 }
329
330 static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
331                                 unsigned long parent)
332 {
333         return 0;
334 }
335
336 static const struct clk_ops si5351_vxco_ops = {
337         .prepare = si5351_vxco_prepare,
338         .unprepare = si5351_vxco_unprepare,
339         .recalc_rate = si5351_vxco_recalc_rate,
340         .set_rate = si5351_vxco_set_rate,
341 };
342
343 /*
344  * Si5351 pll a/b
345  *
346  * Feedback Multisynth Divider Equations [2]
347  *
348  * fVCO = fIN * (a + b/c)
349  *
350  * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
351  * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
352  *
353  * Feedback Multisynth Register Equations
354  *
355  * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
356  * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
357  * (3) MSNx_P3[19:0] = c
358  *
359  * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
360  *
361  * Using (4) on (1) yields:
362  * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
363  * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
364  *
365  * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
366  *         = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
367  *
368  */
369 static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
370                                 int num, enum si5351_pll_src parent)
371 {
372         u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
373
374         if (parent == SI5351_PLL_SRC_DEFAULT)
375                 return 0;
376
377         if (num > 2)
378                 return -EINVAL;
379
380         if (drvdata->variant != SI5351_VARIANT_C &&
381             parent != SI5351_PLL_SRC_XTAL)
382                 return -EINVAL;
383
384         si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
385                         (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
386         return 0;
387 }
388
389 static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
390 {
391         struct si5351_hw_data *hwdata =
392                 container_of(hw, struct si5351_hw_data, hw);
393         u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
394         u8 val;
395
396         val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
397
398         return (val & mask) ? 1 : 0;
399 }
400
401 static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
402 {
403         struct si5351_hw_data *hwdata =
404                 container_of(hw, struct si5351_hw_data, hw);
405
406         if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
407             index > 0)
408                 return -EPERM;
409
410         if (index > 1)
411                 return -EINVAL;
412
413         return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
414                              (index == 0) ? SI5351_PLL_SRC_XTAL :
415                              SI5351_PLL_SRC_CLKIN);
416 }
417
418 static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
419                                             unsigned long parent_rate)
420 {
421         struct si5351_hw_data *hwdata =
422                 container_of(hw, struct si5351_hw_data, hw);
423         u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
424                 SI5351_PLLB_PARAMETERS;
425         unsigned long long rate;
426
427         if (!hwdata->params.valid)
428                 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
429
430         if (hwdata->params.p3 == 0)
431                 return parent_rate;
432
433         /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
434         rate  = hwdata->params.p1 * hwdata->params.p3;
435         rate += 512 * hwdata->params.p3;
436         rate += hwdata->params.p2;
437         rate *= parent_rate;
438         do_div(rate, 128 * hwdata->params.p3);
439
440         dev_dbg(&hwdata->drvdata->client->dev,
441                 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
442                 __func__, clk_hw_get_name(hw),
443                 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
444                 parent_rate, (unsigned long)rate);
445
446         return (unsigned long)rate;
447 }
448
449 static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
450                                   unsigned long *parent_rate)
451 {
452         struct si5351_hw_data *hwdata =
453                 container_of(hw, struct si5351_hw_data, hw);
454         unsigned long rfrac, denom, a, b, c;
455         unsigned long long lltmp;
456
457         if (rate < SI5351_PLL_VCO_MIN)
458                 rate = SI5351_PLL_VCO_MIN;
459         if (rate > SI5351_PLL_VCO_MAX)
460                 rate = SI5351_PLL_VCO_MAX;
461
462         /* determine integer part of feedback equation */
463         a = rate / *parent_rate;
464
465         if (a < SI5351_PLL_A_MIN)
466                 rate = *parent_rate * SI5351_PLL_A_MIN;
467         if (a > SI5351_PLL_A_MAX)
468                 rate = *parent_rate * SI5351_PLL_A_MAX;
469
470         /* find best approximation for b/c = fVCO mod fIN */
471         denom = 1000 * 1000;
472         lltmp = rate % (*parent_rate);
473         lltmp *= denom;
474         do_div(lltmp, *parent_rate);
475         rfrac = (unsigned long)lltmp;
476
477         b = 0;
478         c = 1;
479         if (rfrac)
480                 rational_best_approximation(rfrac, denom,
481                                     SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
482
483         /* calculate parameters */
484         hwdata->params.p3  = c;
485         hwdata->params.p2  = (128 * b) % c;
486         hwdata->params.p1  = 128 * a;
487         hwdata->params.p1 += (128 * b / c);
488         hwdata->params.p1 -= 512;
489
490         /* recalculate rate by fIN * (a + b/c) */
491         lltmp  = *parent_rate;
492         lltmp *= b;
493         do_div(lltmp, c);
494
495         rate  = (unsigned long)lltmp;
496         rate += *parent_rate * a;
497
498         dev_dbg(&hwdata->drvdata->client->dev,
499                 "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
500                 __func__, clk_hw_get_name(hw), a, b, c,
501                 *parent_rate, rate);
502
503         return rate;
504 }
505
506 static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
507                                unsigned long parent_rate)
508 {
509         struct si5351_hw_data *hwdata =
510                 container_of(hw, struct si5351_hw_data, hw);
511         u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
512                 SI5351_PLLB_PARAMETERS;
513
514         /* write multisynth parameters */
515         si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
516
517         /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
518         si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
519                 SI5351_CLK_INTEGER_MODE,
520                 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
521
522         dev_dbg(&hwdata->drvdata->client->dev,
523                 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
524                 __func__, clk_hw_get_name(hw),
525                 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
526                 parent_rate, rate);
527
528         return 0;
529 }
530
531 static const struct clk_ops si5351_pll_ops = {
532         .set_parent = si5351_pll_set_parent,
533         .get_parent = si5351_pll_get_parent,
534         .recalc_rate = si5351_pll_recalc_rate,
535         .round_rate = si5351_pll_round_rate,
536         .set_rate = si5351_pll_set_rate,
537 };
538
539 /*
540  * Si5351 multisync divider
541  *
542  * for fOUT <= 150 MHz:
543  *
544  * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
545  *
546  * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
547  * fIN = fVCO0, fVCO1
548  *
549  * Output Clock Multisynth Register Equations
550  *
551  * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
552  * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
553  * MSx_P3[19:0] = c
554  *
555  * MS[6,7] are integer (P1) divide only, P1 = divide value,
556  * P2 and P3 are not applicable
557  *
558  * for 150MHz < fOUT <= 160MHz:
559  *
560  * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
561  */
562 static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
563                                    int num, enum si5351_multisynth_src parent)
564 {
565         if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
566                 return 0;
567
568         if (num > 8)
569                 return -EINVAL;
570
571         si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
572                         (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
573                         SI5351_CLK_PLL_SELECT);
574         return 0;
575 }
576
577 static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
578 {
579         struct si5351_hw_data *hwdata =
580                 container_of(hw, struct si5351_hw_data, hw);
581         u8 val;
582
583         val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
584
585         return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
586 }
587
588 static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
589 {
590         struct si5351_hw_data *hwdata =
591                 container_of(hw, struct si5351_hw_data, hw);
592
593         return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
594                                (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
595                                SI5351_MULTISYNTH_SRC_VCO1);
596 }
597
598 static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
599                                                unsigned long parent_rate)
600 {
601         struct si5351_hw_data *hwdata =
602                 container_of(hw, struct si5351_hw_data, hw);
603         u8 reg = si5351_msynth_params_address(hwdata->num);
604         unsigned long long rate;
605         unsigned long m;
606
607         if (!hwdata->params.valid)
608                 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
609
610         /*
611          * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
612          * multisync6-7: fOUT = fIN / P1
613          */
614         rate = parent_rate;
615         if (hwdata->num > 5) {
616                 m = hwdata->params.p1;
617         } else if (hwdata->params.p3 == 0) {
618                 return parent_rate;
619         } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
620                     SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
621                 m = 4;
622         } else {
623                 rate *= 128 * hwdata->params.p3;
624                 m = hwdata->params.p1 * hwdata->params.p3;
625                 m += hwdata->params.p2;
626                 m += 512 * hwdata->params.p3;
627         }
628
629         if (m == 0)
630                 return 0;
631         do_div(rate, m);
632
633         dev_dbg(&hwdata->drvdata->client->dev,
634                 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
635                 __func__, clk_hw_get_name(hw),
636                 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
637                 m, parent_rate, (unsigned long)rate);
638
639         return (unsigned long)rate;
640 }
641
642 static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
643                                      unsigned long *parent_rate)
644 {
645         struct si5351_hw_data *hwdata =
646                 container_of(hw, struct si5351_hw_data, hw);
647         unsigned long long lltmp;
648         unsigned long a, b, c;
649         int divby4;
650
651         /* multisync6-7 can only handle freqencies < 150MHz */
652         if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
653                 rate = SI5351_MULTISYNTH67_MAX_FREQ;
654
655         /* multisync frequency is 1MHz .. 160MHz */
656         if (rate > SI5351_MULTISYNTH_MAX_FREQ)
657                 rate = SI5351_MULTISYNTH_MAX_FREQ;
658         if (rate < SI5351_MULTISYNTH_MIN_FREQ)
659                 rate = SI5351_MULTISYNTH_MIN_FREQ;
660
661         divby4 = 0;
662         if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
663                 divby4 = 1;
664
665         /* multisync can set pll */
666         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
667                 /*
668                  * find largest integer divider for max
669                  * vco frequency and given target rate
670                  */
671                 if (divby4 == 0) {
672                         lltmp = SI5351_PLL_VCO_MAX;
673                         do_div(lltmp, rate);
674                         a = (unsigned long)lltmp;
675                 } else
676                         a = 4;
677
678                 b = 0;
679                 c = 1;
680
681                 *parent_rate = a * rate;
682         } else if (hwdata->num >= 6) {
683                 /* determine the closest integer divider */
684                 a = DIV_ROUND_CLOSEST(*parent_rate, rate);
685                 if (a < SI5351_MULTISYNTH_A_MIN)
686                         a = SI5351_MULTISYNTH_A_MIN;
687                 if (a > SI5351_MULTISYNTH67_A_MAX)
688                         a = SI5351_MULTISYNTH67_A_MAX;
689
690                 b = 0;
691                 c = 1;
692         } else {
693                 unsigned long rfrac, denom;
694
695                 /* disable divby4 */
696                 if (divby4) {
697                         rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
698                         divby4 = 0;
699                 }
700
701                 /* determine integer part of divider equation */
702                 a = *parent_rate / rate;
703                 if (a < SI5351_MULTISYNTH_A_MIN)
704                         a = SI5351_MULTISYNTH_A_MIN;
705                 if (a > SI5351_MULTISYNTH_A_MAX)
706                         a = SI5351_MULTISYNTH_A_MAX;
707
708                 /* find best approximation for b/c = fVCO mod fOUT */
709                 denom = 1000 * 1000;
710                 lltmp = (*parent_rate) % rate;
711                 lltmp *= denom;
712                 do_div(lltmp, rate);
713                 rfrac = (unsigned long)lltmp;
714
715                 b = 0;
716                 c = 1;
717                 if (rfrac)
718                         rational_best_approximation(rfrac, denom,
719                             SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
720                             &b, &c);
721         }
722
723         /* recalculate rate by fOUT = fIN / (a + b/c) */
724         lltmp  = *parent_rate;
725         lltmp *= c;
726         do_div(lltmp, a * c + b);
727         rate  = (unsigned long)lltmp;
728
729         /* calculate parameters */
730         if (divby4) {
731                 hwdata->params.p3 = 1;
732                 hwdata->params.p2 = 0;
733                 hwdata->params.p1 = 0;
734         } else if (hwdata->num >= 6) {
735                 hwdata->params.p3 = 0;
736                 hwdata->params.p2 = 0;
737                 hwdata->params.p1 = a;
738         } else {
739                 hwdata->params.p3  = c;
740                 hwdata->params.p2  = (128 * b) % c;
741                 hwdata->params.p1  = 128 * a;
742                 hwdata->params.p1 += (128 * b / c);
743                 hwdata->params.p1 -= 512;
744         }
745
746         dev_dbg(&hwdata->drvdata->client->dev,
747                 "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
748                 __func__, clk_hw_get_name(hw), a, b, c, divby4,
749                 *parent_rate, rate);
750
751         return rate;
752 }
753
754 static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
755                                   unsigned long parent_rate)
756 {
757         struct si5351_hw_data *hwdata =
758                 container_of(hw, struct si5351_hw_data, hw);
759         u8 reg = si5351_msynth_params_address(hwdata->num);
760         int divby4 = 0;
761
762         /* write multisynth parameters */
763         si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
764
765         if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
766                 divby4 = 1;
767
768         /* enable/disable integer mode and divby4 on multisynth0-5 */
769         if (hwdata->num < 6) {
770                 si5351_set_bits(hwdata->drvdata, reg + 2,
771                                 SI5351_OUTPUT_CLK_DIVBY4,
772                                 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
773                 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
774                         SI5351_CLK_INTEGER_MODE,
775                         (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
776         }
777
778         dev_dbg(&hwdata->drvdata->client->dev,
779                 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
780                 __func__, clk_hw_get_name(hw),
781                 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
782                 divby4, parent_rate, rate);
783
784         return 0;
785 }
786
787 static const struct clk_ops si5351_msynth_ops = {
788         .set_parent = si5351_msynth_set_parent,
789         .get_parent = si5351_msynth_get_parent,
790         .recalc_rate = si5351_msynth_recalc_rate,
791         .round_rate = si5351_msynth_round_rate,
792         .set_rate = si5351_msynth_set_rate,
793 };
794
795 /*
796  * Si5351 clkout divider
797  */
798 static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
799                                    int num, enum si5351_clkout_src parent)
800 {
801         u8 val;
802
803         if (num > 8)
804                 return -EINVAL;
805
806         switch (parent) {
807         case SI5351_CLKOUT_SRC_MSYNTH_N:
808                 val = SI5351_CLK_INPUT_MULTISYNTH_N;
809                 break;
810         case SI5351_CLKOUT_SRC_MSYNTH_0_4:
811                 /* clk0/clk4 can only connect to its own multisync */
812                 if (num == 0 || num == 4)
813                         val = SI5351_CLK_INPUT_MULTISYNTH_N;
814                 else
815                         val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
816                 break;
817         case SI5351_CLKOUT_SRC_XTAL:
818                 val = SI5351_CLK_INPUT_XTAL;
819                 break;
820         case SI5351_CLKOUT_SRC_CLKIN:
821                 if (drvdata->variant != SI5351_VARIANT_C)
822                         return -EINVAL;
823
824                 val = SI5351_CLK_INPUT_CLKIN;
825                 break;
826         default:
827                 return 0;
828         }
829
830         si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
831                         SI5351_CLK_INPUT_MASK, val);
832         return 0;
833 }
834
835 static int _si5351_clkout_set_drive_strength(
836         struct si5351_driver_data *drvdata, int num,
837         enum si5351_drive_strength drive)
838 {
839         u8 mask;
840
841         if (num > 8)
842                 return -EINVAL;
843
844         switch (drive) {
845         case SI5351_DRIVE_2MA:
846                 mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
847                 break;
848         case SI5351_DRIVE_4MA:
849                 mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
850                 break;
851         case SI5351_DRIVE_6MA:
852                 mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
853                 break;
854         case SI5351_DRIVE_8MA:
855                 mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
856                 break;
857         default:
858                 return 0;
859         }
860
861         si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
862                         SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
863         return 0;
864 }
865
866 static int _si5351_clkout_set_disable_state(
867         struct si5351_driver_data *drvdata, int num,
868         enum si5351_disable_state state)
869 {
870         u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
871                 SI5351_CLK7_4_DISABLE_STATE;
872         u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
873         u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
874         u8 val;
875
876         if (num > 8)
877                 return -EINVAL;
878
879         switch (state) {
880         case SI5351_DISABLE_LOW:
881                 val = SI5351_CLK_DISABLE_STATE_LOW;
882                 break;
883         case SI5351_DISABLE_HIGH:
884                 val = SI5351_CLK_DISABLE_STATE_HIGH;
885                 break;
886         case SI5351_DISABLE_FLOATING:
887                 val = SI5351_CLK_DISABLE_STATE_FLOAT;
888                 break;
889         case SI5351_DISABLE_NEVER:
890                 val = SI5351_CLK_DISABLE_STATE_NEVER;
891                 break;
892         default:
893                 return 0;
894         }
895
896         si5351_set_bits(drvdata, reg, mask, val << shift);
897
898         return 0;
899 }
900
901 static int si5351_clkout_prepare(struct clk_hw *hw)
902 {
903         struct si5351_hw_data *hwdata =
904                 container_of(hw, struct si5351_hw_data, hw);
905
906         si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
907                         SI5351_CLK_POWERDOWN, 0);
908         si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
909                         (1 << hwdata->num), 0);
910         return 0;
911 }
912
913 static void si5351_clkout_unprepare(struct clk_hw *hw)
914 {
915         struct si5351_hw_data *hwdata =
916                 container_of(hw, struct si5351_hw_data, hw);
917
918         si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
919                         SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
920         si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
921                         (1 << hwdata->num), (1 << hwdata->num));
922 }
923
924 static u8 si5351_clkout_get_parent(struct clk_hw *hw)
925 {
926         struct si5351_hw_data *hwdata =
927                 container_of(hw, struct si5351_hw_data, hw);
928         int index = 0;
929         unsigned char val;
930
931         val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
932         switch (val & SI5351_CLK_INPUT_MASK) {
933         case SI5351_CLK_INPUT_MULTISYNTH_N:
934                 index = 0;
935                 break;
936         case SI5351_CLK_INPUT_MULTISYNTH_0_4:
937                 index = 1;
938                 break;
939         case SI5351_CLK_INPUT_XTAL:
940                 index = 2;
941                 break;
942         case SI5351_CLK_INPUT_CLKIN:
943                 index = 3;
944                 break;
945         }
946
947         return index;
948 }
949
950 static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
951 {
952         struct si5351_hw_data *hwdata =
953                 container_of(hw, struct si5351_hw_data, hw);
954         enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
955
956         switch (index) {
957         case 0:
958                 parent = SI5351_CLKOUT_SRC_MSYNTH_N;
959                 break;
960         case 1:
961                 parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
962                 break;
963         case 2:
964                 parent = SI5351_CLKOUT_SRC_XTAL;
965                 break;
966         case 3:
967                 parent = SI5351_CLKOUT_SRC_CLKIN;
968                 break;
969         }
970
971         return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
972 }
973
974 static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
975                                                unsigned long parent_rate)
976 {
977         struct si5351_hw_data *hwdata =
978                 container_of(hw, struct si5351_hw_data, hw);
979         unsigned char reg;
980         unsigned char rdiv;
981
982         if (hwdata->num <= 5)
983                 reg = si5351_msynth_params_address(hwdata->num) + 2;
984         else
985                 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
986
987         rdiv = si5351_reg_read(hwdata->drvdata, reg);
988         if (hwdata->num == 6) {
989                 rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
990         } else {
991                 rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
992                 rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
993         }
994
995         return parent_rate >> rdiv;
996 }
997
998 static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
999                                      unsigned long *parent_rate)
1000 {
1001         struct si5351_hw_data *hwdata =
1002                 container_of(hw, struct si5351_hw_data, hw);
1003         unsigned char rdiv;
1004
1005         /* clkout6/7 can only handle output freqencies < 150MHz */
1006         if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
1007                 rate = SI5351_CLKOUT67_MAX_FREQ;
1008
1009         /* clkout freqency is 8kHz - 160MHz */
1010         if (rate > SI5351_CLKOUT_MAX_FREQ)
1011                 rate = SI5351_CLKOUT_MAX_FREQ;
1012         if (rate < SI5351_CLKOUT_MIN_FREQ)
1013                 rate = SI5351_CLKOUT_MIN_FREQ;
1014
1015         /* request frequency if multisync master */
1016         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
1017                 /* use r divider for frequencies below 1MHz */
1018                 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1019                 while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
1020                        rdiv < SI5351_OUTPUT_CLK_DIV_128) {
1021                         rdiv += 1;
1022                         rate *= 2;
1023                 }
1024                 *parent_rate = rate;
1025         } else {
1026                 unsigned long new_rate, new_err, err;
1027
1028                 /* round to closed rdiv */
1029                 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1030                 new_rate = *parent_rate;
1031                 err = abs(new_rate - rate);
1032                 do {
1033                         new_rate >>= 1;
1034                         new_err = abs(new_rate - rate);
1035                         if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1036                                 break;
1037                         rdiv++;
1038                         err = new_err;
1039                 } while (1);
1040         }
1041         rate = *parent_rate >> rdiv;
1042
1043         dev_dbg(&hwdata->drvdata->client->dev,
1044                 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1045                 __func__, clk_hw_get_name(hw), (1 << rdiv),
1046                 *parent_rate, rate);
1047
1048         return rate;
1049 }
1050
1051 static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1052                                   unsigned long parent_rate)
1053 {
1054         struct si5351_hw_data *hwdata =
1055                 container_of(hw, struct si5351_hw_data, hw);
1056         unsigned long new_rate, new_err, err;
1057         unsigned char rdiv;
1058
1059         /* round to closed rdiv */
1060         rdiv = SI5351_OUTPUT_CLK_DIV_1;
1061         new_rate = parent_rate;
1062         err = abs(new_rate - rate);
1063         do {
1064                 new_rate >>= 1;
1065                 new_err = abs(new_rate - rate);
1066                 if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1067                         break;
1068                 rdiv++;
1069                 err = new_err;
1070         } while (1);
1071
1072         /* write output divider */
1073         switch (hwdata->num) {
1074         case 6:
1075                 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1076                                 SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
1077                 break;
1078         case 7:
1079                 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1080                                 SI5351_OUTPUT_CLK_DIV_MASK,
1081                                 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1082                 break;
1083         default:
1084                 si5351_set_bits(hwdata->drvdata,
1085                                 si5351_msynth_params_address(hwdata->num) + 2,
1086                                 SI5351_OUTPUT_CLK_DIV_MASK,
1087                                 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1088         }
1089
1090         /* powerup clkout */
1091         si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
1092                         SI5351_CLK_POWERDOWN, 0);
1093
1094         dev_dbg(&hwdata->drvdata->client->dev,
1095                 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1096                 __func__, clk_hw_get_name(hw), (1 << rdiv),
1097                 parent_rate, rate);
1098
1099         return 0;
1100 }
1101
1102 static const struct clk_ops si5351_clkout_ops = {
1103         .prepare = si5351_clkout_prepare,
1104         .unprepare = si5351_clkout_unprepare,
1105         .set_parent = si5351_clkout_set_parent,
1106         .get_parent = si5351_clkout_get_parent,
1107         .recalc_rate = si5351_clkout_recalc_rate,
1108         .round_rate = si5351_clkout_round_rate,
1109         .set_rate = si5351_clkout_set_rate,
1110 };
1111
1112 /*
1113  * Si5351 i2c probe and DT
1114  */
1115 #ifdef CONFIG_OF
1116 static const struct of_device_id si5351_dt_ids[] = {
1117         { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
1118         { .compatible = "silabs,si5351a-msop",
1119                                          .data = (void *)SI5351_VARIANT_A3, },
1120         { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
1121         { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
1122         { }
1123 };
1124 MODULE_DEVICE_TABLE(of, si5351_dt_ids);
1125
1126 static int si5351_dt_parse(struct i2c_client *client,
1127                            enum si5351_variant variant)
1128 {
1129         struct device_node *child, *np = client->dev.of_node;
1130         struct si5351_platform_data *pdata;
1131         struct property *prop;
1132         const __be32 *p;
1133         int num = 0;
1134         u32 val;
1135
1136         if (np == NULL)
1137                 return 0;
1138
1139         pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1140         if (!pdata)
1141                 return -ENOMEM;
1142
1143         /*
1144          * property silabs,pll-source : <num src>, [<..>]
1145          * allow to selectively set pll source
1146          */
1147         of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
1148                 if (num >= 2) {
1149                         dev_err(&client->dev,
1150                                 "invalid pll %d on pll-source prop\n", num);
1151                         return -EINVAL;
1152                 }
1153
1154                 p = of_prop_next_u32(prop, p, &val);
1155                 if (!p) {
1156                         dev_err(&client->dev,
1157                                 "missing pll-source for pll %d\n", num);
1158                         return -EINVAL;
1159                 }
1160
1161                 switch (val) {
1162                 case 0:
1163                         pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
1164                         break;
1165                 case 1:
1166                         if (variant != SI5351_VARIANT_C) {
1167                                 dev_err(&client->dev,
1168                                         "invalid parent %d for pll %d\n",
1169                                         val, num);
1170                                 return -EINVAL;
1171                         }
1172                         pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
1173                         break;
1174                 default:
1175                         dev_err(&client->dev,
1176                                  "invalid parent %d for pll %d\n", val, num);
1177                         return -EINVAL;
1178                 }
1179         }
1180
1181         /* per clkout properties */
1182         for_each_child_of_node(np, child) {
1183                 if (of_property_read_u32(child, "reg", &num)) {
1184                         dev_err(&client->dev, "missing reg property of %s\n",
1185                                 child->name);
1186                         goto put_child;
1187                 }
1188
1189                 if (num >= 8 ||
1190                     (variant == SI5351_VARIANT_A3 && num >= 3)) {
1191                         dev_err(&client->dev, "invalid clkout %d\n", num);
1192                         goto put_child;
1193                 }
1194
1195                 if (!of_property_read_u32(child, "silabs,multisynth-source",
1196                                           &val)) {
1197                         switch (val) {
1198                         case 0:
1199                                 pdata->clkout[num].multisynth_src =
1200                                         SI5351_MULTISYNTH_SRC_VCO0;
1201                                 break;
1202                         case 1:
1203                                 pdata->clkout[num].multisynth_src =
1204                                         SI5351_MULTISYNTH_SRC_VCO1;
1205                                 break;
1206                         default:
1207                                 dev_err(&client->dev,
1208                                         "invalid parent %d for multisynth %d\n",
1209                                         val, num);
1210                                 goto put_child;
1211                         }
1212                 }
1213
1214                 if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
1215                         switch (val) {
1216                         case 0:
1217                                 pdata->clkout[num].clkout_src =
1218                                         SI5351_CLKOUT_SRC_MSYNTH_N;
1219                                 break;
1220                         case 1:
1221                                 pdata->clkout[num].clkout_src =
1222                                         SI5351_CLKOUT_SRC_MSYNTH_0_4;
1223                                 break;
1224                         case 2:
1225                                 pdata->clkout[num].clkout_src =
1226                                         SI5351_CLKOUT_SRC_XTAL;
1227                                 break;
1228                         case 3:
1229                                 if (variant != SI5351_VARIANT_C) {
1230                                         dev_err(&client->dev,
1231                                                 "invalid parent %d for clkout %d\n",
1232                                                 val, num);
1233                                         goto put_child;
1234                                 }
1235                                 pdata->clkout[num].clkout_src =
1236                                         SI5351_CLKOUT_SRC_CLKIN;
1237                                 break;
1238                         default:
1239                                 dev_err(&client->dev,
1240                                         "invalid parent %d for clkout %d\n",
1241                                         val, num);
1242                                 goto put_child;
1243                         }
1244                 }
1245
1246                 if (!of_property_read_u32(child, "silabs,drive-strength",
1247                                           &val)) {
1248                         switch (val) {
1249                         case SI5351_DRIVE_2MA:
1250                         case SI5351_DRIVE_4MA:
1251                         case SI5351_DRIVE_6MA:
1252                         case SI5351_DRIVE_8MA:
1253                                 pdata->clkout[num].drive = val;
1254                                 break;
1255                         default:
1256                                 dev_err(&client->dev,
1257                                         "invalid drive strength %d for clkout %d\n",
1258                                         val, num);
1259                                 goto put_child;
1260                         }
1261                 }
1262
1263                 if (!of_property_read_u32(child, "silabs,disable-state",
1264                                           &val)) {
1265                         switch (val) {
1266                         case 0:
1267                                 pdata->clkout[num].disable_state =
1268                                         SI5351_DISABLE_LOW;
1269                                 break;
1270                         case 1:
1271                                 pdata->clkout[num].disable_state =
1272                                         SI5351_DISABLE_HIGH;
1273                                 break;
1274                         case 2:
1275                                 pdata->clkout[num].disable_state =
1276                                         SI5351_DISABLE_FLOATING;
1277                                 break;
1278                         case 3:
1279                                 pdata->clkout[num].disable_state =
1280                                         SI5351_DISABLE_NEVER;
1281                                 break;
1282                         default:
1283                                 dev_err(&client->dev,
1284                                         "invalid disable state %d for clkout %d\n",
1285                                         val, num);
1286                                 goto put_child;
1287                         }
1288                 }
1289
1290                 if (!of_property_read_u32(child, "clock-frequency", &val))
1291                         pdata->clkout[num].rate = val;
1292
1293                 pdata->clkout[num].pll_master =
1294                         of_property_read_bool(child, "silabs,pll-master");
1295         }
1296         client->dev.platform_data = pdata;
1297
1298         return 0;
1299 put_child:
1300         of_node_put(child);
1301         return -EINVAL;
1302 }
1303 #else
1304 static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
1305 {
1306         return 0;
1307 }
1308 #endif /* CONFIG_OF */
1309
1310 static int si5351_i2c_probe(struct i2c_client *client,
1311                             const struct i2c_device_id *id)
1312 {
1313         enum si5351_variant variant = (enum si5351_variant)id->driver_data;
1314         struct si5351_platform_data *pdata;
1315         struct si5351_driver_data *drvdata;
1316         struct clk_init_data init;
1317         struct clk *clk;
1318         const char *parent_names[4];
1319         u8 num_parents, num_clocks;
1320         int ret, n;
1321
1322         ret = si5351_dt_parse(client, variant);
1323         if (ret)
1324                 return ret;
1325
1326         pdata = client->dev.platform_data;
1327         if (!pdata)
1328                 return -EINVAL;
1329
1330         drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
1331         if (drvdata == NULL) {
1332                 dev_err(&client->dev, "unable to allocate driver data\n");
1333                 return -ENOMEM;
1334         }
1335
1336         i2c_set_clientdata(client, drvdata);
1337         drvdata->client = client;
1338         drvdata->variant = variant;
1339         drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
1340         drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
1341
1342         if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
1343             PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
1344                 return -EPROBE_DEFER;
1345
1346         /*
1347          * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
1348          *   VARIANT_C can have CLKIN instead.
1349          */
1350         if (IS_ERR(drvdata->pxtal) &&
1351             (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
1352                 dev_err(&client->dev, "missing parent clock\n");
1353                 return -EINVAL;
1354         }
1355
1356         drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
1357         if (IS_ERR(drvdata->regmap)) {
1358                 dev_err(&client->dev, "failed to allocate register map\n");
1359                 return PTR_ERR(drvdata->regmap);
1360         }
1361
1362         /* Disable interrupts */
1363         si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
1364         /* Ensure pll select is on XTAL for Si5351A/B */
1365         if (drvdata->variant != SI5351_VARIANT_C)
1366                 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
1367                                 SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
1368
1369         /* setup clock configuration */
1370         for (n = 0; n < 2; n++) {
1371                 ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
1372                 if (ret) {
1373                         dev_err(&client->dev,
1374                                 "failed to reparent pll %d to %d\n",
1375                                 n, pdata->pll_src[n]);
1376                         return ret;
1377                 }
1378         }
1379
1380         for (n = 0; n < 8; n++) {
1381                 ret = _si5351_msynth_reparent(drvdata, n,
1382                                               pdata->clkout[n].multisynth_src);
1383                 if (ret) {
1384                         dev_err(&client->dev,
1385                                 "failed to reparent multisynth %d to %d\n",
1386                                 n, pdata->clkout[n].multisynth_src);
1387                         return ret;
1388                 }
1389
1390                 ret = _si5351_clkout_reparent(drvdata, n,
1391                                               pdata->clkout[n].clkout_src);
1392                 if (ret) {
1393                         dev_err(&client->dev,
1394                                 "failed to reparent clkout %d to %d\n",
1395                                 n, pdata->clkout[n].clkout_src);
1396                         return ret;
1397                 }
1398
1399                 ret = _si5351_clkout_set_drive_strength(drvdata, n,
1400                                                         pdata->clkout[n].drive);
1401                 if (ret) {
1402                         dev_err(&client->dev,
1403                                 "failed set drive strength of clkout%d to %d\n",
1404                                 n, pdata->clkout[n].drive);
1405                         return ret;
1406                 }
1407
1408                 ret = _si5351_clkout_set_disable_state(drvdata, n,
1409                                                 pdata->clkout[n].disable_state);
1410                 if (ret) {
1411                         dev_err(&client->dev,
1412                                 "failed set disable state of clkout%d to %d\n",
1413                                 n, pdata->clkout[n].disable_state);
1414                         return ret;
1415                 }
1416         }
1417
1418         if (!IS_ERR(drvdata->pxtal))
1419                 clk_prepare_enable(drvdata->pxtal);
1420         if (!IS_ERR(drvdata->pclkin))
1421                 clk_prepare_enable(drvdata->pclkin);
1422
1423         /* register xtal input clock gate */
1424         memset(&init, 0, sizeof(init));
1425         init.name = si5351_input_names[0];
1426         init.ops = &si5351_xtal_ops;
1427         init.flags = 0;
1428         if (!IS_ERR(drvdata->pxtal)) {
1429                 drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
1430                 init.parent_names = &drvdata->pxtal_name;
1431                 init.num_parents = 1;
1432         }
1433         drvdata->xtal.init = &init;
1434         clk = devm_clk_register(&client->dev, &drvdata->xtal);
1435         if (IS_ERR(clk)) {
1436                 dev_err(&client->dev, "unable to register %s\n", init.name);
1437                 ret = PTR_ERR(clk);
1438                 goto err_clk;
1439         }
1440
1441         /* register clkin input clock gate */
1442         if (drvdata->variant == SI5351_VARIANT_C) {
1443                 memset(&init, 0, sizeof(init));
1444                 init.name = si5351_input_names[1];
1445                 init.ops = &si5351_clkin_ops;
1446                 if (!IS_ERR(drvdata->pclkin)) {
1447                         drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
1448                         init.parent_names = &drvdata->pclkin_name;
1449                         init.num_parents = 1;
1450                 }
1451                 drvdata->clkin.init = &init;
1452                 clk = devm_clk_register(&client->dev, &drvdata->clkin);
1453                 if (IS_ERR(clk)) {
1454                         dev_err(&client->dev, "unable to register %s\n",
1455                                 init.name);
1456                         ret = PTR_ERR(clk);
1457                         goto err_clk;
1458                 }
1459         }
1460
1461         /* Si5351C allows to mux either xtal or clkin to PLL input */
1462         num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
1463         parent_names[0] = si5351_input_names[0];
1464         parent_names[1] = si5351_input_names[1];
1465
1466         /* register PLLA */
1467         drvdata->pll[0].num = 0;
1468         drvdata->pll[0].drvdata = drvdata;
1469         drvdata->pll[0].hw.init = &init;
1470         memset(&init, 0, sizeof(init));
1471         init.name = si5351_pll_names[0];
1472         init.ops = &si5351_pll_ops;
1473         init.flags = 0;
1474         init.parent_names = parent_names;
1475         init.num_parents = num_parents;
1476         clk = devm_clk_register(&client->dev, &drvdata->pll[0].hw);
1477         if (IS_ERR(clk)) {
1478                 dev_err(&client->dev, "unable to register %s\n", init.name);
1479                 ret = PTR_ERR(clk);
1480                 goto err_clk;
1481         }
1482
1483         /* register PLLB or VXCO (Si5351B) */
1484         drvdata->pll[1].num = 1;
1485         drvdata->pll[1].drvdata = drvdata;
1486         drvdata->pll[1].hw.init = &init;
1487         memset(&init, 0, sizeof(init));
1488         if (drvdata->variant == SI5351_VARIANT_B) {
1489                 init.name = si5351_pll_names[2];
1490                 init.ops = &si5351_vxco_ops;
1491                 init.flags = CLK_IS_ROOT;
1492                 init.parent_names = NULL;
1493                 init.num_parents = 0;
1494         } else {
1495                 init.name = si5351_pll_names[1];
1496                 init.ops = &si5351_pll_ops;
1497                 init.flags = 0;
1498                 init.parent_names = parent_names;
1499                 init.num_parents = num_parents;
1500         }
1501         clk = devm_clk_register(&client->dev, &drvdata->pll[1].hw);
1502         if (IS_ERR(clk)) {
1503                 dev_err(&client->dev, "unable to register %s\n", init.name);
1504                 ret = PTR_ERR(clk);
1505                 goto err_clk;
1506         }
1507
1508         /* register clk multisync and clk out divider */
1509         num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
1510         parent_names[0] = si5351_pll_names[0];
1511         if (drvdata->variant == SI5351_VARIANT_B)
1512                 parent_names[1] = si5351_pll_names[2];
1513         else
1514                 parent_names[1] = si5351_pll_names[1];
1515
1516         drvdata->msynth = devm_kzalloc(&client->dev, num_clocks *
1517                                        sizeof(*drvdata->msynth), GFP_KERNEL);
1518         drvdata->clkout = devm_kzalloc(&client->dev, num_clocks *
1519                                        sizeof(*drvdata->clkout), GFP_KERNEL);
1520
1521         drvdata->onecell.clk_num = num_clocks;
1522         drvdata->onecell.clks = devm_kzalloc(&client->dev,
1523                 num_clocks * sizeof(*drvdata->onecell.clks), GFP_KERNEL);
1524
1525         if (WARN_ON(!drvdata->msynth || !drvdata->clkout ||
1526                     !drvdata->onecell.clks)) {
1527                 ret = -ENOMEM;
1528                 goto err_clk;
1529         }
1530
1531         for (n = 0; n < num_clocks; n++) {
1532                 drvdata->msynth[n].num = n;
1533                 drvdata->msynth[n].drvdata = drvdata;
1534                 drvdata->msynth[n].hw.init = &init;
1535                 memset(&init, 0, sizeof(init));
1536                 init.name = si5351_msynth_names[n];
1537                 init.ops = &si5351_msynth_ops;
1538                 init.flags = 0;
1539                 if (pdata->clkout[n].pll_master)
1540                         init.flags |= CLK_SET_RATE_PARENT;
1541                 init.parent_names = parent_names;
1542                 init.num_parents = 2;
1543                 clk = devm_clk_register(&client->dev, &drvdata->msynth[n].hw);
1544                 if (IS_ERR(clk)) {
1545                         dev_err(&client->dev, "unable to register %s\n",
1546                                 init.name);
1547                         ret = PTR_ERR(clk);
1548                         goto err_clk;
1549                 }
1550         }
1551
1552         num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
1553         parent_names[2] = si5351_input_names[0];
1554         parent_names[3] = si5351_input_names[1];
1555         for (n = 0; n < num_clocks; n++) {
1556                 parent_names[0] = si5351_msynth_names[n];
1557                 parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
1558                         si5351_msynth_names[4];
1559
1560                 drvdata->clkout[n].num = n;
1561                 drvdata->clkout[n].drvdata = drvdata;
1562                 drvdata->clkout[n].hw.init = &init;
1563                 memset(&init, 0, sizeof(init));
1564                 init.name = si5351_clkout_names[n];
1565                 init.ops = &si5351_clkout_ops;
1566                 init.flags = 0;
1567                 if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
1568                         init.flags |= CLK_SET_RATE_PARENT;
1569                 init.parent_names = parent_names;
1570                 init.num_parents = num_parents;
1571                 clk = devm_clk_register(&client->dev, &drvdata->clkout[n].hw);
1572                 if (IS_ERR(clk)) {
1573                         dev_err(&client->dev, "unable to register %s\n",
1574                                 init.name);
1575                         ret = PTR_ERR(clk);
1576                         goto err_clk;
1577                 }
1578                 drvdata->onecell.clks[n] = clk;
1579
1580                 /* set initial clkout rate */
1581                 if (pdata->clkout[n].rate != 0) {
1582                         int ret;
1583                         ret = clk_set_rate(clk, pdata->clkout[n].rate);
1584                         if (ret != 0) {
1585                                 dev_err(&client->dev, "Cannot set rate : %d\n",
1586                                         ret);
1587                         }
1588                 }
1589         }
1590
1591         ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
1592                                   &drvdata->onecell);
1593         if (ret) {
1594                 dev_err(&client->dev, "unable to add clk provider\n");
1595                 goto err_clk;
1596         }
1597
1598         return 0;
1599
1600 err_clk:
1601         if (!IS_ERR(drvdata->pxtal))
1602                 clk_disable_unprepare(drvdata->pxtal);
1603         if (!IS_ERR(drvdata->pclkin))
1604                 clk_disable_unprepare(drvdata->pclkin);
1605         return ret;
1606 }
1607
1608 static const struct i2c_device_id si5351_i2c_ids[] = {
1609         { "si5351a", SI5351_VARIANT_A },
1610         { "si5351a-msop", SI5351_VARIANT_A3 },
1611         { "si5351b", SI5351_VARIANT_B },
1612         { "si5351c", SI5351_VARIANT_C },
1613         { }
1614 };
1615 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
1616
1617 static struct i2c_driver si5351_driver = {
1618         .driver = {
1619                 .name = "si5351",
1620                 .of_match_table = of_match_ptr(si5351_dt_ids),
1621         },
1622         .probe = si5351_i2c_probe,
1623         .id_table = si5351_i2c_ids,
1624 };
1625 module_i2c_driver(si5351_driver);
1626
1627 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
1628 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
1629 MODULE_LICENSE("GPL");