1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Silicon Labs Si5341/Si5340 Clock generator
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/gcd.h>
12 #include <linux/math64.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <asm/unaligned.h>
19 #define SI5341_MAX_NUM_OUTPUTS 10
20 #define SI5340_MAX_NUM_OUTPUTS 4
22 #define SI5341_NUM_SYNTH 5
23 #define SI5340_NUM_SYNTH 4
25 /* Range of the synthesizer fractional divider */
26 #define SI5341_SYNTH_N_MIN 10
27 #define SI5341_SYNTH_N_MAX 4095
29 /* The chip can get its input clock from 3 input pins or an XTAL */
31 /* There is one PLL running at 13500–14256 MHz */
32 #define SI5341_PLL_VCO_MIN 13500000000ull
33 #define SI5341_PLL_VCO_MAX 14256000000ull
35 /* The 5 frequency synthesizers obtain their input from the PLL */
36 struct clk_si5341_synth {
38 struct clk_si5341 *data;
41 #define to_clk_si5341_synth(_hw) \
42 container_of(_hw, struct clk_si5341_synth, hw)
44 /* The output stages can be connected to any synth (full mux) */
45 struct clk_si5341_output {
47 struct clk_si5341 *data;
50 #define to_clk_si5341_output(_hw) \
51 container_of(_hw, struct clk_si5341_output, hw)
55 struct regmap *regmap;
56 struct i2c_client *i2c_client;
57 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
58 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
60 const char *pxtal_name;
61 const u16 *reg_output_offset;
62 const u16 *reg_rdiv_offset;
63 u64 freq_vco; /* 13500–14256 MHz */
67 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
69 struct clk_si5341_output_config {
70 u8 out_format_drv_bits;
76 #define SI5341_PAGE 0x0001
77 #define SI5341_PN_BASE 0x0002
78 #define SI5341_DEVICE_REV 0x0005
79 #define SI5341_STATUS 0x000C
80 #define SI5341_SOFT_RST 0x001C
82 /* Input dividers (48-bit) */
83 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
84 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
86 /* PLL configuration */
87 #define SI5341_PLL_M_NUM 0x0235
88 #define SI5341_PLL_M_DEN 0x023B
90 /* Output configuration */
91 #define SI5341_OUT_CONFIG(output) \
92 ((output)->data->reg_output_offset[(output)->index])
93 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
94 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
95 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
96 #define SI5341_OUT_R_REG(output) \
97 ((output)->data->reg_rdiv_offset[(output)->index])
99 /* Synthesize N divider */
100 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
101 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
102 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
104 /* Synthesizer output enable, phase bypass, power mode */
105 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
106 #define SI5341_SYNTH_N_PIBYP 0x0A04
107 #define SI5341_SYNTH_N_PDNB 0x0A05
108 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
110 #define SI5341_REGISTER_MAX 0xBFF
112 /* SI5341_OUT_CONFIG bits */
113 #define SI5341_OUT_CFG_PDN BIT(0)
114 #define SI5341_OUT_CFG_OE BIT(1)
115 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
117 /* Static configuration (to be moved to firmware) */
118 struct si5341_reg_default {
123 /* Output configuration registers 0..9 are not quite logically organized */
124 static const u16 si5341_reg_output_offset[] = {
137 static const u16 si5340_reg_output_offset[] = {
144 /* The location of the R divider registers */
145 static const u16 si5341_reg_rdiv_offset[] = {
157 static const u16 si5340_reg_rdiv_offset[] = {
165 * Programming sequence from ClockBuilder, settings to initialize the system
166 * using only the XTAL input, without pre-divider.
167 * This also contains settings that aren't mentioned anywhere in the datasheet.
168 * The "known" settings like synth and output configuration are done later.
170 static const struct si5341_reg_default si5341_reg_defaults[] = {
171 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
172 { 0x0018, 0xFF }, /* INT mask */
173 { 0x0021, 0x0F }, /* Select XTAL as input */
174 { 0x0022, 0x00 }, /* Not in datasheet */
175 { 0x002B, 0x02 }, /* SPI config */
176 { 0x002C, 0x20 }, /* LOS enable for XTAL */
177 { 0x002D, 0x00 }, /* LOS timing */
188 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
193 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
194 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
195 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
196 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
197 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
198 { 0x009E, 0x00 }, /* Not in datasheet */
199 { 0x0102, 0x01 }, /* Enable outputs */
200 { 0x013F, 0x00 }, /* Not in datasheet */
201 { 0x0140, 0x00 }, /* Not in datasheet */
202 { 0x0141, 0x40 }, /* OUT LOS */
203 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
207 { 0x0206, 0x00 }, /* PXAXB (2^x) */
208 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
247 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
248 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
255 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
256 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
257 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
286 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
287 { 0x0359, 0x00 }, /* Nx_DELAY */
296 { 0x0362, 0x00 }, /* Nx_DELAY end */
297 { 0x0802, 0x00 }, /* Not in datasheet */
298 { 0x0803, 0x00 }, /* Not in datasheet */
299 { 0x0804, 0x00 }, /* Not in datasheet */
300 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
301 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
302 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
303 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
304 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
305 { 0x0A02, 0x00 }, /* Not in datasheet */
306 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
307 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
308 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
311 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
312 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
313 u64 *val1, u32 *val2)
318 err = regmap_bulk_read(regmap, reg, r, 10);
322 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
323 (get_unaligned_le32(r));
324 *val2 = get_unaligned_le32(&r[6]);
329 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
330 u64 n_num, u32 n_den)
334 /* Shift left as far as possible without overflowing */
335 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
340 /* 44 bits (6 bytes) numerator */
341 put_unaligned_le32(n_num, r);
342 r[4] = (n_num >> 32) & 0xff;
343 r[5] = (n_num >> 40) & 0x0f;
344 /* 32 bits denominator */
345 put_unaligned_le32(n_den, &r[6]);
347 /* Program the fraction */
348 return regmap_bulk_write(regmap, reg, r, sizeof(r));
351 /* VCO, we assume it runs at a constant frequency */
352 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
353 unsigned long parent_rate)
355 struct clk_si5341 *data = to_clk_si5341(hw);
362 /* Assume that PDIV is not being used, just read the PLL setting */
363 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
368 if (!m_num || !m_den)
372 * Though m_num is 64-bit, only the upper bits are actually used. While
373 * calculating m_num and m_den, they are shifted as far as possible to
374 * the left. To avoid 96-bit division here, we just shift them back so
375 * we can do with just 64 bits.
379 while (res & 0xffff00000000ULL) {
384 do_div(res, (m_den >> shift));
386 /* We cannot return the actual frequency in 32 bit, store it locally */
387 data->freq_vco = res;
389 /* Report kHz since the value is out of range */
392 return (unsigned long)res;
395 static const struct clk_ops si5341_clk_ops = {
396 .recalc_rate = si5341_clk_recalc_rate,
399 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
401 /* The synthesizer is on if all power and enable bits are set */
402 static int si5341_synth_clk_is_on(struct clk_hw *hw)
404 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
407 u8 index = synth->index;
409 err = regmap_read(synth->data->regmap,
410 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
414 if (!(val & BIT(index)))
417 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
421 if (!(val & BIT(index)))
424 /* This bit must be 0 for the synthesizer to receive clock input */
425 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
429 return !(val & BIT(index));
432 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
434 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
435 u8 index = synth->index; /* In range 0..5 */
436 u8 mask = BIT(index);
439 regmap_update_bits(synth->data->regmap,
440 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
442 regmap_update_bits(synth->data->regmap,
443 SI5341_SYNTH_N_PDNB, mask, 0);
444 /* Disable clock input to synth (set to 1 to disable) */
445 regmap_update_bits(synth->data->regmap,
446 SI5341_SYNTH_N_CLK_DIS, mask, mask);
449 static int si5341_synth_clk_prepare(struct clk_hw *hw)
451 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
453 u8 index = synth->index;
454 u8 mask = BIT(index);
457 err = regmap_update_bits(synth->data->regmap,
458 SI5341_SYNTH_N_PDNB, mask, mask);
462 /* Enable clock input to synth (set bit to 0 to enable) */
463 err = regmap_update_bits(synth->data->regmap,
464 SI5341_SYNTH_N_CLK_DIS, mask, 0);
469 return regmap_update_bits(synth->data->regmap,
470 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
473 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
474 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
475 unsigned long parent_rate)
477 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
483 err = si5341_decode_44_32(synth->data->regmap,
484 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
487 /* Check for bogus/uninitialized settings */
488 if (!n_num || !n_den)
492 * n_num and n_den are shifted left as much as possible, so to prevent
493 * overflow in 64-bit math, we shift n_den 4 bits to the right
495 f = synth->data->freq_vco;
498 /* Now we need to to 64-bit division: f/n_num */
499 /* And compensate for the 4 bits we dropped */
500 f = div64_u64(f, (n_num >> 4));
505 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
506 unsigned long *parent_rate)
508 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
511 /* The synthesizer accuracy is such that anything in range will work */
512 f = synth->data->freq_vco;
513 do_div(f, SI5341_SYNTH_N_MAX);
517 f = synth->data->freq_vco;
518 do_div(f, SI5341_SYNTH_N_MIN);
525 static int si5341_synth_program(struct clk_si5341_synth *synth,
526 u64 n_num, u32 n_den, bool is_integer)
529 u8 index = synth->index;
531 err = si5341_encode_44_32(synth->data->regmap,
532 SI5341_SYNTH_N_NUM(index), n_num, n_den);
534 err = regmap_update_bits(synth->data->regmap,
535 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
539 return regmap_write(synth->data->regmap,
540 SI5341_SYNTH_N_UPD(index), 0x01);
544 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
545 unsigned long parent_rate)
547 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
554 n_num = synth->data->freq_vco;
556 /* see if there's an integer solution */
557 r = do_div(n_num, rate);
558 is_integer = (r == 0);
560 /* Integer divider equal to n_num */
563 /* Calculate a fractional solution */
570 dev_dbg(&synth->data->i2c_client->dev,
571 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
572 synth->index, n_num, n_den,
573 is_integer ? "int" : "frac");
575 return si5341_synth_program(synth, n_num, n_den, is_integer);
578 static const struct clk_ops si5341_synth_clk_ops = {
579 .is_prepared = si5341_synth_clk_is_on,
580 .prepare = si5341_synth_clk_prepare,
581 .unprepare = si5341_synth_clk_unprepare,
582 .recalc_rate = si5341_synth_clk_recalc_rate,
583 .round_rate = si5341_synth_clk_round_rate,
584 .set_rate = si5341_synth_clk_set_rate,
587 static int si5341_output_clk_is_on(struct clk_hw *hw)
589 struct clk_si5341_output *output = to_clk_si5341_output(hw);
593 err = regmap_read(output->data->regmap,
594 SI5341_OUT_CONFIG(output), &val);
598 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
599 return (val & 0x03) == SI5341_OUT_CFG_OE;
602 /* Disables and then powers down the output */
603 static void si5341_output_clk_unprepare(struct clk_hw *hw)
605 struct clk_si5341_output *output = to_clk_si5341_output(hw);
607 regmap_update_bits(output->data->regmap,
608 SI5341_OUT_CONFIG(output),
609 SI5341_OUT_CFG_OE, 0);
610 regmap_update_bits(output->data->regmap,
611 SI5341_OUT_CONFIG(output),
612 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
615 /* Powers up and then enables the output */
616 static int si5341_output_clk_prepare(struct clk_hw *hw)
618 struct clk_si5341_output *output = to_clk_si5341_output(hw);
621 err = regmap_update_bits(output->data->regmap,
622 SI5341_OUT_CONFIG(output),
623 SI5341_OUT_CFG_PDN, 0);
627 return regmap_update_bits(output->data->regmap,
628 SI5341_OUT_CONFIG(output),
629 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
632 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
633 unsigned long parent_rate)
635 struct clk_si5341_output *output = to_clk_si5341_output(hw);
641 err = regmap_read(output->data->regmap,
642 SI5341_OUT_CONFIG(output), &val);
646 /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
647 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
648 return parent_rate / 2;
650 err = regmap_bulk_read(output->data->regmap,
651 SI5341_OUT_R_REG(output), r, 3);
655 /* Calculate value as 24-bit integer*/
656 r_divider = r[2] << 16 | r[1] << 8 | r[0];
658 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
662 /* Divider is 2*(Rx_REG+1) */
667 return parent_rate / r_divider;
670 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
671 unsigned long *parent_rate)
678 r = *parent_rate >> 1;
680 /* If rate is an even divisor, no changes to parent required */
681 if (r && !(r % rate))
684 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
685 if (rate > 200000000) {
686 /* minimum r-divider is 2 */
689 /* Take a parent frequency near 400 MHz */
690 r = (400000000u / rate) & ~1;
692 *parent_rate = r * rate;
694 /* We cannot change our parent's rate, report what we can do */
696 rate = *parent_rate / (r << 1);
702 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
703 unsigned long parent_rate)
705 struct clk_si5341_output *output = to_clk_si5341_output(hw);
713 /* Frequency divider is (r_div + 1) * 2 */
714 r_div = (parent_rate / rate) >> 1;
718 else if (r_div >= BIT(24))
723 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
724 err = regmap_update_bits(output->data->regmap,
725 SI5341_OUT_CONFIG(output),
726 SI5341_OUT_CFG_RDIV_FORCE2,
727 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
731 /* Always write Rx_REG, because a zero value disables the divider */
732 r[0] = r_div ? (r_div & 0xff) : 1;
733 r[1] = (r_div >> 8) & 0xff;
734 r[2] = (r_div >> 16) & 0xff;
735 err = regmap_bulk_write(output->data->regmap,
736 SI5341_OUT_R_REG(output), r, 3);
741 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
743 return regmap_update_bits(output->data->regmap,
744 SI5341_OUT_MUX_SEL(output), 0x07, index);
747 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
749 struct clk_si5341_output *output = to_clk_si5341_output(hw);
751 if (index >= output->data->num_synth)
754 return si5341_output_reparent(output, index);
757 static u8 si5341_output_get_parent(struct clk_hw *hw)
759 struct clk_si5341_output *output = to_clk_si5341_output(hw);
763 err = regmap_read(output->data->regmap,
764 SI5341_OUT_MUX_SEL(output), &val);
769 static const struct clk_ops si5341_output_clk_ops = {
770 .is_prepared = si5341_output_clk_is_on,
771 .prepare = si5341_output_clk_prepare,
772 .unprepare = si5341_output_clk_unprepare,
773 .recalc_rate = si5341_output_clk_recalc_rate,
774 .round_rate = si5341_output_clk_round_rate,
775 .set_rate = si5341_output_clk_set_rate,
776 .set_parent = si5341_output_set_parent,
777 .get_parent = si5341_output_get_parent,
781 * The chip can be bought in a pre-programmed version, or one can program the
782 * NVM in the chip to boot up in a preset mode. This routine tries to determine
783 * if that's the case, or if we need to reset and program everything from
784 * scratch. Returns negative error, or true/false.
786 static int si5341_is_programmed_already(struct clk_si5341 *data)
791 /* Read the PLL divider value, it must have a non-zero value */
792 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
797 return !!get_unaligned_le32(r);
800 static struct clk_hw *
801 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
803 struct clk_si5341 *data = _data;
804 unsigned int idx = clkspec->args[1];
805 unsigned int group = clkspec->args[0];
809 if (idx >= data->num_outputs) {
810 dev_err(&data->i2c_client->dev,
811 "invalid output index %u\n", idx);
812 return ERR_PTR(-EINVAL);
814 return &data->clk[idx].hw;
816 if (idx >= data->num_synth) {
817 dev_err(&data->i2c_client->dev,
818 "invalid synthesizer index %u\n", idx);
819 return ERR_PTR(-EINVAL);
821 return &data->synth[idx].hw;
824 dev_err(&data->i2c_client->dev,
825 "invalid PLL index %u\n", idx);
826 return ERR_PTR(-EINVAL);
830 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
831 return ERR_PTR(-EINVAL);
835 static int si5341_probe_chip_id(struct clk_si5341 *data)
841 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
844 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
848 model = get_unaligned_le16(reg);
850 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
851 model, reg[2], reg[3]);
855 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
856 data->num_synth = SI5340_NUM_SYNTH;
857 data->reg_output_offset = si5340_reg_output_offset;
858 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
861 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
862 data->num_synth = SI5341_NUM_SYNTH;
863 data->reg_output_offset = si5341_reg_output_offset;
864 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
867 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
875 /* Read active settings into the regmap cache for later reference */
876 static int si5341_read_settings(struct clk_si5341 *data)
882 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
886 err = regmap_bulk_read(data->regmap,
887 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
891 err = regmap_bulk_read(data->regmap,
892 SI5341_SYNTH_N_CLK_DIS, r, 1);
896 for (i = 0; i < data->num_synth; ++i) {
897 err = regmap_bulk_read(data->regmap,
898 SI5341_SYNTH_N_NUM(i), r, 10);
903 for (i = 0; i < data->num_outputs; ++i) {
904 err = regmap_bulk_read(data->regmap,
905 data->reg_output_offset[i], r, 4);
909 err = regmap_bulk_read(data->regmap,
910 data->reg_rdiv_offset[i], r, 3);
918 static int si5341_write_multiple(struct clk_si5341 *data,
919 const struct si5341_reg_default *values, unsigned int num_values)
924 for (i = 0; i < num_values; ++i) {
925 res = regmap_write(data->regmap,
926 values[i].address, values[i].value);
928 dev_err(&data->i2c_client->dev,
929 "Failed to write %#x:%#x\n",
930 values[i].address, values[i].value);
938 static const struct si5341_reg_default si5341_preamble[] = {
946 static int si5341_send_preamble(struct clk_si5341 *data)
951 /* For revision 2 and up, the values are slightly different */
952 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
956 /* Write "preamble" as specified by datasheet */
957 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
960 res = si5341_write_multiple(data,
961 si5341_preamble, ARRAY_SIZE(si5341_preamble));
965 /* Datasheet specifies a 300ms wait after sending the preamble */
971 /* Perform a soft reset and write post-amble */
972 static int si5341_finalize_defaults(struct clk_si5341 *data)
977 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
981 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
983 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
987 /* Datasheet does not explain these nameless registers */
988 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
991 res = regmap_write(data->regmap, 0x0B25, 0x02);
999 static const struct regmap_range si5341_regmap_volatile_range[] = {
1000 regmap_reg_range(0x000C, 0x0012), /* Status */
1001 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1002 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1003 /* Update bits for synth config */
1004 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1005 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1006 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1007 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1008 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1011 static const struct regmap_access_table si5341_regmap_volatile = {
1012 .yes_ranges = si5341_regmap_volatile_range,
1013 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1016 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1017 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1020 .range_max = SI5341_REGISTER_MAX,
1021 .selector_reg = SI5341_PAGE,
1022 .selector_mask = 0xff,
1023 .selector_shift = 0,
1029 static const struct regmap_config si5341_regmap_config = {
1032 .cache_type = REGCACHE_RBTREE,
1033 .ranges = si5341_regmap_ranges,
1034 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1035 .max_register = SI5341_REGISTER_MAX,
1036 .volatile_table = &si5341_regmap_volatile,
1039 static int si5341_dt_parse_dt(struct i2c_client *client,
1040 struct clk_si5341_output_config *config)
1042 struct device_node *child;
1043 struct device_node *np = client->dev.of_node;
1047 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1048 SI5341_MAX_NUM_OUTPUTS);
1050 for_each_child_of_node(np, child) {
1051 if (of_property_read_u32(child, "reg", &num)) {
1052 dev_err(&client->dev, "missing reg property of %s\n",
1057 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1058 dev_err(&client->dev, "invalid clkout %d\n", num);
1062 if (!of_property_read_u32(child, "silabs,format", &val)) {
1063 /* Set cm and ampl conservatively to 3v3 settings */
1065 case 1: /* normal differential */
1066 config[num].out_cm_ampl_bits = 0x33;
1068 case 2: /* low-power differential */
1069 config[num].out_cm_ampl_bits = 0x13;
1071 case 4: /* LVCMOS */
1072 config[num].out_cm_ampl_bits = 0x33;
1073 /* Set SI recommended impedance for LVCMOS */
1074 config[num].out_format_drv_bits |= 0xc0;
1077 dev_err(&client->dev,
1078 "invalid silabs,format %u for %u\n",
1082 config[num].out_format_drv_bits &= ~0x07;
1083 config[num].out_format_drv_bits |= val & 0x07;
1084 /* Always enable the SYNC feature */
1085 config[num].out_format_drv_bits |= 0x08;
1088 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1090 dev_err(&client->dev,
1091 "invalid silabs,common-mode %u\n",
1095 config[num].out_cm_ampl_bits &= 0xf0;
1096 config[num].out_cm_ampl_bits |= val & 0x0f;
1099 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1101 dev_err(&client->dev,
1102 "invalid silabs,amplitude %u\n",
1106 config[num].out_cm_ampl_bits &= 0x0f;
1107 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1110 if (of_property_read_bool(child, "silabs,disable-high"))
1111 config[num].out_format_drv_bits |= 0x10;
1113 config[num].synth_master =
1114 of_property_read_bool(child, "silabs,synth-master");
1116 config[num].always_on =
1117 of_property_read_bool(child, "always-on");
1128 * If not pre-configured, calculate and set the PLL configuration manually.
1129 * For low-jitter performance, the PLL should be set such that the synthesizers
1130 * only need integer division.
1131 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1132 * the chip to generate any frequency on its outputs, but jitter performance
1133 * may be sub-optimal.
1135 static int si5341_initialize_pll(struct clk_si5341 *data)
1137 struct device_node *np = data->i2c_client->dev.of_node;
1141 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1142 dev_err(&data->i2c_client->dev,
1143 "PLL configuration requires silabs,pll-m-num\n");
1145 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1146 dev_err(&data->i2c_client->dev,
1147 "PLL configuration requires silabs,pll-m-den\n");
1150 if (!m_num || !m_den) {
1151 dev_err(&data->i2c_client->dev,
1152 "PLL configuration invalid, assume 14GHz\n");
1153 m_den = clk_get_rate(data->pxtal) / 10;
1157 return si5341_encode_44_32(data->regmap,
1158 SI5341_PLL_M_NUM, m_num, m_den);
1161 static int si5341_probe(struct i2c_client *client,
1162 const struct i2c_device_id *id)
1164 struct clk_si5341 *data;
1165 struct clk_init_data init;
1166 const char *root_clock_name;
1167 const char *synth_clock_names[SI5341_NUM_SYNTH];
1170 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1171 bool initialization_required;
1173 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1177 data->i2c_client = client;
1179 data->pxtal = devm_clk_get(&client->dev, "xtal");
1180 if (IS_ERR(data->pxtal)) {
1181 if (PTR_ERR(data->pxtal) == -EPROBE_DEFER)
1182 return -EPROBE_DEFER;
1184 dev_err(&client->dev, "Missing xtal clock input\n");
1187 err = si5341_dt_parse_dt(client, config);
1191 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1193 init.name = client->dev.of_node->name;
1194 root_clock_name = init.name;
1196 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1197 if (IS_ERR(data->regmap))
1198 return PTR_ERR(data->regmap);
1200 i2c_set_clientdata(client, data);
1202 err = si5341_probe_chip_id(data);
1206 /* "Activate" the xtal (usually a fixed clock) */
1207 clk_prepare_enable(data->pxtal);
1209 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1210 initialization_required = true;
1212 err = si5341_is_programmed_already(data);
1216 initialization_required = !err;
1219 if (initialization_required) {
1220 /* Populate the regmap cache in preparation for "cache only" */
1221 err = si5341_read_settings(data);
1225 err = si5341_send_preamble(data);
1230 * We intend to send all 'final' register values in a single
1231 * transaction. So cache all register writes until we're done
1234 regcache_cache_only(data->regmap, true);
1236 /* Write the configuration pairs from the firmware blob */
1237 err = si5341_write_multiple(data, si5341_reg_defaults,
1238 ARRAY_SIZE(si5341_reg_defaults));
1242 /* PLL configuration is required */
1243 err = si5341_initialize_pll(data);
1248 /* Register the PLL */
1249 data->pxtal_name = __clk_get_name(data->pxtal);
1250 init.parent_names = &data->pxtal_name;
1251 init.num_parents = 1; /* For now, only XTAL input supported */
1252 init.ops = &si5341_clk_ops;
1254 data->hw.init = &init;
1256 err = devm_clk_hw_register(&client->dev, &data->hw);
1258 dev_err(&client->dev, "clock registration failed\n");
1262 init.num_parents = 1;
1263 init.parent_names = &root_clock_name;
1264 init.ops = &si5341_synth_clk_ops;
1265 for (i = 0; i < data->num_synth; ++i) {
1266 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1267 "%s.N%u", client->dev.of_node->name, i);
1268 init.name = synth_clock_names[i];
1269 data->synth[i].index = i;
1270 data->synth[i].data = data;
1271 data->synth[i].hw.init = &init;
1272 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1274 dev_err(&client->dev,
1275 "synth N%u registration failed\n", i);
1279 init.num_parents = data->num_synth;
1280 init.parent_names = synth_clock_names;
1281 init.ops = &si5341_output_clk_ops;
1282 for (i = 0; i < data->num_outputs; ++i) {
1283 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1284 client->dev.of_node->name, i);
1285 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1286 data->clk[i].index = i;
1287 data->clk[i].data = data;
1288 data->clk[i].hw.init = &init;
1289 if (config[i].out_format_drv_bits & 0x07) {
1290 regmap_write(data->regmap,
1291 SI5341_OUT_FORMAT(&data->clk[i]),
1292 config[i].out_format_drv_bits);
1293 regmap_write(data->regmap,
1294 SI5341_OUT_CM(&data->clk[i]),
1295 config[i].out_cm_ampl_bits);
1297 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1298 kfree(init.name); /* clock framework made a copy of the name */
1300 dev_err(&client->dev,
1301 "output %u registration failed\n", i);
1304 if (config[i].always_on)
1305 clk_prepare(data->clk[i].hw.clk);
1308 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
1311 dev_err(&client->dev, "unable to add clk provider\n");
1315 if (initialization_required) {
1317 regcache_cache_only(data->regmap, false);
1318 err = regcache_sync(data->regmap);
1322 err = si5341_finalize_defaults(data);
1327 /* Free the names, clk framework makes copies */
1328 for (i = 0; i < data->num_synth; ++i)
1329 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1334 static const struct i2c_device_id si5341_id[] = {
1339 MODULE_DEVICE_TABLE(i2c, si5341_id);
1341 static const struct of_device_id clk_si5341_of_match[] = {
1342 { .compatible = "silabs,si5340" },
1343 { .compatible = "silabs,si5341" },
1346 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1348 static struct i2c_driver si5341_driver = {
1351 .of_match_table = clk_si5341_of_match,
1353 .probe = si5341_probe,
1354 .id_table = si5341_id,
1356 module_i2c_driver(si5341_driver);
1358 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1359 MODULE_DESCRIPTION("Si5341 driver");
1360 MODULE_LICENSE("GPL");