2 * Copyright (C) 2014 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Adjustable fractional divider clock implementation.
9 * Output rate = (m / n) * parent_rate.
10 * Uses rational best approximation algorithm.
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/device.h>
16 #include <linux/slab.h>
17 #include <linux/rational.h>
19 static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
20 unsigned long parent_rate)
22 struct clk_fractional_divider *fd = to_clk_fd(hw);
23 unsigned long flags = 0;
29 spin_lock_irqsave(fd->lock, flags);
33 val = clk_readl(fd->reg);
36 spin_unlock_irqrestore(fd->lock, flags);
40 m = (val & fd->mmask) >> fd->mshift;
41 n = (val & fd->nmask) >> fd->nshift;
46 ret = (u64)parent_rate * m;
52 static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
53 unsigned long *parent_rate)
55 struct clk_fractional_divider *fd = to_clk_fd(hw);
60 if (!rate || rate >= *parent_rate)
64 * Get rate closer to *parent_rate to guarantee there is no overflow
65 * for m and n. In the result it will be the nearest rate left shifted
66 * by (scale - fd->nwidth) bits.
68 scale = fls_long(*parent_rate / rate - 1);
69 if (scale > fd->nwidth)
70 rate <<= scale - fd->nwidth;
72 rational_best_approximation(rate, *parent_rate,
73 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
76 ret = (u64)*parent_rate * m;
82 static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
83 unsigned long parent_rate)
85 struct clk_fractional_divider *fd = to_clk_fd(hw);
86 unsigned long flags = 0;
90 rational_best_approximation(rate, parent_rate,
91 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
95 spin_lock_irqsave(fd->lock, flags);
99 val = clk_readl(fd->reg);
100 val &= ~(fd->mmask | fd->nmask);
101 val |= (m << fd->mshift) | (n << fd->nshift);
102 clk_writel(val, fd->reg);
105 spin_unlock_irqrestore(fd->lock, flags);
112 const struct clk_ops clk_fractional_divider_ops = {
113 .recalc_rate = clk_fd_recalc_rate,
114 .round_rate = clk_fd_round_rate,
115 .set_rate = clk_fd_set_rate,
117 EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
119 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
120 const char *name, const char *parent_name, unsigned long flags,
121 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
122 u8 clk_divider_flags, spinlock_t *lock)
124 struct clk_fractional_divider *fd;
125 struct clk_init_data init;
129 fd = kzalloc(sizeof(*fd), GFP_KERNEL);
131 return ERR_PTR(-ENOMEM);
134 init.ops = &clk_fractional_divider_ops;
135 init.flags = flags | CLK_IS_BASIC;
136 init.parent_names = parent_name ? &parent_name : NULL;
137 init.num_parents = parent_name ? 1 : 0;
142 fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
145 fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
146 fd->flags = clk_divider_flags;
151 ret = clk_hw_register(dev, hw);
159 EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);
161 struct clk *clk_register_fractional_divider(struct device *dev,
162 const char *name, const char *parent_name, unsigned long flags,
163 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
164 u8 clk_divider_flags, spinlock_t *lock)
168 hw = clk_hw_register_fractional_divider(dev, name, parent_name, flags,
169 reg, mshift, mwidth, nshift, nwidth, clk_divider_flags,
175 EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
177 void clk_hw_unregister_fractional_divider(struct clk_hw *hw)
179 struct clk_fractional_divider *fd;
183 clk_hw_unregister(hw);