2 * Cirrus Logic CLPS711X CLK driver
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk-provider.h>
13 #include <linux/clkdev.h>
15 #include <linux/ioport.h>
16 #include <linux/of_address.h>
17 #include <linux/slab.h>
18 #include <linux/mfd/syscon/clps711x.h>
20 #include <dt-bindings/clock/clps711x-clock.h>
22 #define CLPS711X_SYSCON1 (0x0100)
23 #define CLPS711X_SYSCON2 (0x1100)
24 #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
25 #define CLPS711X_PLLR (0xa5a8)
27 #define CLPS711X_EXT_FREQ (13000000)
28 #define CLPS711X_OSC_FREQ (3686400)
30 static const struct clk_div_table spi_div_table[] = {
31 { .val = 0, .div = 32, },
32 { .val = 1, .div = 8, },
33 { .val = 2, .div = 2, },
34 { .val = 3, .div = 1, },
38 static const struct clk_div_table timer_div_table[] = {
39 { .val = 0, .div = 256, },
40 { .val = 1, .div = 1, },
46 struct clk_hw_onecell_data clk_data;
49 static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,
52 u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi;
53 struct clps711x_clk *clps711x_clk;
57 return ERR_PTR(-ENOMEM);
59 clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
63 return ERR_PTR(-ENOMEM);
65 spin_lock_init(&clps711x_clk->lock);
67 /* Read PLL multiplier value and sanity check */
68 tmp = readl(base + CLPS711X_PLLR) >> 24;
69 if (((tmp >= 10) && (tmp <= 50)) || !fref)
70 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
74 tmp = readl(base + CLPS711X_SYSFLG2);
75 if (tmp & SYSFLG2_CKMODE) {
76 f_cpu = CLPS711X_EXT_FREQ;
77 f_bus = CLPS711X_EXT_FREQ;
78 f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
80 f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
84 f_bus = DIV_ROUND_UP(f_cpu, 2);
87 f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
88 f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
91 if (tmp & SYSFLG2_CKMODE) {
92 if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
93 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
95 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
97 f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
99 tmp = readl(base + CLPS711X_SYSCON1);
100 /* Timer1 in free running mode.
101 * Counter will wrap around to 0xffff when it underflows
102 * and will continue to count down.
104 tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
105 /* Timer2 in prescale mode.
106 * Value writen is automatically re-loaded when
107 * the counter underflows.
109 tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
110 writel(tmp, base + CLPS711X_SYSCON1);
112 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
113 clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
114 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
115 clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
116 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
117 clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
118 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
119 clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
120 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
121 clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
122 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
123 clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
124 base + CLPS711X_SYSCON1, 5, 1, 0,
125 timer_div_table, &clps711x_clk->lock);
126 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
127 clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
128 base + CLPS711X_SYSCON1, 7, 1, 0,
129 timer_div_table, &clps711x_clk->lock);
130 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
131 clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
132 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
133 clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
134 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
135 clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
136 base + CLPS711X_SYSCON1, 16, 2, 0,
137 spi_div_table, &clps711x_clk->lock);
138 clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
139 clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
140 clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
141 clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
142 for (i = 0; i < CLPS711X_CLK_MAX; i++)
143 if (IS_ERR(clps711x_clk->clk_data.hws[i]))
144 pr_err("clk %i: register failed with %ld\n",
145 i, PTR_ERR(clps711x_clk->clk_data.hws[i]));
150 void __init clps711x_clk_init(void __iomem *base)
152 struct clps711x_clk *clps711x_clk;
154 clps711x_clk = _clps711x_clk_init(base, 73728000);
156 BUG_ON(IS_ERR(clps711x_clk));
159 clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1],
160 NULL, "clps711x-timer.0");
161 clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2],
162 NULL, "clps711x-timer.1");
165 clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM],
166 NULL, "clps711x-pwm");
167 clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
168 NULL, "clps711x-uart.0");
169 clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
170 NULL, "clps711x-uart.1");
174 static void __init clps711x_clk_init_dt(struct device_node *np)
176 void __iomem *base = of_iomap(np, 0);
177 struct clps711x_clk *clps711x_clk;
180 WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
182 clps711x_clk = _clps711x_clk_init(base, fref);
183 BUG_ON(IS_ERR(clps711x_clk));
185 clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
186 of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
187 &clps711x_clk->clk_data);
189 CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);