1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/platform_device.h>
10 #include <linux/clk-provider.h>
11 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/err.h>
17 #define AXI_CLKGEN_V2_REG_RESET 0x40
18 #define AXI_CLKGEN_V2_REG_CLKSEL 0x44
19 #define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
20 #define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
22 #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
23 #define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
25 #define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
26 #define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
28 #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
30 #define MMCM_REG_CLKOUT5_2 0x07
31 #define MMCM_REG_CLKOUT0_1 0x08
32 #define MMCM_REG_CLKOUT0_2 0x09
33 #define MMCM_REG_CLKOUT6_2 0x13
34 #define MMCM_REG_CLK_FB1 0x14
35 #define MMCM_REG_CLK_FB2 0x15
36 #define MMCM_REG_CLK_DIV 0x16
37 #define MMCM_REG_LOCK1 0x18
38 #define MMCM_REG_LOCK2 0x19
39 #define MMCM_REG_LOCK3 0x1a
40 #define MMCM_REG_POWER 0x28
41 #define MMCM_REG_FILTER1 0x4e
42 #define MMCM_REG_FILTER2 0x4f
44 #define MMCM_CLKOUT_NOCOUNT BIT(6)
46 #define MMCM_CLK_DIV_DIVIDE BIT(11)
47 #define MMCM_CLK_DIV_NOCOUNT BIT(12)
54 static uint32_t axi_clkgen_lookup_filter(unsigned int m)
84 static const uint32_t axi_clkgen_lock_table[] = {
85 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
86 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
87 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
88 0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
89 0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
90 0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
91 0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
92 0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
93 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
96 static uint32_t axi_clkgen_lookup_lock(unsigned int m)
98 if (m < ARRAY_SIZE(axi_clkgen_lock_table))
99 return axi_clkgen_lock_table[m];
103 static const unsigned int fpfd_min = 10000;
104 static const unsigned int fpfd_max = 300000;
105 static const unsigned int fvco_min = 600000;
106 static const unsigned int fvco_max = 1200000;
108 static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
109 unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
111 unsigned long d, d_min, d_max, _d_min, _d_max;
112 unsigned long m, m_min, m_max;
113 unsigned long f, dout, best_f, fvco;
114 unsigned long fract_shift = 0;
115 unsigned long fvco_min_fract, fvco_max_fract;
125 d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
126 d_max = min_t(unsigned long, fin / fpfd_min, 80);
129 fvco_min_fract = fvco_min << fract_shift;
130 fvco_max_fract = fvco_max << fract_shift;
132 m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
133 m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
135 for (m = m_min; m <= m_max; m++) {
136 _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
137 _d_max = min(d_max, fin * m / fvco_min_fract);
139 for (d = _d_min; d <= _d_max; d++) {
142 dout = DIV_ROUND_CLOSEST(fvco, fout);
143 dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
145 if (abs(f - fout) < abs(best_f - fout)) {
148 *best_m = m << (3 - fract_shift);
149 *best_dout = dout << (3 - fract_shift);
156 /* Lets see if we find a better setting in fractional mode */
157 if (fract_shift == 0) {
163 struct axi_clkgen_div_params {
167 unsigned int nocount;
168 unsigned int frac_en;
170 unsigned int frac_wf_f;
171 unsigned int frac_wf_r;
172 unsigned int frac_phase;
175 static void axi_clkgen_calc_clk_params(unsigned int divider,
176 unsigned int frac_divider, struct axi_clkgen_div_params *params)
179 memset(params, 0x0, sizeof(*params));
186 if (frac_divider == 0) {
187 params->high = divider / 2;
188 params->edge = divider % 2;
189 params->low = divider - params->high;
192 params->frac = frac_divider;
194 params->high = divider / 2;
195 params->edge = divider % 2;
196 params->low = params->high;
198 if (params->edge == 0) {
200 params->frac_wf_r = 1;
203 if (params->edge == 0 || frac_divider == 1)
205 if (((params->edge == 0) ^ (frac_divider == 1)) ||
206 (divider == 2 && frac_divider == 1))
207 params->frac_wf_f = 1;
209 params->frac_phase = params->edge * 4 + frac_divider / 2;
213 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
214 unsigned int reg, unsigned int val)
216 writel(val, axi_clkgen->base + reg);
219 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
220 unsigned int reg, unsigned int *val)
222 *val = readl(axi_clkgen->base + reg);
225 static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
227 unsigned int timeout = 10000;
231 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
232 } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
234 if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
240 static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
241 unsigned int reg, unsigned int *val)
243 unsigned int reg_val;
246 ret = axi_clkgen_wait_non_busy(axi_clkgen);
250 reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
251 reg_val |= (reg << 16);
253 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
255 ret = axi_clkgen_wait_non_busy(axi_clkgen);
264 static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
265 unsigned int reg, unsigned int val, unsigned int mask)
267 unsigned int reg_val = 0;
270 ret = axi_clkgen_wait_non_busy(axi_clkgen);
274 if (mask != 0xffff) {
275 axi_clkgen_mmcm_read(axi_clkgen, reg, ®_val);
279 reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
281 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
286 static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
289 unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
292 val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
294 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
297 static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
299 return container_of(clk_hw, struct axi_clkgen, clk_hw);
302 static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
303 unsigned int reg1, unsigned int reg2, unsigned int reg3,
304 struct axi_clkgen_div_params *params)
306 axi_clkgen_mmcm_write(axi_clkgen, reg1,
307 (params->high << 6) | params->low, 0xefff);
308 axi_clkgen_mmcm_write(axi_clkgen, reg2,
309 (params->frac << 12) | (params->frac_en << 11) |
310 (params->frac_wf_r << 10) | (params->edge << 7) |
311 (params->nocount << 6), 0x7fff);
313 axi_clkgen_mmcm_write(axi_clkgen, reg3,
314 (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
318 static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
319 unsigned long rate, unsigned long parent_rate)
321 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
322 unsigned int d, m, dout;
323 struct axi_clkgen_div_params params;
328 if (parent_rate == 0 || rate == 0)
331 axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
333 if (d == 0 || dout == 0 || m == 0)
336 if ((dout & 0x7) != 0 || (m & 0x7) != 0)
339 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
341 filter = axi_clkgen_lookup_filter(m - 1);
342 lock = axi_clkgen_lookup_lock(m - 1);
344 axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms);
345 axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
346 MMCM_REG_CLKOUT5_2, ¶ms);
348 axi_clkgen_calc_clk_params(d, 0, ¶ms);
349 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
350 (params.edge << 13) | (params.nocount << 12) |
351 (params.high << 6) | params.low, 0x3fff);
353 axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms);
354 axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
355 MMCM_REG_CLKOUT6_2, ¶ms);
357 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
358 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
359 (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
360 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
361 (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
362 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
363 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
368 static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
369 unsigned long *parent_rate)
371 unsigned int d, m, dout;
372 unsigned long long tmp;
374 axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
376 if (d == 0 || dout == 0 || m == 0)
379 tmp = (unsigned long long)*parent_rate * m;
380 tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
382 return min_t(unsigned long long, tmp, LONG_MAX);
385 static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
386 unsigned int reg1, unsigned int reg2)
388 unsigned int val1, val2;
391 axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
392 if (val2 & MMCM_CLKOUT_NOCOUNT)
395 axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
397 div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
400 if (val2 & MMCM_CLK_DIV_DIVIDE) {
401 if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
406 div += (val2 >> 12) & 0x7;
412 static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
413 unsigned long parent_rate)
415 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
416 unsigned int d, m, dout;
417 unsigned long long tmp;
420 dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
422 m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
425 axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
426 if (val & MMCM_CLK_DIV_NOCOUNT)
429 d = (val & 0x3f) + ((val >> 6) & 0x3f);
431 if (d == 0 || dout == 0)
434 tmp = (unsigned long long)parent_rate * m;
435 tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
437 return min_t(unsigned long long, tmp, ULONG_MAX);
440 static int axi_clkgen_enable(struct clk_hw *clk_hw)
442 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
444 axi_clkgen_mmcm_enable(axi_clkgen, true);
449 static void axi_clkgen_disable(struct clk_hw *clk_hw)
451 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
453 axi_clkgen_mmcm_enable(axi_clkgen, false);
456 static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
458 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
460 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
465 static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
467 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
470 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
475 static const struct clk_ops axi_clkgen_ops = {
476 .recalc_rate = axi_clkgen_recalc_rate,
477 .round_rate = axi_clkgen_round_rate,
478 .set_rate = axi_clkgen_set_rate,
479 .enable = axi_clkgen_enable,
480 .disable = axi_clkgen_disable,
481 .set_parent = axi_clkgen_set_parent,
482 .get_parent = axi_clkgen_get_parent,
485 static const struct of_device_id axi_clkgen_ids[] = {
487 .compatible = "adi,axi-clkgen-2.00.a",
491 MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
493 static int axi_clkgen_probe(struct platform_device *pdev)
495 const struct of_device_id *id;
496 struct axi_clkgen *axi_clkgen;
497 struct clk_init_data init;
498 const char *parent_names[2];
499 const char *clk_name;
500 struct resource *mem;
504 if (!pdev->dev.of_node)
507 id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
511 axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
515 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
516 axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
517 if (IS_ERR(axi_clkgen->base))
518 return PTR_ERR(axi_clkgen->base);
520 init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
521 if (init.num_parents < 1 || init.num_parents > 2)
524 for (i = 0; i < init.num_parents; i++) {
525 parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
526 if (!parent_names[i])
530 clk_name = pdev->dev.of_node->name;
531 of_property_read_string(pdev->dev.of_node, "clock-output-names",
534 init.name = clk_name;
535 init.ops = &axi_clkgen_ops;
536 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
537 init.parent_names = parent_names;
539 axi_clkgen_mmcm_enable(axi_clkgen, false);
541 axi_clkgen->clk_hw.init = &init;
542 ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
546 return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
547 &axi_clkgen->clk_hw);
550 static int axi_clkgen_remove(struct platform_device *pdev)
552 of_clk_del_provider(pdev->dev.of_node);
557 static struct platform_driver axi_clkgen_driver = {
559 .name = "adi-axi-clkgen",
560 .of_match_table = axi_clkgen_ids,
562 .probe = axi_clkgen_probe,
563 .remove = axi_clkgen_remove,
565 module_platform_driver(axi_clkgen_driver);
567 MODULE_LICENSE("GPL v2");
568 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
569 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");