1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2014 Broadcom Corporation */
7 #include <linux/kernel.h>
8 #include <linux/list.h>
9 #include <linux/spinlock.h>
10 #include <linux/slab.h>
11 #include <linux/device.h>
13 #include <linux/clk-provider.h>
15 #define IPROC_CLK_NAME_LEN 25
16 #define IPROC_CLK_INVALID_OFFSET 0xffffffff
17 #define bit_mask(width) ((1 << (width)) - 1)
19 /* clocks that should not be disabled at runtime */
20 #define IPROC_CLK_AON BIT(0)
22 /* PLL that requires gating through ASIU */
23 #define IPROC_CLK_PLL_ASIU BIT(1)
25 /* PLL that has fractional part of the NDIV */
26 #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
30 * of the same register following the write to flush the write transaction into
31 * the intended register
33 #define IPROC_CLK_NEEDS_READ_BACK BIT(3)
36 * Some PLLs require the PLL SW override bit to be set before changes can be
39 #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
43 * the PLL control register
45 #define IPROC_CLK_EMBED_PWRCTRL BIT(5)
48 * Some PLLs have separate registers for Status and Control. Identify this to
49 * let the driver know if additional registers need to be used
51 #define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6)
54 * Some PLLs have an additional divide by 2 in master clock calculation;
55 * MCLK = VCO_freq / (Mdiv * 2). Identify this to let the driver know
56 * of modified calculations
58 #define IPROC_CLK_MCLK_DIV_BY_2 BIT(7)
61 * Some PLLs provide a look up table for the leaf clock frequencies and
62 * auto calculates VCO frequency parameters based on the provided leaf
63 * clock frequencies. They have a user mode that allows the divider
64 * controls to be determined by the user
66 #define IPROC_CLK_PLL_USER_MODE_ON BIT(8)
69 * Some PLLs have an active low reset
71 #define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)
74 * Calculate the PLL parameters are runtime, instead of using table
76 #define IPROC_CLK_PLL_CALC_PARAM BIT(10)
79 * Parameters for VCO frequency configuration
82 * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency / pdiv)
84 struct iproc_pll_vco_param {
86 unsigned int ndiv_int;
87 unsigned int ndiv_frac;
91 struct iproc_clk_reg_op {
98 * Clock gating control at the top ASIU level
100 struct iproc_asiu_gate {
102 unsigned int en_shift;
106 * Control of powering on/off of a PLL
108 * Before powering off a PLL, input isolation (ISO) needs to be enabled
110 struct iproc_pll_aon_pwr_ctrl {
112 unsigned int pwr_width;
113 unsigned int pwr_shift;
114 unsigned int iso_shift;
118 * Control of the PLL reset
120 struct iproc_pll_reset_ctrl {
122 unsigned int reset_shift;
123 unsigned int p_reset_shift;
127 * Control of the Ki, Kp, and Ka parameters
129 struct iproc_pll_dig_filter_ctrl {
131 unsigned int ki_shift;
132 unsigned int ki_width;
133 unsigned int kp_shift;
134 unsigned int kp_width;
135 unsigned int ka_shift;
136 unsigned int ka_width;
140 * To enable SW control of the PLL
142 struct iproc_pll_sw_ctrl {
147 struct iproc_pll_vco_ctrl {
148 unsigned int u_offset;
149 unsigned int l_offset;
153 * Main PLL control parameters
155 struct iproc_pll_ctrl {
157 struct iproc_pll_aon_pwr_ctrl aon;
158 struct iproc_asiu_gate asiu;
159 struct iproc_pll_reset_ctrl reset;
160 struct iproc_pll_dig_filter_ctrl dig_filter;
161 struct iproc_pll_sw_ctrl sw_ctrl;
162 struct iproc_clk_reg_op ndiv_int;
163 struct iproc_clk_reg_op ndiv_frac;
164 struct iproc_clk_reg_op pdiv;
165 struct iproc_pll_vco_ctrl vco_ctrl;
166 struct iproc_clk_reg_op status;
167 struct iproc_clk_reg_op macro_mode;
171 * Controls enabling/disabling a PLL derived clock
173 struct iproc_clk_enable_ctrl {
175 unsigned int enable_shift;
176 unsigned int hold_shift;
177 unsigned int bypass_shift;
181 * Main clock control parameters for clocks derived from the PLLs
183 struct iproc_clk_ctrl {
184 unsigned int channel;
186 struct iproc_clk_enable_ctrl enable;
187 struct iproc_clk_reg_op mdiv;
191 * Divisor of the ASIU clocks
193 struct iproc_asiu_div {
195 unsigned int en_shift;
196 unsigned int high_shift;
197 unsigned int high_width;
198 unsigned int low_shift;
199 unsigned int low_width;
202 void iproc_armpll_setup(struct device_node *node);
203 void iproc_pll_clk_setup(struct device_node *node,
204 const struct iproc_pll_ctrl *pll_ctrl,
205 const struct iproc_pll_vco_param *vco,
206 unsigned int num_vco_entries,
207 const struct iproc_clk_ctrl *clk_ctrl,
208 unsigned int num_clks);
209 void iproc_asiu_setup(struct device_node *node,
210 const struct iproc_asiu_div *div,
211 const struct iproc_asiu_gate *gate,
212 unsigned int num_clks);
214 #endif /* _CLK_IPROC_H */