2 * Copyright (C) 2014 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/err.h>
16 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
23 #include "clk-iproc.h"
25 #define PLL_VCO_HIGH_SHIFT 19
26 #define PLL_VCO_LOW_SHIFT 30
29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
32 #define PLL_USER_MODE 7
34 /* number of delay loops waiting for PLL to lock */
35 #define LOCK_DELAY 100
37 /* number of VCO frequency bands */
38 #define NUM_FREQ_BANDS 8
40 #define NUM_KP_BANDS 3
47 static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = {
48 { 5, 6, 6, 7, 7, 8, 9, 10 },
49 { 4, 4, 5, 5, 6, 7, 8, 9 },
50 { 4, 5, 5, 6, 7, 8, 9, 10 },
53 static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = {
54 { 10000000, 12500000 },
55 { 12500000, 15000000 },
56 { 15000000, 20000000 },
57 { 20000000, 25000000 },
58 { 25000000, 50000000 },
59 { 50000000, 75000000 },
60 { 75000000, 100000000 },
61 { 100000000, 125000000 },
66 VCO_MID = 1200000000U,
67 VCO_HIGH = 2200000000U,
68 VCO_HIGH_HIGH = 3100000000U,
69 VCO_MAX = 4000000000U,
73 void __iomem *status_base;
74 void __iomem *control_base;
75 void __iomem *pwr_base;
76 void __iomem *asiu_base;
78 const struct iproc_pll_ctrl *ctrl;
79 const struct iproc_pll_vco_param *vco_param;
80 unsigned int num_vco_entries;
85 struct iproc_pll *pll;
86 const struct iproc_clk_ctrl *ctrl;
89 #define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw)
92 * Based on the target frequency, find a match from the VCO frequency parameter
93 * table and return its index
95 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate)
99 for (i = 0; i < pll->num_vco_entries; i++)
100 if (target_rate == pll->vco_param[i].rate)
103 if (i >= pll->num_vco_entries)
109 static int get_kp(unsigned long ref_freq, enum kp_band kp_index)
113 if (ref_freq < ref_freq_table[0][0])
116 for (i = 0; i < NUM_FREQ_BANDS; i++) {
117 if (ref_freq >= ref_freq_table[i][0] &&
118 ref_freq < ref_freq_table[i][1])
119 return kp_table[kp_index][i];
124 static int pll_wait_for_lock(struct iproc_pll *pll)
127 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
129 for (i = 0; i < LOCK_DELAY; i++) {
130 u32 val = readl(pll->status_base + ctrl->status.offset);
132 if (val & (1 << ctrl->status.shift))
140 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base,
141 const u32 offset, u32 val)
143 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
145 writel(val, base + offset);
147 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK &&
148 (base == pll->status_base || base == pll->control_base)))
149 val = readl(base + offset);
152 static void __pll_disable(struct iproc_pll *pll)
154 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
157 if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
158 val = readl(pll->asiu_base + ctrl->asiu.offset);
159 val &= ~(1 << ctrl->asiu.en_shift);
160 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
163 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
164 val = readl(pll->control_base + ctrl->aon.offset);
165 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
166 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
170 /* latch input value so core power can be shut down */
171 val = readl(pll->pwr_base + ctrl->aon.offset);
172 val |= 1 << ctrl->aon.iso_shift;
173 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
175 /* power down the core */
176 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
177 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
181 static int __pll_enable(struct iproc_pll *pll)
183 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
186 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
187 val = readl(pll->control_base + ctrl->aon.offset);
188 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
189 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
193 /* power up the PLL and make sure it's not latched */
194 val = readl(pll->pwr_base + ctrl->aon.offset);
195 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
196 val &= ~(1 << ctrl->aon.iso_shift);
197 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
200 /* certain PLLs also need to be ungated from the ASIU top level */
201 if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
202 val = readl(pll->asiu_base + ctrl->asiu.offset);
203 val |= (1 << ctrl->asiu.en_shift);
204 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
210 static void __pll_put_in_reset(struct iproc_pll *pll)
213 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
214 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
216 val = readl(pll->control_base + reset->offset);
217 if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW)
218 val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift);
220 val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift));
221 iproc_pll_write(pll, pll->control_base, reset->offset, val);
224 static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
225 unsigned int ka, unsigned int ki)
228 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
229 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
230 const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter;
232 val = readl(pll->control_base + dig_filter->offset);
233 val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift |
234 bit_mask(dig_filter->kp_width) << dig_filter->kp_shift |
235 bit_mask(dig_filter->ka_width) << dig_filter->ka_shift);
236 val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift |
237 ka << dig_filter->ka_shift;
238 iproc_pll_write(pll, pll->control_base, dig_filter->offset, val);
240 val = readl(pll->control_base + reset->offset);
241 if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW)
242 val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift));
244 val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift);
245 iproc_pll_write(pll, pll->control_base, reset->offset, val);
248 static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
249 unsigned long parent_rate)
251 struct iproc_pll *pll = clk->pll;
252 const struct iproc_pll_vco_param *vco = &pll->vco_param[rate_index];
253 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
254 int ka = 0, ki, kp, ret;
255 unsigned long rate = vco->rate;
257 enum kp_band kp_index;
258 unsigned long ref_freq;
259 const char *clk_name = clk_hw_get_name(&clk->hw);
262 * reference frequency = parent frequency / PDIV
263 * If PDIV = 0, then it becomes a multiplier (x2)
266 ref_freq = parent_rate * 2;
268 ref_freq = parent_rate / vco->pdiv;
270 /* determine Ki and Kp index based on target VCO frequency */
271 if (rate >= VCO_LOW && rate < VCO_HIGH) {
273 kp_index = KP_BAND_MID;
274 } else if (rate >= VCO_HIGH && rate < VCO_HIGH_HIGH) {
276 kp_index = KP_BAND_HIGH;
277 } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) {
279 kp_index = KP_BAND_HIGH_HIGH;
281 pr_err("%s: pll: %s has invalid rate: %lu\n", __func__,
286 kp = get_kp(ref_freq, kp_index);
288 pr_err("%s: pll: %s has invalid kp\n", __func__, clk_name);
292 ret = __pll_enable(pll);
294 pr_err("%s: pll: %s fails to enable\n", __func__, clk_name);
298 /* put PLL in reset */
299 __pll_put_in_reset(pll);
301 /* set PLL in user mode before modifying PLL controls */
302 if (ctrl->flags & IPROC_CLK_PLL_USER_MODE_ON) {
303 val = readl(pll->control_base + ctrl->macro_mode.offset);
304 val &= ~(bit_mask(ctrl->macro_mode.width) <<
305 ctrl->macro_mode.shift);
306 val |= PLL_USER_MODE << ctrl->macro_mode.shift;
307 iproc_pll_write(pll, pll->control_base,
308 ctrl->macro_mode.offset, val);
311 iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0);
313 val = readl(pll->control_base + ctrl->vco_ctrl.l_offset);
315 if (rate >= VCO_LOW && rate < VCO_MID)
316 val |= (1 << PLL_VCO_LOW_SHIFT);
319 val &= ~(1 << PLL_VCO_HIGH_SHIFT);
321 val |= (1 << PLL_VCO_HIGH_SHIFT);
323 iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val);
325 /* program integer part of NDIV */
326 val = readl(pll->control_base + ctrl->ndiv_int.offset);
327 val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift);
328 val |= vco->ndiv_int << ctrl->ndiv_int.shift;
329 iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val);
331 /* program fractional part of NDIV */
332 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
333 val = readl(pll->control_base + ctrl->ndiv_frac.offset);
334 val &= ~(bit_mask(ctrl->ndiv_frac.width) <<
335 ctrl->ndiv_frac.shift);
336 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift;
337 iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset,
342 val = readl(pll->control_base + ctrl->pdiv.offset);
343 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift);
344 val |= vco->pdiv << ctrl->pdiv.shift;
345 iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val);
347 __pll_bring_out_reset(pll, kp, ka, ki);
349 ret = pll_wait_for_lock(pll);
351 pr_err("%s: pll: %s failed to lock\n", __func__, clk_name);
358 static int iproc_pll_enable(struct clk_hw *hw)
360 struct iproc_clk *clk = to_iproc_clk(hw);
361 struct iproc_pll *pll = clk->pll;
363 return __pll_enable(pll);
366 static void iproc_pll_disable(struct clk_hw *hw)
368 struct iproc_clk *clk = to_iproc_clk(hw);
369 struct iproc_pll *pll = clk->pll;
370 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
372 if (ctrl->flags & IPROC_CLK_AON)
378 static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
379 unsigned long parent_rate)
381 struct iproc_clk *clk = to_iproc_clk(hw);
382 struct iproc_pll *pll = clk->pll;
383 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
385 u64 ndiv, ndiv_int, ndiv_frac;
389 if (parent_rate == 0)
392 /* PLL needs to be locked */
393 val = readl(pll->status_base + ctrl->status.offset);
394 if ((val & (1 << ctrl->status.shift)) == 0)
398 * PLL output frequency =
400 * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv)
402 val = readl(pll->control_base + ctrl->ndiv_int.offset);
403 ndiv_int = (val >> ctrl->ndiv_int.shift) &
404 bit_mask(ctrl->ndiv_int.width);
405 ndiv = ndiv_int << 20;
407 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
408 val = readl(pll->control_base + ctrl->ndiv_frac.offset);
409 ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
410 bit_mask(ctrl->ndiv_frac.width);
414 val = readl(pll->control_base + ctrl->pdiv.offset);
415 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
417 rate = (ndiv * parent_rate) >> 20;
427 static long iproc_pll_round_rate(struct clk_hw *hw, unsigned long rate,
428 unsigned long *parent_rate)
431 struct iproc_clk *clk = to_iproc_clk(hw);
432 struct iproc_pll *pll = clk->pll;
434 if (rate == 0 || *parent_rate == 0 || !pll->vco_param)
437 for (i = 0; i < pll->num_vco_entries; i++) {
438 if (rate <= pll->vco_param[i].rate)
442 if (i == pll->num_vco_entries)
445 return pll->vco_param[i].rate;
448 static int iproc_pll_set_rate(struct clk_hw *hw, unsigned long rate,
449 unsigned long parent_rate)
451 struct iproc_clk *clk = to_iproc_clk(hw);
452 struct iproc_pll *pll = clk->pll;
455 rate_index = pll_get_rate_index(pll, rate);
459 ret = pll_set_rate(clk, rate_index, parent_rate);
463 static const struct clk_ops iproc_pll_ops = {
464 .enable = iproc_pll_enable,
465 .disable = iproc_pll_disable,
466 .recalc_rate = iproc_pll_recalc_rate,
467 .round_rate = iproc_pll_round_rate,
468 .set_rate = iproc_pll_set_rate,
471 static int iproc_clk_enable(struct clk_hw *hw)
473 struct iproc_clk *clk = to_iproc_clk(hw);
474 const struct iproc_clk_ctrl *ctrl = clk->ctrl;
475 struct iproc_pll *pll = clk->pll;
478 /* channel enable is active low */
479 val = readl(pll->control_base + ctrl->enable.offset);
480 val &= ~(1 << ctrl->enable.enable_shift);
481 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val);
483 /* also make sure channel is not held */
484 val = readl(pll->control_base + ctrl->enable.offset);
485 val &= ~(1 << ctrl->enable.hold_shift);
486 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val);
491 static void iproc_clk_disable(struct clk_hw *hw)
493 struct iproc_clk *clk = to_iproc_clk(hw);
494 const struct iproc_clk_ctrl *ctrl = clk->ctrl;
495 struct iproc_pll *pll = clk->pll;
498 if (ctrl->flags & IPROC_CLK_AON)
501 val = readl(pll->control_base + ctrl->enable.offset);
502 val |= 1 << ctrl->enable.enable_shift;
503 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val);
506 static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
507 unsigned long parent_rate)
509 struct iproc_clk *clk = to_iproc_clk(hw);
510 const struct iproc_clk_ctrl *ctrl = clk->ctrl;
511 struct iproc_pll *pll = clk->pll;
516 if (parent_rate == 0)
519 val = readl(pll->control_base + ctrl->mdiv.offset);
520 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width);
524 if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)
525 rate = parent_rate / (mdiv * 2);
527 rate = parent_rate / mdiv;
532 static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
533 unsigned long *parent_rate)
537 if (rate == 0 || *parent_rate == 0)
540 if (rate == *parent_rate)
543 div = DIV_ROUND_UP(*parent_rate, rate);
550 return *parent_rate / div;
553 static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
554 unsigned long parent_rate)
556 struct iproc_clk *clk = to_iproc_clk(hw);
557 const struct iproc_clk_ctrl *ctrl = clk->ctrl;
558 struct iproc_pll *pll = clk->pll;
562 if (rate == 0 || parent_rate == 0)
565 if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)
566 div = DIV_ROUND_UP(parent_rate, rate * 2);
568 div = DIV_ROUND_UP(parent_rate, rate);
572 val = readl(pll->control_base + ctrl->mdiv.offset);
574 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
576 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
577 val |= div << ctrl->mdiv.shift;
579 iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val);
584 static const struct clk_ops iproc_clk_ops = {
585 .enable = iproc_clk_enable,
586 .disable = iproc_clk_disable,
587 .recalc_rate = iproc_clk_recalc_rate,
588 .round_rate = iproc_clk_round_rate,
589 .set_rate = iproc_clk_set_rate,
593 * Some PLLs require the PLL SW override bit to be set before changes can be
596 static void iproc_pll_sw_cfg(struct iproc_pll *pll)
598 const struct iproc_pll_ctrl *ctrl = pll->ctrl;
600 if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) {
603 val = readl(pll->control_base + ctrl->sw_ctrl.offset);
604 val |= BIT(ctrl->sw_ctrl.shift);
605 iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset,
610 void iproc_pll_clk_setup(struct device_node *node,
611 const struct iproc_pll_ctrl *pll_ctrl,
612 const struct iproc_pll_vco_param *vco,
613 unsigned int num_vco_entries,
614 const struct iproc_clk_ctrl *clk_ctrl,
615 unsigned int num_clks)
618 struct iproc_pll *pll;
619 struct iproc_clk *iclk;
620 struct clk_init_data init;
621 const char *parent_name;
622 struct iproc_clk *iclk_array;
623 struct clk_hw_onecell_data *clk_data;
624 const char *clk_name;
626 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl))
629 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
633 clk_data = kzalloc(sizeof(*clk_data->hws) * num_clks +
634 sizeof(*clk_data), GFP_KERNEL);
635 if (WARN_ON(!clk_data))
637 clk_data->num = num_clks;
639 iclk_array = kcalloc(num_clks, sizeof(struct iproc_clk), GFP_KERNEL);
640 if (WARN_ON(!iclk_array))
643 pll->control_base = of_iomap(node, 0);
644 if (WARN_ON(!pll->control_base))
647 /* Some SoCs do not require the pwr_base, thus failing is not fatal */
648 pll->pwr_base = of_iomap(node, 1);
650 /* some PLLs require gating control at the top ASIU level */
651 if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) {
652 pll->asiu_base = of_iomap(node, 2);
653 if (WARN_ON(!pll->asiu_base))
657 if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) {
658 /* Some SoCs have a split status/control. If this does not
659 * exist, assume they are unified.
661 pll->status_base = of_iomap(node, 2);
662 if (!pll->status_base)
663 goto err_status_iomap;
665 pll->status_base = pll->control_base;
667 /* initialize and register the PLL itself */
668 pll->ctrl = pll_ctrl;
670 iclk = &iclk_array[0];
673 ret = of_property_read_string_index(node, "clock-output-names",
676 goto err_pll_register;
678 init.name = clk_name;
679 init.ops = &iproc_pll_ops;
681 parent_name = of_clk_get_parent_name(node, 0);
682 init.parent_names = (parent_name ? &parent_name : NULL);
683 init.num_parents = (parent_name ? 1 : 0);
684 iclk->hw.init = &init;
687 pll->num_vco_entries = num_vco_entries;
688 pll->vco_param = vco;
691 iproc_pll_sw_cfg(pll);
693 ret = clk_hw_register(NULL, &iclk->hw);
695 goto err_pll_register;
697 clk_data->hws[0] = &iclk->hw;
698 parent_name = clk_name;
700 /* now initialize and register all leaf clocks */
701 for (i = 1; i < num_clks; i++) {
702 memset(&init, 0, sizeof(init));
704 ret = of_property_read_string_index(node, "clock-output-names",
707 goto err_clk_register;
709 iclk = &iclk_array[i];
711 iclk->ctrl = &clk_ctrl[i];
713 init.name = clk_name;
714 init.ops = &iproc_clk_ops;
716 init.parent_names = (parent_name ? &parent_name : NULL);
717 init.num_parents = (parent_name ? 1 : 0);
718 iclk->hw.init = &init;
720 ret = clk_hw_register(NULL, &iclk->hw);
722 goto err_clk_register;
724 clk_data->hws[i] = &iclk->hw;
727 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
729 goto err_clk_register;
735 clk_hw_unregister(clk_data->hws[i]);
738 if (pll->status_base != pll->control_base)
739 iounmap(pll->status_base);
743 iounmap(pll->asiu_base);
747 iounmap(pll->pwr_base);
749 iounmap(pll->control_base);