1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Broadcom Corporation
4 #include <linux/kernel.h>
6 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
10 #include <linux/of_address.h>
11 #include <linux/delay.h>
13 #include "clk-iproc.h"
17 struct iproc_asiu_clk {
20 struct iproc_asiu *asiu;
22 struct iproc_asiu_div div;
23 struct iproc_asiu_gate gate;
27 void __iomem *div_base;
28 void __iomem *gate_base;
30 struct clk_hw_onecell_data *clk_data;
31 struct iproc_asiu_clk *clks;
34 #define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
36 static int iproc_asiu_clk_enable(struct clk_hw *hw)
38 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
39 struct iproc_asiu *asiu = clk->asiu;
42 /* some clocks at the ASIU level are always enabled */
43 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
46 val = readl(asiu->gate_base + clk->gate.offset);
47 val |= (1 << clk->gate.en_shift);
48 writel(val, asiu->gate_base + clk->gate.offset);
53 static void iproc_asiu_clk_disable(struct clk_hw *hw)
55 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
56 struct iproc_asiu *asiu = clk->asiu;
59 /* some clocks at the ASIU level are always enabled */
60 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
63 val = readl(asiu->gate_base + clk->gate.offset);
64 val &= ~(1 << clk->gate.en_shift);
65 writel(val, asiu->gate_base + clk->gate.offset);
68 static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
69 unsigned long parent_rate)
71 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
72 struct iproc_asiu *asiu = clk->asiu;
74 unsigned int div_h, div_l;
76 if (parent_rate == 0) {
81 /* if clock divisor is not enabled, simply return parent rate */
82 val = readl(asiu->div_base + clk->div.offset);
83 if ((val & (1 << clk->div.en_shift)) == 0) {
84 clk->rate = parent_rate;
88 /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
89 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
94 clk->rate = parent_rate / (div_h + div_l);
95 pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
96 __func__, clk->rate, parent_rate, div_h, div_l);
101 static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
102 unsigned long *parent_rate)
106 if (rate == 0 || *parent_rate == 0)
109 if (rate == *parent_rate)
112 div = DIV_ROUND_CLOSEST(*parent_rate, rate);
116 return *parent_rate / div;
119 static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
120 unsigned long parent_rate)
122 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
123 struct iproc_asiu *asiu = clk->asiu;
124 unsigned int div, div_h, div_l;
127 if (rate == 0 || parent_rate == 0)
130 /* simply disable the divisor if one wants the same rate as parent */
131 if (rate == parent_rate) {
132 val = readl(asiu->div_base + clk->div.offset);
133 val &= ~(1 << clk->div.en_shift);
134 writel(val, asiu->div_base + clk->div.offset);
138 div = DIV_ROUND_CLOSEST(parent_rate, rate);
142 div_h = div_l = div >> 1;
146 val = readl(asiu->div_base + clk->div.offset);
147 val |= 1 << clk->div.en_shift;
149 val &= ~(bit_mask(clk->div.high_width)
150 << clk->div.high_shift);
151 val |= div_h << clk->div.high_shift;
153 val &= ~(bit_mask(clk->div.high_width)
154 << clk->div.high_shift);
157 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
158 val |= div_l << clk->div.low_shift;
160 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
162 writel(val, asiu->div_base + clk->div.offset);
167 static const struct clk_ops iproc_asiu_ops = {
168 .enable = iproc_asiu_clk_enable,
169 .disable = iproc_asiu_clk_disable,
170 .recalc_rate = iproc_asiu_clk_recalc_rate,
171 .round_rate = iproc_asiu_clk_round_rate,
172 .set_rate = iproc_asiu_clk_set_rate,
175 void __init iproc_asiu_setup(struct device_node *node,
176 const struct iproc_asiu_div *div,
177 const struct iproc_asiu_gate *gate,
178 unsigned int num_clks)
181 struct iproc_asiu *asiu;
183 if (WARN_ON(!gate || !div))
186 asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
190 asiu->clk_data = kzalloc(struct_size(asiu->clk_data, hws, num_clks),
192 if (WARN_ON(!asiu->clk_data))
194 asiu->clk_data->num = num_clks;
196 asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
197 if (WARN_ON(!asiu->clks))
200 asiu->div_base = of_iomap(node, 0);
201 if (WARN_ON(!asiu->div_base))
204 asiu->gate_base = of_iomap(node, 1);
205 if (WARN_ON(!asiu->gate_base))
208 for (i = 0; i < num_clks; i++) {
209 struct clk_init_data init;
210 const char *parent_name;
211 struct iproc_asiu_clk *asiu_clk;
212 const char *clk_name;
214 ret = of_property_read_string_index(node, "clock-output-names",
217 goto err_clk_register;
219 asiu_clk = &asiu->clks[i];
220 asiu_clk->name = clk_name;
221 asiu_clk->asiu = asiu;
222 asiu_clk->div = div[i];
223 asiu_clk->gate = gate[i];
224 init.name = clk_name;
225 init.ops = &iproc_asiu_ops;
227 parent_name = of_clk_get_parent_name(node, 0);
228 init.parent_names = (parent_name ? &parent_name : NULL);
229 init.num_parents = (parent_name ? 1 : 0);
230 asiu_clk->hw.init = &init;
232 ret = clk_hw_register(NULL, &asiu_clk->hw);
234 goto err_clk_register;
235 asiu->clk_data->hws[i] = &asiu_clk->hw;
238 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
241 goto err_clk_register;
247 clk_hw_unregister(asiu->clk_data->hws[i]);
248 iounmap(asiu->gate_base);
251 iounmap(asiu->div_base);
257 kfree(asiu->clk_data);