1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Broadcom Corporation
4 #include <linux/kernel.h>
5 #include <linux/slab.h>
7 #include <linux/clk-provider.h>
10 #include <linux/clkdev.h>
11 #include <linux/of_address.h>
13 #include "clk-iproc.h"
15 #define IPROC_CLK_MAX_FREQ_POLICY 0x3
16 #define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
17 #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
18 #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
20 #define IPROC_CLK_PLLARMA_OFFSET 0xc00
21 #define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
22 #define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
23 #define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
24 #define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
25 #define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
27 #define IPROC_CLK_PLLARMB_OFFSET 0xc04
28 #define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff
30 #define IPROC_CLK_PLLARMC_OFFSET 0xc08
31 #define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8
32 #define IPROC_CLK_PLLARMC_MDIV_MASK 0xff
34 #define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
35 #define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff
37 #define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
38 #define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29
39 #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
40 #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff
41 #define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff
43 #define IPROC_CLK_ARM_DIV_OFFSET 0xe00
44 #define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
45 #define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf
47 #define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
48 #define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
49 #define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7
51 enum iproc_arm_pll_fid {
52 ARM_PLL_FID_CRYSTAL_CLK = 0,
53 ARM_PLL_FID_SYS_CLK = 2,
54 ARM_PLL_FID_CH0_SLOW_CLK = 6,
55 ARM_PLL_FID_CH1_FAST_CLK = 7
58 struct iproc_arm_pll {
64 #define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)
66 static unsigned int __get_fid(struct iproc_arm_pll *pll)
69 unsigned int policy, fid, active_fid;
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
72 if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
73 policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
77 /* something is seriously wrong */
78 BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
81 fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
82 IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
85 active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
86 (val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
87 if (fid != active_fid) {
88 pr_debug("%s: fid override %u->%u\n", __func__, fid,
93 pr_debug("%s: active fid: %u\n", __func__, fid);
99 * Determine the mdiv (post divider) based on the frequency ID being used.
100 * There are 4 sources that can be used to derive the output clock rate:
103 * - PLL channel 0 (slow clock)
104 * - PLL channel 1 (fast clock)
106 static int __get_mdiv(struct iproc_arm_pll *pll)
112 fid = __get_fid(pll);
115 case ARM_PLL_FID_CRYSTAL_CLK:
116 case ARM_PLL_FID_SYS_CLK:
120 case ARM_PLL_FID_CH0_SLOW_CLK:
121 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
122 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
127 case ARM_PLL_FID_CH1_FAST_CLK:
128 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
129 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
141 static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
144 unsigned int ndiv_int, ndiv_frac, ndiv;
146 val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
147 if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
149 * offset mode is active. Read the ndiv from the PLLARM OFFSET
152 ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
153 IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
157 ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
159 /* offset mode not active */
160 val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
161 ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
162 IPROC_CLK_PLLARMA_NDIV_INT_MASK;
166 val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
167 ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
170 ndiv = (ndiv_int << 20) | ndiv_frac;
176 * The output frequency of the ARM PLL is calculated based on the ARM PLL
178 * pdiv = ARM PLL pre-divider
179 * ndiv = ARM PLL multiplier
180 * mdiv = ARM PLL post divider
182 * The frequency is calculated by:
183 * ((ndiv * parent clock rate) / pdiv) / mdiv
185 static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
186 unsigned long parent_rate)
188 struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
194 /* in bypass mode, use parent rate */
195 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
196 if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
197 pll->rate = parent_rate;
201 /* PLL needs to be locked */
202 val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
203 if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
208 pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
209 IPROC_CLK_PLLARMA_PDIV_MASK;
213 ndiv = __get_ndiv(pll);
214 mdiv = __get_mdiv(pll);
219 pll->rate = (ndiv * parent_rate) >> 20;
220 pll->rate = (pll->rate / pdiv) / mdiv;
222 pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
223 pll->rate, parent_rate);
224 pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
225 (unsigned int)(ndiv >> 20), pdiv, mdiv);
230 static const struct clk_ops iproc_arm_pll_ops = {
231 .recalc_rate = iproc_arm_pll_recalc_rate,
234 void __init iproc_armpll_setup(struct device_node *node)
237 struct iproc_arm_pll *pll;
238 struct clk_init_data init;
239 const char *parent_name;
241 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
245 pll->base = of_iomap(node, 0);
246 if (WARN_ON(!pll->base))
249 init.name = node->name;
250 init.ops = &iproc_arm_pll_ops;
252 parent_name = of_clk_get_parent_name(node, 0);
253 init.parent_names = (parent_name ? &parent_name : NULL);
254 init.num_parents = (parent_name ? 1 : 0);
255 pll->hw.init = &init;
257 ret = clk_hw_register(NULL, &pll->hw);
261 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw);
263 goto err_clk_unregister;
268 clk_hw_unregister(&pll->hw);