2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <linux/clk-provider.h>
38 #include <linux/clkdev.h>
39 #include <linux/clk.h>
40 #include <linux/debugfs.h>
41 #include <linux/delay.h>
42 #include <linux/module.h>
44 #include <linux/platform_device.h>
45 #include <linux/slab.h>
46 #include <dt-bindings/clock/bcm2835.h>
48 #define CM_PASSWORD 0x5a000000
50 #define CM_GNRICCTL 0x000
51 #define CM_GNRICDIV 0x004
52 # define CM_DIV_FRAC_BITS 12
53 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
55 #define CM_VPUCTL 0x008
56 #define CM_VPUDIV 0x00c
57 #define CM_SYSCTL 0x010
58 #define CM_SYSDIV 0x014
59 #define CM_PERIACTL 0x018
60 #define CM_PERIADIV 0x01c
61 #define CM_PERIICTL 0x020
62 #define CM_PERIIDIV 0x024
63 #define CM_H264CTL 0x028
64 #define CM_H264DIV 0x02c
65 #define CM_ISPCTL 0x030
66 #define CM_ISPDIV 0x034
67 #define CM_V3DCTL 0x038
68 #define CM_V3DDIV 0x03c
69 #define CM_CAM0CTL 0x040
70 #define CM_CAM0DIV 0x044
71 #define CM_CAM1CTL 0x048
72 #define CM_CAM1DIV 0x04c
73 #define CM_CCP2CTL 0x050
74 #define CM_CCP2DIV 0x054
75 #define CM_DSI0ECTL 0x058
76 #define CM_DSI0EDIV 0x05c
77 #define CM_DSI0PCTL 0x060
78 #define CM_DSI0PDIV 0x064
79 #define CM_DPICTL 0x068
80 #define CM_DPIDIV 0x06c
81 #define CM_GP0CTL 0x070
82 #define CM_GP0DIV 0x074
83 #define CM_GP1CTL 0x078
84 #define CM_GP1DIV 0x07c
85 #define CM_GP2CTL 0x080
86 #define CM_GP2DIV 0x084
87 #define CM_HSMCTL 0x088
88 #define CM_HSMDIV 0x08c
89 #define CM_OTPCTL 0x090
90 #define CM_OTPDIV 0x094
91 #define CM_PCMCTL 0x098
92 #define CM_PCMDIV 0x09c
93 #define CM_PWMCTL 0x0a0
94 #define CM_PWMDIV 0x0a4
95 #define CM_SLIMCTL 0x0a8
96 #define CM_SLIMDIV 0x0ac
97 #define CM_SMICTL 0x0b0
98 #define CM_SMIDIV 0x0b4
99 /* no definition for 0x0b8 and 0x0bc */
100 #define CM_TCNTCTL 0x0c0
101 # define CM_TCNT_SRC1_SHIFT 12
102 #define CM_TCNTCNT 0x0c4
103 #define CM_TECCTL 0x0c8
104 #define CM_TECDIV 0x0cc
105 #define CM_TD0CTL 0x0d0
106 #define CM_TD0DIV 0x0d4
107 #define CM_TD1CTL 0x0d8
108 #define CM_TD1DIV 0x0dc
109 #define CM_TSENSCTL 0x0e0
110 #define CM_TSENSDIV 0x0e4
111 #define CM_TIMERCTL 0x0e8
112 #define CM_TIMERDIV 0x0ec
113 #define CM_UARTCTL 0x0f0
114 #define CM_UARTDIV 0x0f4
115 #define CM_VECCTL 0x0f8
116 #define CM_VECDIV 0x0fc
117 #define CM_PULSECTL 0x190
118 #define CM_PULSEDIV 0x194
119 #define CM_SDCCTL 0x1a8
120 #define CM_SDCDIV 0x1ac
121 #define CM_ARMCTL 0x1b0
122 #define CM_AVEOCTL 0x1b8
123 #define CM_AVEODIV 0x1bc
124 #define CM_EMMCCTL 0x1c0
125 #define CM_EMMCDIV 0x1c4
127 /* General bits for the CM_*CTL regs */
128 # define CM_ENABLE BIT(4)
129 # define CM_KILL BIT(5)
130 # define CM_GATE_BIT 6
131 # define CM_GATE BIT(CM_GATE_BIT)
132 # define CM_BUSY BIT(7)
133 # define CM_BUSYD BIT(8)
134 # define CM_FRAC BIT(9)
135 # define CM_SRC_SHIFT 0
136 # define CM_SRC_BITS 4
137 # define CM_SRC_MASK 0xf
138 # define CM_SRC_GND 0
139 # define CM_SRC_OSC 1
140 # define CM_SRC_TESTDEBUG0 2
141 # define CM_SRC_TESTDEBUG1 3
142 # define CM_SRC_PLLA_CORE 4
143 # define CM_SRC_PLLA_PER 4
144 # define CM_SRC_PLLC_CORE0 5
145 # define CM_SRC_PLLC_PER 5
146 # define CM_SRC_PLLC_CORE1 8
147 # define CM_SRC_PLLD_CORE 6
148 # define CM_SRC_PLLD_PER 6
149 # define CM_SRC_PLLH_AUX 7
150 # define CM_SRC_PLLC_CORE1 8
151 # define CM_SRC_PLLC_CORE2 9
153 #define CM_OSCCOUNT 0x100
155 #define CM_PLLA 0x104
156 # define CM_PLL_ANARST BIT(8)
157 # define CM_PLLA_HOLDPER BIT(7)
158 # define CM_PLLA_LOADPER BIT(6)
159 # define CM_PLLA_HOLDCORE BIT(5)
160 # define CM_PLLA_LOADCORE BIT(4)
161 # define CM_PLLA_HOLDCCP2 BIT(3)
162 # define CM_PLLA_LOADCCP2 BIT(2)
163 # define CM_PLLA_HOLDDSI0 BIT(1)
164 # define CM_PLLA_LOADDSI0 BIT(0)
166 #define CM_PLLC 0x108
167 # define CM_PLLC_HOLDPER BIT(7)
168 # define CM_PLLC_LOADPER BIT(6)
169 # define CM_PLLC_HOLDCORE2 BIT(5)
170 # define CM_PLLC_LOADCORE2 BIT(4)
171 # define CM_PLLC_HOLDCORE1 BIT(3)
172 # define CM_PLLC_LOADCORE1 BIT(2)
173 # define CM_PLLC_HOLDCORE0 BIT(1)
174 # define CM_PLLC_LOADCORE0 BIT(0)
176 #define CM_PLLD 0x10c
177 # define CM_PLLD_HOLDPER BIT(7)
178 # define CM_PLLD_LOADPER BIT(6)
179 # define CM_PLLD_HOLDCORE BIT(5)
180 # define CM_PLLD_LOADCORE BIT(4)
181 # define CM_PLLD_HOLDDSI1 BIT(3)
182 # define CM_PLLD_LOADDSI1 BIT(2)
183 # define CM_PLLD_HOLDDSI0 BIT(1)
184 # define CM_PLLD_LOADDSI0 BIT(0)
186 #define CM_PLLH 0x110
187 # define CM_PLLH_LOADRCAL BIT(2)
188 # define CM_PLLH_LOADAUX BIT(1)
189 # define CM_PLLH_LOADPIX BIT(0)
191 #define CM_LOCK 0x114
192 # define CM_LOCK_FLOCKH BIT(12)
193 # define CM_LOCK_FLOCKD BIT(11)
194 # define CM_LOCK_FLOCKC BIT(10)
195 # define CM_LOCK_FLOCKB BIT(9)
196 # define CM_LOCK_FLOCKA BIT(8)
198 #define CM_EVENT 0x118
199 #define CM_DSI1ECTL 0x158
200 #define CM_DSI1EDIV 0x15c
201 #define CM_DSI1PCTL 0x160
202 #define CM_DSI1PDIV 0x164
203 #define CM_DFTCTL 0x168
204 #define CM_DFTDIV 0x16c
206 #define CM_PLLB 0x170
207 # define CM_PLLB_HOLDARM BIT(1)
208 # define CM_PLLB_LOADARM BIT(0)
210 #define A2W_PLLA_CTRL 0x1100
211 #define A2W_PLLC_CTRL 0x1120
212 #define A2W_PLLD_CTRL 0x1140
213 #define A2W_PLLH_CTRL 0x1160
214 #define A2W_PLLB_CTRL 0x11e0
215 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
216 # define A2W_PLL_CTRL_PWRDN BIT(16)
217 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
218 # define A2W_PLL_CTRL_PDIV_SHIFT 12
219 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
220 # define A2W_PLL_CTRL_NDIV_SHIFT 0
222 #define A2W_PLLA_ANA0 0x1010
223 #define A2W_PLLC_ANA0 0x1030
224 #define A2W_PLLD_ANA0 0x1050
225 #define A2W_PLLH_ANA0 0x1070
226 #define A2W_PLLB_ANA0 0x10f0
228 #define A2W_PLL_KA_SHIFT 7
229 #define A2W_PLL_KA_MASK GENMASK(9, 7)
230 #define A2W_PLL_KI_SHIFT 19
231 #define A2W_PLL_KI_MASK GENMASK(21, 19)
232 #define A2W_PLL_KP_SHIFT 15
233 #define A2W_PLL_KP_MASK GENMASK(18, 15)
235 #define A2W_PLLH_KA_SHIFT 19
236 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
237 #define A2W_PLLH_KI_LOW_SHIFT 22
238 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
239 #define A2W_PLLH_KI_HIGH_SHIFT 0
240 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
241 #define A2W_PLLH_KP_SHIFT 1
242 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
244 #define A2W_XOSC_CTRL 0x1190
245 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
246 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
247 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
248 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
249 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
250 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
251 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
252 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
254 #define A2W_PLLA_FRAC 0x1200
255 #define A2W_PLLC_FRAC 0x1220
256 #define A2W_PLLD_FRAC 0x1240
257 #define A2W_PLLH_FRAC 0x1260
258 #define A2W_PLLB_FRAC 0x12e0
259 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
260 # define A2W_PLL_FRAC_BITS 20
262 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
263 #define A2W_PLL_DIV_BITS 8
264 #define A2W_PLL_DIV_SHIFT 0
266 #define A2W_PLLA_DSI0 0x1300
267 #define A2W_PLLA_CORE 0x1400
268 #define A2W_PLLA_PER 0x1500
269 #define A2W_PLLA_CCP2 0x1600
271 #define A2W_PLLC_CORE2 0x1320
272 #define A2W_PLLC_CORE1 0x1420
273 #define A2W_PLLC_PER 0x1520
274 #define A2W_PLLC_CORE0 0x1620
276 #define A2W_PLLD_DSI0 0x1340
277 #define A2W_PLLD_CORE 0x1440
278 #define A2W_PLLD_PER 0x1540
279 #define A2W_PLLD_DSI1 0x1640
281 #define A2W_PLLH_AUX 0x1360
282 #define A2W_PLLH_RCAL 0x1460
283 #define A2W_PLLH_PIX 0x1560
284 #define A2W_PLLH_STS 0x1660
286 #define A2W_PLLH_CTRLR 0x1960
287 #define A2W_PLLH_FRACR 0x1a60
288 #define A2W_PLLH_AUXR 0x1b60
289 #define A2W_PLLH_RCALR 0x1c60
290 #define A2W_PLLH_PIXR 0x1d60
291 #define A2W_PLLH_STSR 0x1e60
293 #define A2W_PLLB_ARM 0x13e0
294 #define A2W_PLLB_SP0 0x14e0
295 #define A2W_PLLB_SP1 0x15e0
296 #define A2W_PLLB_SP2 0x16e0
298 #define LOCK_TIMEOUT_NS 100000000
299 #define BCM2835_MAX_FB_RATE 1750000000u
302 * Names of clocks used within the driver that need to be replaced
303 * with an external parent's name. This array is in the order that
304 * the clocks node in the DT references external clocks.
306 static const char *const cprman_parent_names[] = {
316 struct bcm2835_cprman {
319 spinlock_t regs_lock; /* spinlock for all clocks */
322 * Real names of cprman clock parents looked up through
323 * of_clk_get_parent_name(), which will be used in the
324 * parent_names[] arrays for clock registration.
326 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
329 struct clk_hw_onecell_data onecell;
332 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
334 writel(CM_PASSWORD | val, cprman->regs + reg);
337 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
339 return readl(cprman->regs + reg);
342 /* Does a cycle of measuring a clock through the TCNT clock, which may
343 * source from many other clocks in the system.
345 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
348 u32 osccount = 19200; /* 1ms */
352 spin_lock(&cprman->regs_lock);
354 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
356 cprman_write(cprman, CM_TCNTCTL,
357 (tcnt_mux & CM_SRC_MASK) |
358 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
360 cprman_write(cprman, CM_OSCCOUNT, osccount);
362 /* do a kind delay at the start */
365 /* Finish off whatever is left of OSCCOUNT */
366 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
367 while (cprman_read(cprman, CM_OSCCOUNT)) {
368 if (ktime_after(ktime_get(), timeout)) {
369 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
376 /* Wait for BUSY to clear. */
377 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
378 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
379 if (ktime_after(ktime_get(), timeout)) {
380 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
387 count = cprman_read(cprman, CM_TCNTCNT);
389 cprman_write(cprman, CM_TCNTCTL, 0);
392 spin_unlock(&cprman->regs_lock);
397 static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
398 struct debugfs_reg32 *regs, size_t nregs,
399 struct dentry *dentry)
401 struct debugfs_regset32 *regset;
403 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
408 regset->nregs = nregs;
409 regset->base = cprman->regs + base;
411 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
414 struct bcm2835_pll_data {
420 u32 reference_enable_mask;
421 /* Bit in CM_LOCK to indicate when the PLL has locked. */
424 const struct bcm2835_pll_ana_bits *ana;
426 unsigned long min_rate;
427 unsigned long max_rate;
429 * Highest rate for the VCO before we have to use the
432 unsigned long max_fb_rate;
435 struct bcm2835_pll_ana_bits {
445 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
448 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
449 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
450 .mask3 = A2W_PLL_KA_MASK,
451 .set3 = (2 << A2W_PLL_KA_SHIFT),
452 .fb_prediv_mask = BIT(14),
455 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
456 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
457 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
458 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
459 .set1 = (6 << A2W_PLLH_KP_SHIFT),
462 .fb_prediv_mask = BIT(11),
465 struct bcm2835_pll_divider_data {
467 const char *source_pll;
478 struct bcm2835_clock_data {
481 const char *const *parents;
484 /* Bitmap encoding which parents accept rate change propagation. */
485 unsigned int set_rate_parent;
490 /* Number of integer bits in the divider */
492 /* Number of fractional bits in the divider */
504 struct bcm2835_gate_data {
513 struct bcm2835_cprman *cprman;
514 const struct bcm2835_pll_data *data;
517 static int bcm2835_pll_is_on(struct clk_hw *hw)
519 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
520 struct bcm2835_cprman *cprman = pll->cprman;
521 const struct bcm2835_pll_data *data = pll->data;
523 return cprman_read(cprman, data->a2w_ctrl_reg) &
524 A2W_PLL_CTRL_PRST_DISABLE;
527 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
528 unsigned long parent_rate,
529 u32 *ndiv, u32 *fdiv)
533 div = (u64)rate << A2W_PLL_FRAC_BITS;
534 do_div(div, parent_rate);
536 *ndiv = div >> A2W_PLL_FRAC_BITS;
537 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
540 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
541 u32 ndiv, u32 fdiv, u32 pdiv)
548 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
550 return rate >> A2W_PLL_FRAC_BITS;
553 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
554 unsigned long *parent_rate)
556 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
557 const struct bcm2835_pll_data *data = pll->data;
560 rate = clamp(rate, data->min_rate, data->max_rate);
562 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
564 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
567 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
568 unsigned long parent_rate)
570 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
571 struct bcm2835_cprman *cprman = pll->cprman;
572 const struct bcm2835_pll_data *data = pll->data;
573 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
574 u32 ndiv, pdiv, fdiv;
577 if (parent_rate == 0)
580 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
581 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
582 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
583 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
584 data->ana->fb_prediv_mask;
591 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
594 static void bcm2835_pll_off(struct clk_hw *hw)
596 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
597 struct bcm2835_cprman *cprman = pll->cprman;
598 const struct bcm2835_pll_data *data = pll->data;
600 spin_lock(&cprman->regs_lock);
601 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
602 cprman_write(cprman, data->a2w_ctrl_reg,
603 cprman_read(cprman, data->a2w_ctrl_reg) |
605 spin_unlock(&cprman->regs_lock);
608 static int bcm2835_pll_on(struct clk_hw *hw)
610 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
611 struct bcm2835_cprman *cprman = pll->cprman;
612 const struct bcm2835_pll_data *data = pll->data;
615 cprman_write(cprman, data->a2w_ctrl_reg,
616 cprman_read(cprman, data->a2w_ctrl_reg) &
617 ~A2W_PLL_CTRL_PWRDN);
619 /* Take the PLL out of reset. */
620 spin_lock(&cprman->regs_lock);
621 cprman_write(cprman, data->cm_ctrl_reg,
622 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
623 spin_unlock(&cprman->regs_lock);
625 /* Wait for the PLL to lock. */
626 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
627 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
628 if (ktime_after(ktime_get(), timeout)) {
629 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
630 clk_hw_get_name(hw));
637 cprman_write(cprman, data->a2w_ctrl_reg,
638 cprman_read(cprman, data->a2w_ctrl_reg) |
639 A2W_PLL_CTRL_PRST_DISABLE);
645 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
650 * ANA register setup is done as a series of writes to
651 * ANA3-ANA0, in that order. This lets us write all 4
652 * registers as a single cycle of the serdes interface (taking
653 * 100 xosc clocks), whereas if we were to update ana0, 1, and
654 * 3 individually through their partial-write registers, each
655 * would be their own serdes cycle.
657 for (i = 3; i >= 0; i--)
658 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
661 static int bcm2835_pll_set_rate(struct clk_hw *hw,
662 unsigned long rate, unsigned long parent_rate)
664 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
665 struct bcm2835_cprman *cprman = pll->cprman;
666 const struct bcm2835_pll_data *data = pll->data;
667 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
668 u32 ndiv, fdiv, a2w_ctl;
672 if (rate > data->max_fb_rate) {
673 use_fb_prediv = true;
676 use_fb_prediv = false;
679 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
681 for (i = 3; i >= 0; i--)
682 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
684 was_using_prediv = ana[1] & data->ana->fb_prediv_mask;
686 ana[0] &= ~data->ana->mask0;
687 ana[0] |= data->ana->set0;
688 ana[1] &= ~data->ana->mask1;
689 ana[1] |= data->ana->set1;
690 ana[3] &= ~data->ana->mask3;
691 ana[3] |= data->ana->set3;
693 if (was_using_prediv && !use_fb_prediv) {
694 ana[1] &= ~data->ana->fb_prediv_mask;
695 do_ana_setup_first = true;
696 } else if (!was_using_prediv && use_fb_prediv) {
697 ana[1] |= data->ana->fb_prediv_mask;
698 do_ana_setup_first = false;
700 do_ana_setup_first = true;
703 /* Unmask the reference clock from the oscillator. */
704 spin_lock(&cprman->regs_lock);
705 cprman_write(cprman, A2W_XOSC_CTRL,
706 cprman_read(cprman, A2W_XOSC_CTRL) |
707 data->reference_enable_mask);
708 spin_unlock(&cprman->regs_lock);
710 if (do_ana_setup_first)
711 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
713 /* Set the PLL multiplier from the oscillator. */
714 cprman_write(cprman, data->frac_reg, fdiv);
716 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
717 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
718 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
719 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
720 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
721 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
723 if (!do_ana_setup_first)
724 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
729 static void bcm2835_pll_debug_init(struct clk_hw *hw,
730 struct dentry *dentry)
732 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
733 struct bcm2835_cprman *cprman = pll->cprman;
734 const struct bcm2835_pll_data *data = pll->data;
735 struct debugfs_reg32 *regs;
737 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
741 regs[0].name = "cm_ctrl";
742 regs[0].offset = data->cm_ctrl_reg;
743 regs[1].name = "a2w_ctrl";
744 regs[1].offset = data->a2w_ctrl_reg;
745 regs[2].name = "frac";
746 regs[2].offset = data->frac_reg;
747 regs[3].name = "ana0";
748 regs[3].offset = data->ana_reg_base + 0 * 4;
749 regs[4].name = "ana1";
750 regs[4].offset = data->ana_reg_base + 1 * 4;
751 regs[5].name = "ana2";
752 regs[5].offset = data->ana_reg_base + 2 * 4;
753 regs[6].name = "ana3";
754 regs[6].offset = data->ana_reg_base + 3 * 4;
756 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
759 static const struct clk_ops bcm2835_pll_clk_ops = {
760 .is_prepared = bcm2835_pll_is_on,
761 .prepare = bcm2835_pll_on,
762 .unprepare = bcm2835_pll_off,
763 .recalc_rate = bcm2835_pll_get_rate,
764 .set_rate = bcm2835_pll_set_rate,
765 .round_rate = bcm2835_pll_round_rate,
766 .debug_init = bcm2835_pll_debug_init,
769 struct bcm2835_pll_divider {
770 struct clk_divider div;
771 struct bcm2835_cprman *cprman;
772 const struct bcm2835_pll_divider_data *data;
775 static struct bcm2835_pll_divider *
776 bcm2835_pll_divider_from_hw(struct clk_hw *hw)
778 return container_of(hw, struct bcm2835_pll_divider, div.hw);
781 static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
783 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
784 struct bcm2835_cprman *cprman = divider->cprman;
785 const struct bcm2835_pll_divider_data *data = divider->data;
787 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
790 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
792 unsigned long *parent_rate)
794 return clk_divider_ops.round_rate(hw, rate, parent_rate);
797 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
798 unsigned long parent_rate)
800 return clk_divider_ops.recalc_rate(hw, parent_rate);
803 static void bcm2835_pll_divider_off(struct clk_hw *hw)
805 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
806 struct bcm2835_cprman *cprman = divider->cprman;
807 const struct bcm2835_pll_divider_data *data = divider->data;
809 spin_lock(&cprman->regs_lock);
810 cprman_write(cprman, data->cm_reg,
811 (cprman_read(cprman, data->cm_reg) &
812 ~data->load_mask) | data->hold_mask);
813 cprman_write(cprman, data->a2w_reg,
814 cprman_read(cprman, data->a2w_reg) |
815 A2W_PLL_CHANNEL_DISABLE);
816 spin_unlock(&cprman->regs_lock);
819 static int bcm2835_pll_divider_on(struct clk_hw *hw)
821 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
822 struct bcm2835_cprman *cprman = divider->cprman;
823 const struct bcm2835_pll_divider_data *data = divider->data;
825 spin_lock(&cprman->regs_lock);
826 cprman_write(cprman, data->a2w_reg,
827 cprman_read(cprman, data->a2w_reg) &
828 ~A2W_PLL_CHANNEL_DISABLE);
830 cprman_write(cprman, data->cm_reg,
831 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
832 spin_unlock(&cprman->regs_lock);
837 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
839 unsigned long parent_rate)
841 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
842 struct bcm2835_cprman *cprman = divider->cprman;
843 const struct bcm2835_pll_divider_data *data = divider->data;
844 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
846 div = DIV_ROUND_UP_ULL(parent_rate, rate);
848 div = min(div, max_div);
852 cprman_write(cprman, data->a2w_reg, div);
853 cm = cprman_read(cprman, data->cm_reg);
854 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
855 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
860 static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
861 struct dentry *dentry)
863 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
864 struct bcm2835_cprman *cprman = divider->cprman;
865 const struct bcm2835_pll_divider_data *data = divider->data;
866 struct debugfs_reg32 *regs;
868 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
873 regs[0].offset = data->cm_reg;
874 regs[1].name = "a2w";
875 regs[1].offset = data->a2w_reg;
877 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
880 static const struct clk_ops bcm2835_pll_divider_clk_ops = {
881 .is_prepared = bcm2835_pll_divider_is_on,
882 .prepare = bcm2835_pll_divider_on,
883 .unprepare = bcm2835_pll_divider_off,
884 .recalc_rate = bcm2835_pll_divider_get_rate,
885 .set_rate = bcm2835_pll_divider_set_rate,
886 .round_rate = bcm2835_pll_divider_round_rate,
887 .debug_init = bcm2835_pll_divider_debug_init,
891 * The CM dividers do fixed-point division, so we can't use the
892 * generic integer divider code like the PLL dividers do (and we can't
893 * fake it by having some fixed shifts preceding it in the clock tree,
894 * because we'd run out of bits in a 32-bit unsigned long).
896 struct bcm2835_clock {
898 struct bcm2835_cprman *cprman;
899 const struct bcm2835_clock_data *data;
902 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
904 return container_of(hw, struct bcm2835_clock, hw);
907 static int bcm2835_clock_is_on(struct clk_hw *hw)
909 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
910 struct bcm2835_cprman *cprman = clock->cprman;
911 const struct bcm2835_clock_data *data = clock->data;
913 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
916 static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
918 unsigned long parent_rate)
920 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
921 const struct bcm2835_clock_data *data = clock->data;
922 u32 unused_frac_mask =
923 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
924 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
926 u32 div, mindiv, maxdiv;
928 rem = do_div(temp, rate);
930 div &= ~unused_frac_mask;
932 /* different clamping limits apply for a mash clock */
933 if (data->is_mash_clock) {
934 /* clamp to min divider of 2 */
935 mindiv = 2 << CM_DIV_FRAC_BITS;
936 /* clamp to the highest possible integer divider */
937 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
939 /* clamp to min divider of 1 */
940 mindiv = 1 << CM_DIV_FRAC_BITS;
941 /* clamp to the highest possible fractional divider */
942 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
943 CM_DIV_FRAC_BITS - data->frac_bits);
946 /* apply the clamping limits */
947 div = max_t(u32, div, mindiv);
948 div = min_t(u32, div, maxdiv);
953 static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
954 unsigned long parent_rate,
957 const struct bcm2835_clock_data *data = clock->data;
960 if (data->int_bits == 0 && data->frac_bits == 0)
964 * The divisor is a 12.12 fixed point field, but only some of
965 * the bits are populated in any given clock.
967 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
968 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
973 temp = (u64)parent_rate << data->frac_bits;
980 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
981 unsigned long parent_rate)
983 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
984 struct bcm2835_cprman *cprman = clock->cprman;
985 const struct bcm2835_clock_data *data = clock->data;
988 if (data->int_bits == 0 && data->frac_bits == 0)
991 div = cprman_read(cprman, data->div_reg);
993 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
996 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
998 struct bcm2835_cprman *cprman = clock->cprman;
999 const struct bcm2835_clock_data *data = clock->data;
1000 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1002 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1003 if (ktime_after(ktime_get(), timeout)) {
1004 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1005 clk_hw_get_name(&clock->hw));
1012 static void bcm2835_clock_off(struct clk_hw *hw)
1014 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1015 struct bcm2835_cprman *cprman = clock->cprman;
1016 const struct bcm2835_clock_data *data = clock->data;
1018 spin_lock(&cprman->regs_lock);
1019 cprman_write(cprman, data->ctl_reg,
1020 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1021 spin_unlock(&cprman->regs_lock);
1023 /* BUSY will remain high until the divider completes its cycle. */
1024 bcm2835_clock_wait_busy(clock);
1027 static int bcm2835_clock_on(struct clk_hw *hw)
1029 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1030 struct bcm2835_cprman *cprman = clock->cprman;
1031 const struct bcm2835_clock_data *data = clock->data;
1033 spin_lock(&cprman->regs_lock);
1034 cprman_write(cprman, data->ctl_reg,
1035 cprman_read(cprman, data->ctl_reg) |
1038 spin_unlock(&cprman->regs_lock);
1040 /* Debug code to measure the clock once it's turned on to see
1041 * if it's ticking at the rate we expect.
1043 if (data->tcnt_mux && false) {
1044 dev_info(cprman->dev,
1045 "clk %s: rate %ld, measure %ld\n",
1047 clk_hw_get_rate(hw),
1048 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1054 static int bcm2835_clock_set_rate(struct clk_hw *hw,
1055 unsigned long rate, unsigned long parent_rate)
1057 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1058 struct bcm2835_cprman *cprman = clock->cprman;
1059 const struct bcm2835_clock_data *data = clock->data;
1060 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
1063 spin_lock(&cprman->regs_lock);
1066 * Setting up frac support
1068 * In principle it is recommended to stop/start the clock first,
1069 * but as we set CLK_SET_RATE_GATE during registration of the
1070 * clock this requirement should be take care of by the
1073 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1074 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1075 cprman_write(cprman, data->ctl_reg, ctl);
1077 cprman_write(cprman, data->div_reg, div);
1079 spin_unlock(&cprman->regs_lock);
1085 bcm2835_clk_is_pllc(struct clk_hw *hw)
1090 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1093 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1097 unsigned long *prate,
1098 unsigned long *avgrate)
1100 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1101 struct bcm2835_cprman *cprman = clock->cprman;
1102 const struct bcm2835_clock_data *data = clock->data;
1103 unsigned long best_rate = 0;
1104 u32 curdiv, mindiv, maxdiv;
1105 struct clk_hw *parent;
1107 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1109 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1110 *prate = clk_hw_get_rate(parent);
1111 *div = bcm2835_clock_choose_div(hw, rate, *prate);
1113 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1115 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1116 unsigned long high, low;
1117 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1119 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1121 int_div += CM_DIV_FRAC_MASK + 1;
1122 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1126 * Return a value which is the maximum deviation
1127 * below the ideal rate, for use as a metric.
1129 return *avgrate - max(*avgrate - low, high - *avgrate);
1134 if (data->frac_bits)
1135 dev_warn(cprman->dev,
1136 "frac bits are not used when propagating rate change");
1138 /* clamp to min divider of 2 if we're dealing with a mash clock */
1139 mindiv = data->is_mash_clock ? 2 : 1;
1140 maxdiv = BIT(data->int_bits) - 1;
1142 /* TODO: Be smart, and only test a subset of the available divisors. */
1143 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1144 unsigned long tmp_rate;
1146 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1148 if (curdiv == mindiv ||
1149 (tmp_rate > best_rate && tmp_rate <= rate))
1150 best_rate = tmp_rate;
1152 if (best_rate == rate)
1156 *div = curdiv << CM_DIV_FRAC_BITS;
1157 *prate = curdiv * best_rate;
1158 *avgrate = best_rate;
1163 static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1164 struct clk_rate_request *req)
1166 struct clk_hw *parent, *best_parent = NULL;
1167 bool current_parent_is_pllc;
1168 unsigned long rate, best_rate = 0;
1169 unsigned long prate, best_prate = 0;
1170 unsigned long avgrate, best_avgrate = 0;
1174 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1177 * Select parent clock that results in the closest but lower rate
1179 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1180 parent = clk_hw_get_parent_by_index(hw, i);
1185 * Don't choose a PLLC-derived clock as our parent
1186 * unless it had been manually set that way. PLLC's
1187 * frequency gets adjusted by the firmware due to
1188 * over-temp or under-voltage conditions, without
1189 * prior notification to our clock consumer.
1191 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1194 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1197 if (abs(req->rate - rate) < abs(req->rate - best_rate)) {
1198 best_parent = parent;
1201 best_avgrate = avgrate;
1208 req->best_parent_hw = best_parent;
1209 req->best_parent_rate = best_prate;
1211 req->rate = best_avgrate;
1216 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1218 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1219 struct bcm2835_cprman *cprman = clock->cprman;
1220 const struct bcm2835_clock_data *data = clock->data;
1221 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1223 cprman_write(cprman, data->ctl_reg, src);
1227 static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1229 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1230 struct bcm2835_cprman *cprman = clock->cprman;
1231 const struct bcm2835_clock_data *data = clock->data;
1232 u32 src = cprman_read(cprman, data->ctl_reg);
1234 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1237 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1248 static void bcm2835_clock_debug_init(struct clk_hw *hw,
1249 struct dentry *dentry)
1251 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1252 struct bcm2835_cprman *cprman = clock->cprman;
1253 const struct bcm2835_clock_data *data = clock->data;
1255 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1256 bcm2835_debugfs_clock_reg32,
1257 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1261 static const struct clk_ops bcm2835_clock_clk_ops = {
1262 .is_prepared = bcm2835_clock_is_on,
1263 .prepare = bcm2835_clock_on,
1264 .unprepare = bcm2835_clock_off,
1265 .recalc_rate = bcm2835_clock_get_rate,
1266 .set_rate = bcm2835_clock_set_rate,
1267 .determine_rate = bcm2835_clock_determine_rate,
1268 .set_parent = bcm2835_clock_set_parent,
1269 .get_parent = bcm2835_clock_get_parent,
1270 .debug_init = bcm2835_clock_debug_init,
1273 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1279 * The VPU clock can never be disabled (it doesn't have an ENABLE
1280 * bit), so it gets its own set of clock ops.
1282 static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1283 .is_prepared = bcm2835_vpu_clock_is_on,
1284 .recalc_rate = bcm2835_clock_get_rate,
1285 .set_rate = bcm2835_clock_set_rate,
1286 .determine_rate = bcm2835_clock_determine_rate,
1287 .set_parent = bcm2835_clock_set_parent,
1288 .get_parent = bcm2835_clock_get_parent,
1289 .debug_init = bcm2835_clock_debug_init,
1292 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1293 const struct bcm2835_pll_data *data)
1295 struct bcm2835_pll *pll;
1296 struct clk_init_data init;
1299 memset(&init, 0, sizeof(init));
1301 /* All of the PLLs derive from the external oscillator. */
1302 init.parent_names = &cprman->real_parent_names[0];
1303 init.num_parents = 1;
1304 init.name = data->name;
1305 init.ops = &bcm2835_pll_clk_ops;
1306 init.flags = CLK_IGNORE_UNUSED;
1308 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1312 pll->cprman = cprman;
1314 pll->hw.init = &init;
1316 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1324 static struct clk_hw *
1325 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1326 const struct bcm2835_pll_divider_data *data)
1328 struct bcm2835_pll_divider *divider;
1329 struct clk_init_data init;
1330 const char *divider_name;
1333 if (data->fixed_divider != 1) {
1334 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1335 "%s_prediv", data->name);
1339 divider_name = data->name;
1342 memset(&init, 0, sizeof(init));
1344 init.parent_names = &data->source_pll;
1345 init.num_parents = 1;
1346 init.name = divider_name;
1347 init.ops = &bcm2835_pll_divider_clk_ops;
1348 init.flags = data->flags | CLK_IGNORE_UNUSED;
1350 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1354 divider->div.reg = cprman->regs + data->a2w_reg;
1355 divider->div.shift = A2W_PLL_DIV_SHIFT;
1356 divider->div.width = A2W_PLL_DIV_BITS;
1357 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1358 divider->div.lock = &cprman->regs_lock;
1359 divider->div.hw.init = &init;
1360 divider->div.table = NULL;
1362 divider->cprman = cprman;
1363 divider->data = data;
1365 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
1367 return ERR_PTR(ret);
1370 * PLLH's channels have a fixed divide by 10 afterwards, which
1371 * is what our consumers are actually using.
1373 if (data->fixed_divider != 1) {
1374 return clk_hw_register_fixed_factor(cprman->dev, data->name,
1376 CLK_SET_RATE_PARENT,
1378 data->fixed_divider);
1381 return ÷r->div.hw;
1384 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1385 const struct bcm2835_clock_data *data)
1387 struct bcm2835_clock *clock;
1388 struct clk_init_data init;
1389 const char *parents[1 << CM_SRC_BITS];
1394 * Replace our strings referencing parent clocks with the
1395 * actual clock-output-name of the parent.
1397 for (i = 0; i < data->num_mux_parents; i++) {
1398 parents[i] = data->parents[i];
1400 ret = match_string(cprman_parent_names,
1401 ARRAY_SIZE(cprman_parent_names),
1404 parents[i] = cprman->real_parent_names[ret];
1407 memset(&init, 0, sizeof(init));
1408 init.parent_names = parents;
1409 init.num_parents = data->num_mux_parents;
1410 init.name = data->name;
1411 init.flags = data->flags | CLK_IGNORE_UNUSED;
1414 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1415 * rate changes on at least of the parents.
1417 if (data->set_rate_parent)
1418 init.flags |= CLK_SET_RATE_PARENT;
1420 if (data->is_vpu_clock) {
1421 init.ops = &bcm2835_vpu_clock_clk_ops;
1423 init.ops = &bcm2835_clock_clk_ops;
1424 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1426 /* If the clock wasn't actually enabled at boot, it's not
1429 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))
1430 init.flags &= ~CLK_IS_CRITICAL;
1433 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1437 clock->cprman = cprman;
1439 clock->hw.init = &init;
1441 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1443 return ERR_PTR(ret);
1447 static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1448 const struct bcm2835_gate_data *data)
1450 return clk_hw_register_gate(cprman->dev, data->name, data->parent,
1451 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1452 cprman->regs + data->ctl_reg,
1453 CM_GATE_BIT, 0, &cprman->regs_lock);
1456 typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1458 struct bcm2835_clk_desc {
1459 bcm2835_clk_register clk_register;
1463 /* assignment helper macros for different clock types */
1464 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1465 .data = __VA_ARGS__ }
1466 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1467 &(struct bcm2835_pll_data) \
1469 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1470 &(struct bcm2835_pll_divider_data) \
1472 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1473 &(struct bcm2835_clock_data) \
1475 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1476 &(struct bcm2835_gate_data) \
1479 /* parent mux arrays plus helper macros */
1481 /* main oscillator parent mux */
1482 static const char *const bcm2835_clock_osc_parents[] = {
1489 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1490 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1491 .parents = bcm2835_clock_osc_parents, \
1494 /* main peripherial parent mux */
1495 static const char *const bcm2835_clock_per_parents[] = {
1506 #define REGISTER_PER_CLK(...) REGISTER_CLK( \
1507 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1508 .parents = bcm2835_clock_per_parents, \
1512 * Restrict clock sources for the PCM peripheral to the oscillator and
1513 * PLLD_PER because other source may have varying rates or be switched
1516 * Prevent other sources from being selected by replacing their names in
1517 * the list of potential parents with dummy entries (entry index is
1520 static const char *const bcm2835_pcm_per_parents[] = {
1531 #define REGISTER_PCM_CLK(...) REGISTER_CLK( \
1532 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1533 .parents = bcm2835_pcm_per_parents, \
1536 /* main vpu parent mux */
1537 static const char *const bcm2835_clock_vpu_parents[] = {
1550 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1551 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1552 .parents = bcm2835_clock_vpu_parents, \
1556 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
1557 * analog PHY. The _inv variants are generated internally to cprman,
1558 * but we don't use them so they aren't hooked up.
1560 static const char *const bcm2835_clock_dsi0_parents[] = {
1573 static const char *const bcm2835_clock_dsi1_parents[] = {
1586 #define REGISTER_DSI0_CLK(...) REGISTER_CLK( \
1587 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1588 .parents = bcm2835_clock_dsi0_parents, \
1591 #define REGISTER_DSI1_CLK(...) REGISTER_CLK( \
1592 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1593 .parents = bcm2835_clock_dsi1_parents, \
1597 * the real definition of all the pll, pll_dividers and clocks
1598 * these make use of the above REGISTER_* macros
1600 static const struct bcm2835_clk_desc clk_desc_array[] = {
1601 /* the PLL + PLL dividers */
1604 * PLLA is the auxiliary PLL, used to drive the CCP2
1605 * (Compact Camera Port 2) transmitter clock.
1607 * It is in the PX LDO power domain, which is on when the
1608 * AUDIO domain is on.
1610 [BCM2835_PLLA] = REGISTER_PLL(
1612 .cm_ctrl_reg = CM_PLLA,
1613 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1614 .frac_reg = A2W_PLLA_FRAC,
1615 .ana_reg_base = A2W_PLLA_ANA0,
1616 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1617 .lock_mask = CM_LOCK_FLOCKA,
1619 .ana = &bcm2835_ana_default,
1621 .min_rate = 600000000u,
1622 .max_rate = 2400000000u,
1623 .max_fb_rate = BCM2835_MAX_FB_RATE),
1624 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1625 .name = "plla_core",
1626 .source_pll = "plla",
1628 .a2w_reg = A2W_PLLA_CORE,
1629 .load_mask = CM_PLLA_LOADCORE,
1630 .hold_mask = CM_PLLA_HOLDCORE,
1632 .flags = CLK_SET_RATE_PARENT),
1633 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1635 .source_pll = "plla",
1637 .a2w_reg = A2W_PLLA_PER,
1638 .load_mask = CM_PLLA_LOADPER,
1639 .hold_mask = CM_PLLA_HOLDPER,
1641 .flags = CLK_SET_RATE_PARENT),
1642 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1643 .name = "plla_dsi0",
1644 .source_pll = "plla",
1646 .a2w_reg = A2W_PLLA_DSI0,
1647 .load_mask = CM_PLLA_LOADDSI0,
1648 .hold_mask = CM_PLLA_HOLDDSI0,
1649 .fixed_divider = 1),
1650 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1651 .name = "plla_ccp2",
1652 .source_pll = "plla",
1654 .a2w_reg = A2W_PLLA_CCP2,
1655 .load_mask = CM_PLLA_LOADCCP2,
1656 .hold_mask = CM_PLLA_HOLDCCP2,
1658 .flags = CLK_SET_RATE_PARENT),
1660 /* PLLB is used for the ARM's clock. */
1661 [BCM2835_PLLB] = REGISTER_PLL(
1663 .cm_ctrl_reg = CM_PLLB,
1664 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1665 .frac_reg = A2W_PLLB_FRAC,
1666 .ana_reg_base = A2W_PLLB_ANA0,
1667 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1668 .lock_mask = CM_LOCK_FLOCKB,
1670 .ana = &bcm2835_ana_default,
1672 .min_rate = 600000000u,
1673 .max_rate = 3000000000u,
1674 .max_fb_rate = BCM2835_MAX_FB_RATE),
1675 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1677 .source_pll = "pllb",
1679 .a2w_reg = A2W_PLLB_ARM,
1680 .load_mask = CM_PLLB_LOADARM,
1681 .hold_mask = CM_PLLB_HOLDARM,
1683 .flags = CLK_SET_RATE_PARENT),
1686 * PLLC is the core PLL, used to drive the core VPU clock.
1688 * It is in the PX LDO power domain, which is on when the
1689 * AUDIO domain is on.
1691 [BCM2835_PLLC] = REGISTER_PLL(
1693 .cm_ctrl_reg = CM_PLLC,
1694 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1695 .frac_reg = A2W_PLLC_FRAC,
1696 .ana_reg_base = A2W_PLLC_ANA0,
1697 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1698 .lock_mask = CM_LOCK_FLOCKC,
1700 .ana = &bcm2835_ana_default,
1702 .min_rate = 600000000u,
1703 .max_rate = 3000000000u,
1704 .max_fb_rate = BCM2835_MAX_FB_RATE),
1705 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1706 .name = "pllc_core0",
1707 .source_pll = "pllc",
1709 .a2w_reg = A2W_PLLC_CORE0,
1710 .load_mask = CM_PLLC_LOADCORE0,
1711 .hold_mask = CM_PLLC_HOLDCORE0,
1713 .flags = CLK_SET_RATE_PARENT),
1714 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1715 .name = "pllc_core1",
1716 .source_pll = "pllc",
1718 .a2w_reg = A2W_PLLC_CORE1,
1719 .load_mask = CM_PLLC_LOADCORE1,
1720 .hold_mask = CM_PLLC_HOLDCORE1,
1722 .flags = CLK_SET_RATE_PARENT),
1723 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1724 .name = "pllc_core2",
1725 .source_pll = "pllc",
1727 .a2w_reg = A2W_PLLC_CORE2,
1728 .load_mask = CM_PLLC_LOADCORE2,
1729 .hold_mask = CM_PLLC_HOLDCORE2,
1731 .flags = CLK_SET_RATE_PARENT),
1732 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1734 .source_pll = "pllc",
1736 .a2w_reg = A2W_PLLC_PER,
1737 .load_mask = CM_PLLC_LOADPER,
1738 .hold_mask = CM_PLLC_HOLDPER,
1740 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1743 * PLLD is the display PLL, used to drive DSI display panels.
1745 * It is in the PX LDO power domain, which is on when the
1746 * AUDIO domain is on.
1748 [BCM2835_PLLD] = REGISTER_PLL(
1750 .cm_ctrl_reg = CM_PLLD,
1751 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1752 .frac_reg = A2W_PLLD_FRAC,
1753 .ana_reg_base = A2W_PLLD_ANA0,
1754 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1755 .lock_mask = CM_LOCK_FLOCKD,
1757 .ana = &bcm2835_ana_default,
1759 .min_rate = 600000000u,
1760 .max_rate = 2400000000u,
1761 .max_fb_rate = BCM2835_MAX_FB_RATE),
1762 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1763 .name = "plld_core",
1764 .source_pll = "plld",
1766 .a2w_reg = A2W_PLLD_CORE,
1767 .load_mask = CM_PLLD_LOADCORE,
1768 .hold_mask = CM_PLLD_HOLDCORE,
1770 .flags = CLK_SET_RATE_PARENT),
1771 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1773 .source_pll = "plld",
1775 .a2w_reg = A2W_PLLD_PER,
1776 .load_mask = CM_PLLD_LOADPER,
1777 .hold_mask = CM_PLLD_HOLDPER,
1779 .flags = CLK_SET_RATE_PARENT),
1780 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1781 .name = "plld_dsi0",
1782 .source_pll = "plld",
1784 .a2w_reg = A2W_PLLD_DSI0,
1785 .load_mask = CM_PLLD_LOADDSI0,
1786 .hold_mask = CM_PLLD_HOLDDSI0,
1787 .fixed_divider = 1),
1788 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1789 .name = "plld_dsi1",
1790 .source_pll = "plld",
1792 .a2w_reg = A2W_PLLD_DSI1,
1793 .load_mask = CM_PLLD_LOADDSI1,
1794 .hold_mask = CM_PLLD_HOLDDSI1,
1795 .fixed_divider = 1),
1798 * PLLH is used to supply the pixel clock or the AUX clock for the
1801 * It is in the HDMI power domain.
1803 [BCM2835_PLLH] = REGISTER_PLL(
1805 .cm_ctrl_reg = CM_PLLH,
1806 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1807 .frac_reg = A2W_PLLH_FRAC,
1808 .ana_reg_base = A2W_PLLH_ANA0,
1809 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1810 .lock_mask = CM_LOCK_FLOCKH,
1812 .ana = &bcm2835_ana_pllh,
1814 .min_rate = 600000000u,
1815 .max_rate = 3000000000u,
1816 .max_fb_rate = BCM2835_MAX_FB_RATE),
1817 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1818 .name = "pllh_rcal",
1819 .source_pll = "pllh",
1821 .a2w_reg = A2W_PLLH_RCAL,
1822 .load_mask = CM_PLLH_LOADRCAL,
1824 .fixed_divider = 10,
1825 .flags = CLK_SET_RATE_PARENT),
1826 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1828 .source_pll = "pllh",
1830 .a2w_reg = A2W_PLLH_AUX,
1831 .load_mask = CM_PLLH_LOADAUX,
1834 .flags = CLK_SET_RATE_PARENT),
1835 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1837 .source_pll = "pllh",
1839 .a2w_reg = A2W_PLLH_PIX,
1840 .load_mask = CM_PLLH_LOADPIX,
1842 .fixed_divider = 10,
1843 .flags = CLK_SET_RATE_PARENT),
1847 /* clocks with oscillator parent mux */
1849 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1850 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1852 .ctl_reg = CM_OTPCTL,
1853 .div_reg = CM_OTPDIV,
1858 * Used for a 1Mhz clock for the system clocksource, and also used
1859 * bythe watchdog timer and the camera pulse generator.
1861 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1863 .ctl_reg = CM_TIMERCTL,
1864 .div_reg = CM_TIMERDIV,
1868 * Clock for the temperature sensor.
1869 * Generally run at 2Mhz, max 5Mhz.
1871 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1873 .ctl_reg = CM_TSENSCTL,
1874 .div_reg = CM_TSENSDIV,
1877 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1879 .ctl_reg = CM_TECCTL,
1880 .div_reg = CM_TECDIV,
1884 /* clocks with vpu parent mux */
1885 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1887 .ctl_reg = CM_H264CTL,
1888 .div_reg = CM_H264DIV,
1892 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1894 .ctl_reg = CM_ISPCTL,
1895 .div_reg = CM_ISPDIV,
1901 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1902 * in the SDRAM controller can't be used.
1904 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1906 .ctl_reg = CM_SDCCTL,
1907 .div_reg = CM_SDCDIV,
1911 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1913 .ctl_reg = CM_V3DCTL,
1914 .div_reg = CM_V3DDIV,
1919 * VPU clock. This doesn't have an enable bit, since it drives
1920 * the bus for everything else, and is special so it doesn't need
1921 * to be gated for rate changes. It is also known as "clk_audio"
1922 * in various hardware documentation.
1924 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
1926 .ctl_reg = CM_VPUCTL,
1927 .div_reg = CM_VPUDIV,
1930 .flags = CLK_IS_CRITICAL,
1931 .is_vpu_clock = true,
1934 /* clocks with per parent mux */
1935 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
1937 .ctl_reg = CM_AVEOCTL,
1938 .div_reg = CM_AVEODIV,
1942 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
1944 .ctl_reg = CM_CAM0CTL,
1945 .div_reg = CM_CAM0DIV,
1949 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
1951 .ctl_reg = CM_CAM1CTL,
1952 .div_reg = CM_CAM1DIV,
1956 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
1958 .ctl_reg = CM_DFTCTL,
1959 .div_reg = CM_DFTDIV,
1962 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
1964 .ctl_reg = CM_DPICTL,
1965 .div_reg = CM_DPIDIV,
1970 /* Arasan EMMC clock */
1971 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
1973 .ctl_reg = CM_EMMCCTL,
1974 .div_reg = CM_EMMCDIV,
1979 /* General purpose (GPIO) clocks */
1980 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
1982 .ctl_reg = CM_GP0CTL,
1983 .div_reg = CM_GP0DIV,
1986 .is_mash_clock = true,
1988 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
1990 .ctl_reg = CM_GP1CTL,
1991 .div_reg = CM_GP1DIV,
1994 .flags = CLK_IS_CRITICAL,
1995 .is_mash_clock = true,
1997 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
1999 .ctl_reg = CM_GP2CTL,
2000 .div_reg = CM_GP2DIV,
2003 .flags = CLK_IS_CRITICAL),
2005 /* HDMI state machine */
2006 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2008 .ctl_reg = CM_HSMCTL,
2009 .div_reg = CM_HSMDIV,
2013 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2015 .ctl_reg = CM_PCMCTL,
2016 .div_reg = CM_PCMDIV,
2019 .is_mash_clock = true,
2022 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2024 .ctl_reg = CM_PWMCTL,
2025 .div_reg = CM_PWMDIV,
2028 .is_mash_clock = true,
2030 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2032 .ctl_reg = CM_SLIMCTL,
2033 .div_reg = CM_SLIMDIV,
2036 .is_mash_clock = true,
2038 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2040 .ctl_reg = CM_SMICTL,
2041 .div_reg = CM_SMIDIV,
2045 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2047 .ctl_reg = CM_UARTCTL,
2048 .div_reg = CM_UARTDIV,
2053 /* TV encoder clock. Only operating frequency is 108Mhz. */
2054 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2056 .ctl_reg = CM_VECCTL,
2057 .div_reg = CM_VECDIV,
2061 * Allow rate change propagation only on PLLH_AUX which is
2062 * assigned index 7 in the parent array.
2064 .set_rate_parent = BIT(7),
2068 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2070 .ctl_reg = CM_DSI0ECTL,
2071 .div_reg = CM_DSI0EDIV,
2075 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2077 .ctl_reg = CM_DSI1ECTL,
2078 .div_reg = CM_DSI1EDIV,
2082 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2084 .ctl_reg = CM_DSI0PCTL,
2085 .div_reg = CM_DSI0PDIV,
2089 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2091 .ctl_reg = CM_DSI1PCTL,
2092 .div_reg = CM_DSI1PDIV,
2100 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2101 * you have the debug bit set in the power manager, which we
2102 * don't bother exposing) are individual gates off of the
2103 * non-stop vpu clock.
2105 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2106 .name = "peri_image",
2108 .ctl_reg = CM_PERIICTL),
2112 * Permanently take a reference on the parent of the SDRAM clock.
2114 * While the SDRAM is being driven by its dedicated PLL most of the
2115 * time, there is a little loop running in the firmware that
2116 * periodically switches the SDRAM to using our CM clock to do PVT
2117 * recalibration, with the assumption that the previously configured
2118 * SDRAM parent is still enabled and running.
2120 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2122 struct clk *parent = clk_get_parent(sdc);
2125 return PTR_ERR(parent);
2127 return clk_prepare_enable(parent);
2130 static int bcm2835_clk_probe(struct platform_device *pdev)
2132 struct device *dev = &pdev->dev;
2133 struct clk_hw **hws;
2134 struct bcm2835_cprman *cprman;
2135 struct resource *res;
2136 const struct bcm2835_clk_desc *desc;
2137 const size_t asize = ARRAY_SIZE(clk_desc_array);
2141 cprman = devm_kzalloc(dev,
2142 struct_size(cprman, onecell.hws, asize),
2147 spin_lock_init(&cprman->regs_lock);
2149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2150 cprman->regs = devm_ioremap_resource(dev, res);
2151 if (IS_ERR(cprman->regs))
2152 return PTR_ERR(cprman->regs);
2154 memcpy(cprman->real_parent_names, cprman_parent_names,
2155 sizeof(cprman_parent_names));
2156 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2157 ARRAY_SIZE(cprman_parent_names));
2160 * Make sure the external oscillator has been registered.
2162 * The other (DSI) clocks are not present on older device
2163 * trees, which we still need to support for backwards
2166 if (!cprman->real_parent_names[0])
2169 platform_set_drvdata(pdev, cprman);
2171 cprman->onecell.num = asize;
2172 hws = cprman->onecell.hws;
2174 for (i = 0; i < asize; i++) {
2175 desc = &clk_desc_array[i];
2176 if (desc->clk_register && desc->data)
2177 hws[i] = desc->clk_register(cprman, desc->data);
2180 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2184 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2188 static const struct of_device_id bcm2835_clk_of_match[] = {
2189 { .compatible = "brcm,bcm2835-cprman", },
2192 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2194 static struct platform_driver bcm2835_clk_driver = {
2196 .name = "bcm2835-clk",
2197 .of_match_table = bcm2835_clk_of_match,
2199 .probe = bcm2835_clk_probe,
2202 builtin_platform_driver(bcm2835_clk_driver);
2204 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2205 MODULE_DESCRIPTION("BCM2835 clock driver");
2206 MODULE_LICENSE("GPL v2");