drivers/clk/baikal-t1/clk-ccu-div.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
   4  *
   5  * Authors:
   6  *   Serge Semin <Sergey.Semin@baikalelectronics.ru>
   7  *   Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
   8  *
   9  * Baikal-T1 CCU Dividers clock driver
  10  */
  11
  12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
  13
  14 #include <linux/kernel.h>
  15 #include <linux/printk.h>
  16 #include <linux/slab.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/reset-controller.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/ioport.h>
  24 #include <linux/regmap.h>
  25
  26 #include <dt-bindings/clock/bt1-ccu.h>
  27 #include <dt-bindings/reset/bt1-ccu.h>
  28
  29 #include "ccu-div.h"
  30
  31 #define CCU_AXI_MAIN_BASE               0x030
  32 #define CCU_AXI_DDR_BASE                0x034
  33 #define CCU_AXI_SATA_BASE               0x038
  34 #define CCU_AXI_GMAC0_BASE              0x03C
  35 #define CCU_AXI_GMAC1_BASE              0x040
  36 #define CCU_AXI_XGMAC_BASE              0x044
  37 #define CCU_AXI_PCIE_M_BASE             0x048
  38 #define CCU_AXI_PCIE_S_BASE             0x04C
  39 #define CCU_AXI_USB_BASE                0x050
  40 #define CCU_AXI_HWA_BASE                0x054
  41 #define CCU_AXI_SRAM_BASE               0x058
  42
  43 #define CCU_SYS_SATA_REF_BASE           0x060
  44 #define CCU_SYS_APB_BASE                0x064
  45 #define CCU_SYS_GMAC0_BASE              0x068
  46 #define CCU_SYS_GMAC1_BASE              0x06C
  47 #define CCU_SYS_XGMAC_BASE              0x070
  48 #define CCU_SYS_USB_BASE                0x074
  49 #define CCU_SYS_PVT_BASE                0x078
  50 #define CCU_SYS_HWA_BASE                0x07C
  51 #define CCU_SYS_UART_BASE               0x084
  52 #define CCU_SYS_TIMER0_BASE             0x088
  53 #define CCU_SYS_TIMER1_BASE             0x08C
  54 #define CCU_SYS_TIMER2_BASE             0x090
  55 #define CCU_SYS_WDT_BASE                0x150
  56
  57 #define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
  58         {                                                               \
  59                 .id = _id,                                              \
  60                 .name = _name,                                          \
  61                 .parent_name = _pname,                                  \
  62                 .base = _base,                                          \
  63                 .type = CCU_DIV_VAR,                                    \
  64                 .width = _width,                                        \
  65                 .flags = _flags,                                        \
  66                 .features = _features                                   \
  67         }
  68
  69 #define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider)  \
  70         {                                                       \
  71                 .id = _id,                                      \
  72                 .name = _name,                                  \
  73                 .parent_name = _pname,                          \
  74                 .base = _base,                                  \
  75                 .type = CCU_DIV_GATE,                           \
  76                 .divider = _divider                             \
  77         }
  78
  79 #define CCU_DIV_BUF_INFO(_id, _name, _pname, _base, _flags)     \
  80         {                                                       \
  81                 .id = _id,                                      \
  82                 .name = _name,                                  \
  83                 .parent_name = _pname,                          \
  84                 .base = _base,                                  \
  85                 .type = CCU_DIV_BUF,                            \
  86                 .flags = _flags                                 \
  87         }
  88
  89 #define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider)        \
  90         {                                                       \
  91                 .id = _id,                                      \
  92                 .name = _name,                                  \
  93                 .parent_name = _pname,                          \
  94                 .type = CCU_DIV_FIXED,                          \
  95                 .divider = _divider                             \
  96         }
  97
  98 #define CCU_DIV_RST_MAP(_rst_id, _clk_id)       \
  99         {                                       \
 100                 .rst_id = _rst_id,              \
 101                 .clk_id = _clk_id               \
 102         }
 103
 104 struct ccu_div_info {
 105         unsigned int id;
 106         const char *name;
 107         const char *parent_name;
 108         unsigned int base;
 109         enum ccu_div_type type;
 110         union {
 111                 unsigned int width;
 112                 unsigned int divider;
 113         };
 114         unsigned long flags;
 115         unsigned long features;
 116 };
 117
 118 struct ccu_div_rst_map {
 119         unsigned int rst_id;
 120         unsigned int clk_id;
 121 };
 122
 123 struct ccu_div_data {
 124         struct device_node *np;
 125         struct regmap *sys_regs;
 126
 127         unsigned int divs_num;
 128         const struct ccu_div_info *divs_info;
 129         struct ccu_div **divs;
 130
 131         unsigned int rst_num;
 132         const struct ccu_div_rst_map *rst_map;
 133         struct reset_controller_dev rcdev;
 134 };
 135 #define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
 136
 137 /*
 138  * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
 139  * must be left enabled in any case, since former one is responsible for
 140  * clocking a bus between CPU cores and the rest of the SoC components, while
 141  * the later is clocking the AXI-bus between DDR controller and the Main
 142  * Interconnect. So should any of these clocks get to be disabled, the system
 143  * will literally stop working. That's why we marked them as critical.
 144  */
 145 static const struct ccu_div_info axi_info[] = {
 146         CCU_DIV_VAR_INFO(CCU_AXI_MAIN_CLK, "axi_main_clk", "pcie_clk",
 147                          CCU_AXI_MAIN_BASE, 4,
 148                          CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
 149         CCU_DIV_VAR_INFO(CCU_AXI_DDR_CLK, "axi_ddr_clk", "sata_clk",
 150                          CCU_AXI_DDR_BASE, 4,
 151                          CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
 152                          CCU_DIV_RESET_DOMAIN),
 153         CCU_DIV_VAR_INFO(CCU_AXI_SATA_CLK, "axi_sata_clk", "sata_clk",
 154                          CCU_AXI_SATA_BASE, 4,
 155                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 156         CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
 157                          CCU_AXI_GMAC0_BASE, 4,
 158                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 159         CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
 160                          CCU_AXI_GMAC1_BASE, 4,
 161                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 162         CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
 163                          CCU_AXI_XGMAC_BASE, 4,
 164                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 165         CCU_DIV_VAR_INFO(CCU_AXI_PCIE_M_CLK, "axi_pcie_m_clk", "pcie_clk",
 166                          CCU_AXI_PCIE_M_BASE, 4,
 167                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 168         CCU_DIV_VAR_INFO(CCU_AXI_PCIE_S_CLK, "axi_pcie_s_clk", "pcie_clk",
 169                          CCU_AXI_PCIE_S_BASE, 4,
 170                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 171         CCU_DIV_VAR_INFO(CCU_AXI_USB_CLK, "axi_usb_clk", "sata_clk",
 172                          CCU_AXI_USB_BASE, 4,
 173                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 174         CCU_DIV_VAR_INFO(CCU_AXI_HWA_CLK, "axi_hwa_clk", "sata_clk",
 175                          CCU_AXI_HWA_BASE, 4,
 176                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
 177         CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
 178                          CCU_AXI_SRAM_BASE, 4,
 179                          CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
 180 };
 181
 182 static const struct ccu_div_rst_map axi_rst_map[] = {
 183         CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
 184         CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
 185         CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
 186         CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
 187         CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
 188         CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
 189         CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
 190         CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
 191         CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
 192         CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
 193         CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
 194 };
 195
 196 /*
 197  * APB-bus clock is marked as critical since it's a main communication bus
 198  * for the SoC devices registers IO-operations.
 199  */
 200 static const struct ccu_div_info sys_info[] = {
 201         CCU_DIV_VAR_INFO(CCU_SYS_SATA_CLK, "sys_sata_clk",
 202                          "sata_clk", CCU_SYS_SATA_REF_BASE, 4,
 203                          CLK_SET_RATE_GATE,
 204                          CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
 205                          CCU_DIV_RESET_DOMAIN),
 206         CCU_DIV_BUF_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
 207                          "sys_sata_clk", CCU_SYS_SATA_REF_BASE,
 208                          CLK_SET_RATE_PARENT),
 209         CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
 210                          "pcie_clk", CCU_SYS_APB_BASE, 5,
 211                          CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
 212         CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
 213                           "eth_clk", CCU_SYS_GMAC0_BASE, 5),
 214         CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
 215                            "eth_clk", 10),
 216         CCU_DIV_GATE_INFO(CCU_SYS_GMAC1_TX_CLK, "sys_gmac1_tx_clk",
 217                           "eth_clk", CCU_SYS_GMAC1_BASE, 5),
 218         CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
 219                            "eth_clk", 10),
 220         CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_CLK, "sys_xgmac_clk",
 221                           "eth_clk", CCU_SYS_XGMAC_BASE, 1),
 222         CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
 223                            "sys_xgmac_clk", 8),
 224         CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
 225                            "sys_xgmac_clk", 8),
 226         CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
 227                           "eth_clk", CCU_SYS_USB_BASE, 10),
 228         CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
 229                          "ref_clk", CCU_SYS_PVT_BASE, 5,
 230                          CLK_SET_RATE_GATE, 0),
 231         CCU_DIV_VAR_INFO(CCU_SYS_HWA_CLK, "sys_hwa_clk",
 232                          "sata_clk", CCU_SYS_HWA_BASE, 4,
 233                          CLK_SET_RATE_GATE, 0),
 234         CCU_DIV_VAR_INFO(CCU_SYS_UART_CLK, "sys_uart_clk",
 235                          "eth_clk", CCU_SYS_UART_BASE, 17,
 236                          CLK_SET_RATE_GATE, 0),
 237         CCU_DIV_FIXED_INFO(CCU_SYS_I2C1_CLK, "sys_i2c1_clk",
 238                            "eth_clk", 10),
 239         CCU_DIV_FIXED_INFO(CCU_SYS_I2C2_CLK, "sys_i2c2_clk",
 240                            "eth_clk", 10),
 241         CCU_DIV_FIXED_INFO(CCU_SYS_GPIO_CLK, "sys_gpio_clk",
 242                            "ref_clk", 25),
 243         CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
 244                          "ref_clk", CCU_SYS_TIMER0_BASE, 17,
 245                          CLK_SET_RATE_GATE, 0),
 246         CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
 247                          "ref_clk", CCU_SYS_TIMER1_BASE, 17,
 248                          CLK_SET_RATE_GATE, 0),
 249         CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
 250                          "ref_clk", CCU_SYS_TIMER2_BASE, 17,
 251                          CLK_SET_RATE_GATE, 0),
 252         CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
 253                          "eth_clk", CCU_SYS_WDT_BASE, 17,
 254                          CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
 255 };
 256
 257 static const struct ccu_div_rst_map sys_rst_map[] = {
 258         CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
 259         CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
 260 };
 261
 262 static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
 263                                          unsigned int clk_id)
 264 {
 265         struct ccu_div *div;
 266         int idx;
 267
 268         for (idx = 0; idx < data->divs_num; ++idx) {
 269                 div = data->divs[idx];
 270                 if (div && div->id == clk_id)
 271                         return div;
 272         }
 273
 274         return ERR_PTR(-EINVAL);
 275 }
 276
 277 static int ccu_div_reset(struct reset_controller_dev *rcdev,
 278                          unsigned long rst_id)
 279 {
 280         struct ccu_div_data *data = to_ccu_div_data(rcdev);
 281         const struct ccu_div_rst_map *map;
 282         struct ccu_div *div;
 283         int idx, ret;
 284
 285         for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
 286                 if (map->rst_id == rst_id)
 287                         break;
 288         }
 289         if (idx == data->rst_num) {
 290                 pr_err("Invalid reset ID %lu specified\n", rst_id);
 291                 return -EINVAL;
 292         }
 293
 294         div = ccu_div_find_desc(data, map->clk_id);
 295         if (IS_ERR(div)) {
 296                 pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
 297                 return PTR_ERR(div);
 298         }
 299
 300         ret = ccu_div_reset_domain(div);
 301         if (ret) {
 302                 pr_err("Reset isn't supported by divider %s\n",
 303                         clk_hw_get_name(ccu_div_get_clk_hw(div)));
 304         }
 305
 306         return ret;
 307 }
 308
 309 static const struct reset_control_ops ccu_div_rst_ops = {
 310         .reset = ccu_div_reset,
 311 };
 312
 313 static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
 314 {
 315         struct ccu_div_data *data;
 316         int ret;
 317
 318         data = kzalloc(sizeof(*data), GFP_KERNEL);
 319         if (!data)
 320                 return ERR_PTR(-ENOMEM);
 321
 322         data->np = np;
 323         if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
 324                 data->divs_num = ARRAY_SIZE(axi_info);
 325                 data->divs_info = axi_info;
 326                 data->rst_num = ARRAY_SIZE(axi_rst_map);
 327                 data->rst_map = axi_rst_map;
 328         } else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
 329                 data->divs_num = ARRAY_SIZE(sys_info);
 330                 data->divs_info = sys_info;
 331                 data->rst_num = ARRAY_SIZE(sys_rst_map);
 332                 data->rst_map = sys_rst_map;
 333         } else {
 334                 pr_err("Incompatible DT node '%s' specified\n",
 335                         of_node_full_name(np));
 336                 ret = -EINVAL;
 337                 goto err_kfree_data;
 338         }
 339
 340         data->divs = kcalloc(data->divs_num, sizeof(*data->divs), GFP_KERNEL);
 341         if (!data->divs) {
 342                 ret = -ENOMEM;
 343                 goto err_kfree_data;
 344         }
 345
 346         return data;
 347
 348 err_kfree_data:
 349         kfree(data);
 350
 351         return ERR_PTR(ret);
 352 }
 353
 354 static void ccu_div_free_data(struct ccu_div_data *data)
 355 {
 356         kfree(data->divs);
 357
 358         kfree(data);
 359 }
 360
 361 static int ccu_div_find_sys_regs(struct ccu_div_data *data)
 362 {
 363         data->sys_regs = syscon_node_to_regmap(data->np->parent);
 364         if (IS_ERR(data->sys_regs)) {
 365                 pr_err("Failed to find syscon regs for '%s'\n",
 366                         of_node_full_name(data->np));
 367                 return PTR_ERR(data->sys_regs);
 368         }
 369
 370         return 0;
 371 }
 372
 373 static struct clk_hw *ccu_div_of_clk_hw_get(struct of_phandle_args *clkspec,
 374                                             void *priv)
 375 {
 376         struct ccu_div_data *data = priv;
 377         struct ccu_div *div;
 378         unsigned int clk_id;
 379
 380         clk_id = clkspec->args[0];
 381         div = ccu_div_find_desc(data, clk_id);
 382         if (IS_ERR(div)) {
 383                 pr_info("Invalid clock ID %d specified\n", clk_id);
 384                 return ERR_CAST(div);
 385         }
 386
 387         return ccu_div_get_clk_hw(div);
 388 }
 389
 390 static int ccu_div_clk_register(struct ccu_div_data *data)
 391 {
 392         int idx, ret;
 393
 394         for (idx = 0; idx < data->divs_num; ++idx) {
 395                 const struct ccu_div_info *info = &data->divs_info[idx];
 396                 struct ccu_div_init_data init = {0};
 397
 398                 init.id = info->id;
 399                 init.name = info->name;
 400                 init.parent_name = info->parent_name;
 401                 init.np = data->np;
 402                 init.type = info->type;
 403                 init.flags = info->flags;
 404                 init.features = info->features;
 405
 406                 if (init.type == CCU_DIV_VAR) {
 407                         init.base = info->base;
 408                         init.sys_regs = data->sys_regs;
 409                         init.width = info->width;
 410                 } else if (init.type == CCU_DIV_GATE) {
 411                         init.base = info->base;
 412                         init.sys_regs = data->sys_regs;
 413                         init.divider = info->divider;
 414                 } else if (init.type == CCU_DIV_BUF) {
 415                         init.base = info->base;
 416                         init.sys_regs = data->sys_regs;
 417                 } else {
 418                         init.divider = info->divider;
 419                 }
 420
 421                 data->divs[idx] = ccu_div_hw_register(&init);
 422                 if (IS_ERR(data->divs[idx])) {
 423                         ret = PTR_ERR(data->divs[idx]);
 424                         pr_err("Couldn't register divider '%s' hw\n",
 425                                 init.name);
 426                         goto err_hw_unregister;
 427                 }
 428         }
 429
 430         ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
 431         if (ret) {
 432                 pr_err("Couldn't register dividers '%s' clock provider\n",
 433                         of_node_full_name(data->np));
 434                 goto err_hw_unregister;
 435         }
 436
 437         return 0;
 438
 439 err_hw_unregister:
 440         for (--idx; idx >= 0; --idx)
 441                 ccu_div_hw_unregister(data->divs[idx]);
 442
 443         return ret;
 444 }
 445
 446 static void ccu_div_clk_unregister(struct ccu_div_data *data)
 447 {
 448         int idx;
 449
 450         of_clk_del_provider(data->np);
 451
 452         for (idx = 0; idx < data->divs_num; ++idx)
 453                 ccu_div_hw_unregister(data->divs[idx]);
 454 }
 455
 456 static int ccu_div_rst_register(struct ccu_div_data *data)
 457 {
 458         int ret;
 459
 460         data->rcdev.ops = &ccu_div_rst_ops;
 461         data->rcdev.of_node = data->np;
 462         data->rcdev.nr_resets = data->rst_num;
 463
 464         ret = reset_controller_register(&data->rcdev);
 465         if (ret)
 466                 pr_err("Couldn't register divider '%s' reset controller\n",
 467                         of_node_full_name(data->np));
 468
 469         return ret;
 470 }
 471
 472 static void ccu_div_init(struct device_node *np)
 473 {
 474         struct ccu_div_data *data;
 475         int ret;
 476
 477         data = ccu_div_create_data(np);
 478         if (IS_ERR(data))
 479                 return;
 480
 481         ret = ccu_div_find_sys_regs(data);
 482         if (ret)
 483                 goto err_free_data;
 484
 485         ret = ccu_div_clk_register(data);
 486         if (ret)
 487                 goto err_free_data;
 488
 489         ret = ccu_div_rst_register(data);
 490         if (ret)
 491                 goto err_clk_unregister;
 492
 493         return;
 494
 495 err_clk_unregister:
 496         ccu_div_clk_unregister(data);
 497
 498 err_free_data:
 499         ccu_div_free_data(data);
 500 }
 501
 502 CLK_OF_DECLARE(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
 503 CLK_OF_DECLARE(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);