1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
6 #include <dt-bindings/clock/at91.h>
10 static DEFINE_SPINLOCK(mck_lock);
12 static const struct clk_master_characteristics mck_characteristics = {
13 .output = { .min = 124000000, .max = 166000000 },
14 .divisors = { 1, 2, 4, 3 },
17 static u8 plla_out[] = { 0 };
19 static u16 plla_icpll[] = { 0 };
21 static const struct clk_range plla_outputs[] = {
22 { .min = 600000000, .max = 1200000000 },
25 static const struct clk_pll_characteristics plla_characteristics = {
26 .input = { .min = 12000000, .max = 24000000 },
27 .num_output = ARRAY_SIZE(plla_outputs),
28 .output = plla_outputs,
33 static const struct clk_pcr_layout sama5d2_pcr_layout = {
36 .gckcss_mask = GENMASK(10, 8),
37 .pid_mask = GENMASK(6, 0),
44 } sama5d2_systemck[] = {
45 { .n = "ddrck", .p = "masterck_div", .id = 2 },
46 { .n = "lcdck", .p = "masterck_div", .id = 3 },
47 { .n = "uhpck", .p = "usbck", .id = 6 },
48 { .n = "udpck", .p = "usbck", .id = 7 },
49 { .n = "pck0", .p = "prog0", .id = 8 },
50 { .n = "pck1", .p = "prog1", .id = 9 },
51 { .n = "pck2", .p = "prog2", .id = 10 },
52 { .n = "iscck", .p = "masterck_div", .id = 18 },
59 } sama5d2_periph32ck[] = {
60 { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, },
61 { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, },
62 { .n = "matrix1_clk", .id = 14, },
63 { .n = "hsmc_clk", .id = 17, },
64 { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, },
65 { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, },
66 { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, },
67 { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, },
68 { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, },
69 { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, },
70 { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, },
71 { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, },
72 { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, },
73 { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, },
74 { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, },
75 { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
76 { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, },
77 { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, },
78 { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, },
79 { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
80 { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
81 { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
82 { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
83 { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
84 { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, },
85 { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, },
86 { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, },
87 { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
88 { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
89 { .n = "securam_clk", .id = 51, },
90 { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
91 { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
92 { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
93 { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
94 { .n = "ptc_clk", .id = 58, .r = { .min = 0, .max = 83000000 }, },
95 { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
101 } sama5d2_periphck[] = {
102 { .n = "dma0_clk", .id = 6, },
103 { .n = "dma1_clk", .id = 7, },
104 { .n = "aes_clk", .id = 9, },
105 { .n = "aesb_clk", .id = 10, },
106 { .n = "sha_clk", .id = 12, },
107 { .n = "mpddr_clk", .id = 13, },
108 { .n = "matrix0_clk", .id = 15, },
109 { .n = "sdmmc0_hclk", .id = 31, },
110 { .n = "sdmmc1_hclk", .id = 32, },
111 { .n = "lcdc_clk", .id = 45, },
112 { .n = "isc_clk", .id = 46, },
113 { .n = "qspi0_clk", .id = 52, },
114 { .n = "qspi1_clk", .id = 53, },
117 static const struct {
123 { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
124 { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
125 { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
126 { .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
127 { .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
128 { .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, },
129 { .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, },
130 { .n = "i2s0_gclk", .id = 54, .chg_pid = 5, },
131 { .n = "i2s1_gclk", .id = 55, .chg_pid = 5, },
132 { .n = "can0_gclk", .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
133 { .n = "can1_gclk", .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
134 { .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },
137 static const struct clk_programmable_layout sama5d2_programmable_layout = {
145 static void __init sama5d2_pmc_setup(struct device_node *np)
147 struct clk_range range = CLK_RANGE(0, 0);
148 const char *slck_name, *mainxtal_name;
149 struct pmc_data *sama5d2_pmc;
150 const char *parent_names[6];
151 struct regmap *regmap, *regmap_sfr;
156 i = of_property_match_string(np, "clock-names", "slow_clk");
160 slck_name = of_clk_get_parent_name(np, i);
162 i = of_property_match_string(np, "clock-names", "main_xtal");
165 mainxtal_name = of_clk_get_parent_name(np, i);
167 regmap = device_node_to_regmap(np);
171 sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPLLCK + 1,
172 nck(sama5d2_systemck),
173 nck(sama5d2_periph32ck),
174 nck(sama5d2_gck), 3);
178 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
183 bypass = of_property_read_bool(np, "atmel,osc-bypass");
185 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
190 parent_names[0] = "main_rc_osc";
191 parent_names[1] = "main_osc";
192 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
196 sama5d2_pmc->chws[PMC_MAIN] = hw;
198 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
199 &sama5d3_pll_layout, &plla_characteristics);
203 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
207 sama5d2_pmc->chws[PMC_PLLACK] = hw;
209 hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
214 hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
219 hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
224 sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw;
226 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
227 if (IS_ERR(regmap_sfr))
230 hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
234 sama5d2_pmc->chws[PMC_UTMI] = hw;
236 parent_names[0] = slck_name;
237 parent_names[1] = "mainck";
238 parent_names[2] = "plladivck";
239 parent_names[3] = "utmick";
240 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
242 &at91sam9x5_master_layout,
243 &mck_characteristics, &mck_lock,
244 CLK_SET_RATE_GATE, INT_MIN);
248 hw = at91_clk_register_master_div(regmap, "masterck_div",
250 &at91sam9x5_master_layout,
251 &mck_characteristics, &mck_lock,
256 sama5d2_pmc->chws[PMC_MCK] = hw;
258 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
262 sama5d2_pmc->chws[PMC_MCK2] = hw;
264 parent_names[0] = "plladivck";
265 parent_names[1] = "utmick";
266 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
270 parent_names[0] = slck_name;
271 parent_names[1] = "mainck";
272 parent_names[2] = "plladivck";
273 parent_names[3] = "utmick";
274 parent_names[4] = "masterck_div";
275 parent_names[5] = "audiopll_pmcck";
276 for (i = 0; i < 3; i++) {
279 snprintf(name, sizeof(name), "prog%d", i);
281 hw = at91_clk_register_programmable(regmap, name,
283 &sama5d2_programmable_layout,
288 sama5d2_pmc->pchws[i] = hw;
291 for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
292 hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
293 sama5d2_systemck[i].p,
294 sama5d2_systemck[i].id);
298 sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
301 for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
302 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
304 sama5d2_periphck[i].n,
306 sama5d2_periphck[i].id,
311 sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
314 for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
315 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
317 sama5d2_periph32ck[i].n,
319 sama5d2_periph32ck[i].id,
320 &sama5d2_periph32ck[i].r,
325 sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
328 parent_names[0] = slck_name;
329 parent_names[1] = "mainck";
330 parent_names[2] = "plladivck";
331 parent_names[3] = "utmick";
332 parent_names[4] = "masterck_div";
333 parent_names[5] = "audiopll_pmcck";
334 for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
335 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
338 parent_names, NULL, 6,
341 sama5d2_gck[i].chg_pid);
345 sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
349 parent_names[0] = "i2s0_clk";
350 parent_names[1] = "i2s0_gclk";
351 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
356 sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
358 parent_names[0] = "i2s1_clk";
359 parent_names[1] = "i2s1_gclk";
360 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
365 sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
368 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
376 CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);