1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
8 #include <linux/clk/at91_pmc.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/regmap.h>
12 #include <soc/at91/atmel-sfr.h>
17 * The purpose of this clock is to generate a 480 MHz signal. A different
18 * rate can't be configured.
20 #define UTMI_RATE 480000000
24 struct regmap *regmap_pmc;
25 struct regmap *regmap_sfr;
26 struct at91_clk_pms pms;
29 #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
31 static inline bool clk_utmi_ready(struct regmap *regmap)
35 regmap_read(regmap, AT91_PMC_SR, &status);
37 return status & AT91_PMC_LOCKU;
40 static int clk_utmi_prepare(struct clk_hw *hw)
42 struct clk_hw *hw_parent;
43 struct clk_utmi *utmi = to_clk_utmi(hw);
44 unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
46 unsigned int utmi_ref_clk_freq;
47 unsigned long parent_rate;
50 * If mainck rate is different from 12 MHz, we have to configure the
51 * FREQ field of the SFR_UTMICKTRIM register to generate properly
54 hw_parent = clk_hw_get_parent(hw);
55 parent_rate = clk_hw_get_rate(hw_parent);
57 switch (parent_rate) {
59 utmi_ref_clk_freq = 0;
62 utmi_ref_clk_freq = 1;
65 utmi_ref_clk_freq = 2;
68 * Not supported on SAMA5D2 but it's not an issue since MAINCK
69 * maximum value is 24 MHz.
72 utmi_ref_clk_freq = 3;
75 pr_err("UTMICK: unsupported mainck rate\n");
79 if (utmi->regmap_sfr) {
80 regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
81 AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
82 } else if (utmi_ref_clk_freq) {
83 pr_err("UTMICK: sfr node required\n");
87 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr);
89 while (!clk_utmi_ready(utmi->regmap_pmc))
95 static int clk_utmi_is_prepared(struct clk_hw *hw)
97 struct clk_utmi *utmi = to_clk_utmi(hw);
99 return clk_utmi_ready(utmi->regmap_pmc);
102 static void clk_utmi_unprepare(struct clk_hw *hw)
104 struct clk_utmi *utmi = to_clk_utmi(hw);
106 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR,
110 static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate)
113 /* UTMI clk rate is fixed. */
117 static int clk_utmi_save_context(struct clk_hw *hw)
119 struct clk_utmi *utmi = to_clk_utmi(hw);
121 utmi->pms.status = clk_utmi_is_prepared(hw);
126 static void clk_utmi_restore_context(struct clk_hw *hw)
128 struct clk_utmi *utmi = to_clk_utmi(hw);
130 if (utmi->pms.status)
131 clk_utmi_prepare(hw);
134 static const struct clk_ops utmi_ops = {
135 .prepare = clk_utmi_prepare,
136 .unprepare = clk_utmi_unprepare,
137 .is_prepared = clk_utmi_is_prepared,
138 .recalc_rate = clk_utmi_recalc_rate,
139 .save_context = clk_utmi_save_context,
140 .restore_context = clk_utmi_restore_context,
143 static struct clk_hw * __init
144 at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
145 struct regmap *regmap_sfr,
146 const char *name, const char *parent_name,
147 const struct clk_ops *ops, unsigned long flags)
149 struct clk_utmi *utmi;
151 struct clk_init_data init;
154 utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
156 return ERR_PTR(-ENOMEM);
160 init.parent_names = parent_name ? &parent_name : NULL;
161 init.num_parents = parent_name ? 1 : 0;
164 utmi->hw.init = &init;
165 utmi->regmap_pmc = regmap_pmc;
166 utmi->regmap_sfr = regmap_sfr;
169 ret = clk_hw_register(NULL, &utmi->hw);
178 struct clk_hw * __init
179 at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
180 const char *name, const char *parent_name)
182 return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name,
183 parent_name, &utmi_ops, CLK_SET_RATE_GATE);
186 static int clk_utmi_sama7g5_prepare(struct clk_hw *hw)
188 struct clk_utmi *utmi = to_clk_utmi(hw);
189 struct clk_hw *hw_parent;
190 unsigned long parent_rate;
193 hw_parent = clk_hw_get_parent(hw);
194 parent_rate = clk_hw_get_rate(hw_parent);
196 switch (parent_rate) {
210 pr_err("UTMICK: unsupported main_xtal rate\n");
214 regmap_write(utmi->regmap_pmc, AT91_PMC_XTALF, val);
220 static int clk_utmi_sama7g5_is_prepared(struct clk_hw *hw)
222 struct clk_utmi *utmi = to_clk_utmi(hw);
223 struct clk_hw *hw_parent;
224 unsigned long parent_rate;
227 hw_parent = clk_hw_get_parent(hw);
228 parent_rate = clk_hw_get_rate(hw_parent);
230 regmap_read(utmi->regmap_pmc, AT91_PMC_XTALF, &val);
233 if (parent_rate == 16000000)
237 if (parent_rate == 20000000)
241 if (parent_rate == 24000000)
245 if (parent_rate == 32000000)
255 static int clk_utmi_sama7g5_save_context(struct clk_hw *hw)
257 struct clk_utmi *utmi = to_clk_utmi(hw);
259 utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw);
264 static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw)
266 struct clk_utmi *utmi = to_clk_utmi(hw);
268 if (utmi->pms.status)
269 clk_utmi_sama7g5_prepare(hw);
272 static const struct clk_ops sama7g5_utmi_ops = {
273 .prepare = clk_utmi_sama7g5_prepare,
274 .is_prepared = clk_utmi_sama7g5_is_prepared,
275 .recalc_rate = clk_utmi_recalc_rate,
276 .save_context = clk_utmi_sama7g5_save_context,
277 .restore_context = clk_utmi_sama7g5_restore_context,
280 struct clk_hw * __init
281 at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name,
282 const char *parent_name)
284 return at91_clk_register_utmi_internal(regmap_pmc, NULL, name,
285 parent_name, &sama7g5_utmi_ops, 0);