2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk/at91_pmc.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/regmap.h>
20 #define USB_SOURCE_MAX 2
22 #define SAM9X5_USB_DIV_SHIFT 8
23 #define SAM9X5_USB_MAX_DIV 0xf
25 #define RM9200_USB_DIV_SHIFT 28
26 #define RM9200_USB_DIV_TAB_SIZE 4
28 struct at91sam9x5_clk_usb {
30 struct regmap *regmap;
33 #define to_at91sam9x5_clk_usb(hw) \
34 container_of(hw, struct at91sam9x5_clk_usb, hw)
36 struct at91rm9200_clk_usb {
38 struct regmap *regmap;
42 #define to_at91rm9200_clk_usb(hw) \
43 container_of(hw, struct at91rm9200_clk_usb, hw)
45 static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
46 unsigned long parent_rate)
48 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
52 regmap_read(usb->regmap, AT91_PMC_USB, &usbr);
53 usbdiv = (usbr & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT;
55 return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1));
58 static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,
59 struct clk_rate_request *req)
61 struct clk_hw *parent;
62 long best_rate = -EINVAL;
63 unsigned long tmp_rate;
68 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
71 parent = clk_hw_get_parent_by_index(hw, i);
75 for (div = 1; div < SAM9X5_USB_MAX_DIV + 2; div++) {
76 unsigned long tmp_parent_rate;
78 tmp_parent_rate = req->rate * div;
79 tmp_parent_rate = clk_hw_round_rate(parent,
84 tmp_rate = DIV_ROUND_CLOSEST(tmp_parent_rate, div);
85 if (tmp_rate < req->rate)
86 tmp_diff = req->rate - tmp_rate;
88 tmp_diff = tmp_rate - req->rate;
90 if (best_diff < 0 || best_diff > tmp_diff) {
93 req->best_parent_rate = tmp_parent_rate;
94 req->best_parent_hw = parent;
97 if (!best_diff || tmp_rate < req->rate)
108 req->rate = best_rate;
112 static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
114 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
119 regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS,
120 index ? AT91_PMC_USBS : 0);
125 static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
127 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
130 regmap_read(usb->regmap, AT91_PMC_USB, &usbr);
132 return usbr & AT91_PMC_USBS;
135 static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
136 unsigned long parent_rate)
138 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
144 div = DIV_ROUND_CLOSEST(parent_rate, rate);
145 if (div > SAM9X5_USB_MAX_DIV + 1 || !div)
148 regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_OHCIUSBDIV,
149 (div - 1) << SAM9X5_USB_DIV_SHIFT);
154 static const struct clk_ops at91sam9x5_usb_ops = {
155 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
156 .determine_rate = at91sam9x5_clk_usb_determine_rate,
157 .get_parent = at91sam9x5_clk_usb_get_parent,
158 .set_parent = at91sam9x5_clk_usb_set_parent,
159 .set_rate = at91sam9x5_clk_usb_set_rate,
162 static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
164 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
166 regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS,
172 static void at91sam9n12_clk_usb_disable(struct clk_hw *hw)
174 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
176 regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, 0);
179 static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw)
181 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
184 regmap_read(usb->regmap, AT91_PMC_USB, &usbr);
186 return usbr & AT91_PMC_USBS;
189 static const struct clk_ops at91sam9n12_usb_ops = {
190 .enable = at91sam9n12_clk_usb_enable,
191 .disable = at91sam9n12_clk_usb_disable,
192 .is_enabled = at91sam9n12_clk_usb_is_enabled,
193 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
194 .determine_rate = at91sam9x5_clk_usb_determine_rate,
195 .set_rate = at91sam9x5_clk_usb_set_rate,
198 static struct clk_hw * __init
199 at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
200 const char **parent_names, u8 num_parents)
202 struct at91sam9x5_clk_usb *usb;
204 struct clk_init_data init;
207 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
209 return ERR_PTR(-ENOMEM);
212 init.ops = &at91sam9x5_usb_ops;
213 init.parent_names = parent_names;
214 init.num_parents = num_parents;
215 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
218 usb->hw.init = &init;
219 usb->regmap = regmap;
222 ret = clk_hw_register(NULL, &usb->hw);
231 static struct clk_hw * __init
232 at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
233 const char *parent_name)
235 struct at91sam9x5_clk_usb *usb;
237 struct clk_init_data init;
240 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
242 return ERR_PTR(-ENOMEM);
245 init.ops = &at91sam9n12_usb_ops;
246 init.parent_names = &parent_name;
247 init.num_parents = 1;
248 init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
250 usb->hw.init = &init;
251 usb->regmap = regmap;
254 ret = clk_hw_register(NULL, &usb->hw);
263 static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
264 unsigned long parent_rate)
266 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
270 regmap_read(usb->regmap, AT91_CKGR_PLLBR, &pllbr);
272 usbdiv = (pllbr & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT;
273 if (usb->divisors[usbdiv])
274 return parent_rate / usb->divisors[usbdiv];
279 static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
280 unsigned long *parent_rate)
282 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
283 struct clk_hw *parent = clk_hw_get_parent(hw);
284 unsigned long bestrate = 0;
286 unsigned long tmprate;
290 for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
291 unsigned long tmp_parent_rate;
293 if (!usb->divisors[i])
296 tmp_parent_rate = rate * usb->divisors[i];
297 tmp_parent_rate = clk_hw_round_rate(parent, tmp_parent_rate);
298 tmprate = DIV_ROUND_CLOSEST(tmp_parent_rate, usb->divisors[i]);
300 tmpdiff = rate - tmprate;
302 tmpdiff = tmprate - rate;
304 if (bestdiff < 0 || bestdiff > tmpdiff) {
307 *parent_rate = tmp_parent_rate;
317 static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
318 unsigned long parent_rate)
321 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
327 div = DIV_ROUND_CLOSEST(parent_rate, rate);
329 for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
330 if (usb->divisors[i] == div) {
331 regmap_update_bits(usb->regmap, AT91_CKGR_PLLBR,
333 i << RM9200_USB_DIV_SHIFT);
342 static const struct clk_ops at91rm9200_usb_ops = {
343 .recalc_rate = at91rm9200_clk_usb_recalc_rate,
344 .round_rate = at91rm9200_clk_usb_round_rate,
345 .set_rate = at91rm9200_clk_usb_set_rate,
348 static struct clk_hw * __init
349 at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
350 const char *parent_name, const u32 *divisors)
352 struct at91rm9200_clk_usb *usb;
354 struct clk_init_data init;
357 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
359 return ERR_PTR(-ENOMEM);
362 init.ops = &at91rm9200_usb_ops;
363 init.parent_names = &parent_name;
364 init.num_parents = 1;
365 init.flags = CLK_SET_RATE_PARENT;
367 usb->hw.init = &init;
368 usb->regmap = regmap;
369 memcpy(usb->divisors, divisors, sizeof(usb->divisors));
372 ret = clk_hw_register(NULL, &usb->hw);
381 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
384 unsigned int num_parents;
385 const char *parent_names[USB_SOURCE_MAX];
386 const char *name = np->name;
387 struct regmap *regmap;
389 num_parents = of_clk_get_parent_count(np);
390 if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
393 of_clk_parent_fill(np, parent_names, num_parents);
395 of_property_read_string(np, "clock-output-names", &name);
397 regmap = syscon_node_to_regmap(of_get_parent(np));
401 hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
406 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
408 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
409 of_at91sam9x5_clk_usb_setup);
411 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
414 const char *parent_name;
415 const char *name = np->name;
416 struct regmap *regmap;
418 parent_name = of_clk_get_parent_name(np, 0);
422 of_property_read_string(np, "clock-output-names", &name);
424 regmap = syscon_node_to_regmap(of_get_parent(np));
428 hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
432 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
434 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
435 of_at91sam9n12_clk_usb_setup);
437 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
440 const char *parent_name;
441 const char *name = np->name;
442 u32 divisors[4] = {0, 0, 0, 0};
443 struct regmap *regmap;
445 parent_name = of_clk_get_parent_name(np, 0);
449 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
453 of_property_read_string(np, "clock-output-names", &name);
455 regmap = syscon_node_to_regmap(of_get_parent(np));
458 hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
462 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
464 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
465 of_at91rm9200_clk_usb_setup);