2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk/at91_pmc.h>
14 #include <linux/delay.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
21 #define SLOW_CLOCK_FREQ 32768
23 #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
25 #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
26 #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
28 #define MOR_KEY_MASK (0xff << 16)
30 #define clk_main_parent_select(s) (((s) & \
32 AT91_PMC_OSCBYPASS)) ? 1 : 0)
36 struct regmap *regmap;
39 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
41 struct clk_main_rc_osc {
43 struct regmap *regmap;
44 unsigned long frequency;
45 unsigned long accuracy;
48 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
50 struct clk_rm9200_main {
52 struct regmap *regmap;
55 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
57 struct clk_sam9x5_main {
59 struct regmap *regmap;
63 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
65 static inline bool clk_main_osc_ready(struct regmap *regmap)
69 regmap_read(regmap, AT91_PMC_SR, &status);
71 return status & AT91_PMC_MOSCS;
74 static int clk_main_osc_prepare(struct clk_hw *hw)
76 struct clk_main_osc *osc = to_clk_main_osc(hw);
77 struct regmap *regmap = osc->regmap;
80 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
83 if (tmp & AT91_PMC_OSCBYPASS)
86 if (!(tmp & AT91_PMC_MOSCEN)) {
87 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
88 regmap_write(regmap, AT91_CKGR_MOR, tmp);
91 while (!clk_main_osc_ready(regmap))
97 static void clk_main_osc_unprepare(struct clk_hw *hw)
99 struct clk_main_osc *osc = to_clk_main_osc(hw);
100 struct regmap *regmap = osc->regmap;
103 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
104 if (tmp & AT91_PMC_OSCBYPASS)
107 if (!(tmp & AT91_PMC_MOSCEN))
110 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
111 regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
114 static int clk_main_osc_is_prepared(struct clk_hw *hw)
116 struct clk_main_osc *osc = to_clk_main_osc(hw);
117 struct regmap *regmap = osc->regmap;
120 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
121 if (tmp & AT91_PMC_OSCBYPASS)
124 regmap_read(regmap, AT91_PMC_SR, &status);
126 return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
129 static const struct clk_ops main_osc_ops = {
130 .prepare = clk_main_osc_prepare,
131 .unprepare = clk_main_osc_unprepare,
132 .is_prepared = clk_main_osc_is_prepared,
135 static struct clk_hw * __init
136 at91_clk_register_main_osc(struct regmap *regmap,
138 const char *parent_name,
141 struct clk_main_osc *osc;
142 struct clk_init_data init;
146 if (!name || !parent_name)
147 return ERR_PTR(-EINVAL);
149 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
151 return ERR_PTR(-ENOMEM);
154 init.ops = &main_osc_ops;
155 init.parent_names = &parent_name;
156 init.num_parents = 1;
157 init.flags = CLK_IGNORE_UNUSED;
159 osc->hw.init = &init;
160 osc->regmap = regmap;
163 regmap_update_bits(regmap,
164 AT91_CKGR_MOR, MOR_KEY_MASK |
166 AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
169 ret = clk_hw_register(NULL, &osc->hw);
178 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
181 const char *name = np->name;
182 const char *parent_name;
183 struct regmap *regmap;
186 of_property_read_string(np, "clock-output-names", &name);
187 bypass = of_property_read_bool(np, "atmel,osc-bypass");
188 parent_name = of_clk_get_parent_name(np, 0);
190 regmap = syscon_node_to_regmap(of_get_parent(np));
194 hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
198 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
200 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
201 of_at91rm9200_clk_main_osc_setup);
203 static bool clk_main_rc_osc_ready(struct regmap *regmap)
207 regmap_read(regmap, AT91_PMC_SR, &status);
209 return status & AT91_PMC_MOSCRCS;
212 static int clk_main_rc_osc_prepare(struct clk_hw *hw)
214 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
215 struct regmap *regmap = osc->regmap;
218 regmap_read(regmap, AT91_CKGR_MOR, &mor);
220 if (!(mor & AT91_PMC_MOSCRCEN))
221 regmap_update_bits(regmap, AT91_CKGR_MOR,
222 MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
223 AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
225 while (!clk_main_rc_osc_ready(regmap))
231 static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
233 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
234 struct regmap *regmap = osc->regmap;
237 regmap_read(regmap, AT91_CKGR_MOR, &mor);
239 if (!(mor & AT91_PMC_MOSCRCEN))
242 regmap_update_bits(regmap, AT91_CKGR_MOR,
243 MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
246 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
248 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
249 struct regmap *regmap = osc->regmap;
250 unsigned int mor, status;
252 regmap_read(regmap, AT91_CKGR_MOR, &mor);
253 regmap_read(regmap, AT91_PMC_SR, &status);
255 return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
258 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
259 unsigned long parent_rate)
261 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
263 return osc->frequency;
266 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
267 unsigned long parent_acc)
269 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
271 return osc->accuracy;
274 static const struct clk_ops main_rc_osc_ops = {
275 .prepare = clk_main_rc_osc_prepare,
276 .unprepare = clk_main_rc_osc_unprepare,
277 .is_prepared = clk_main_rc_osc_is_prepared,
278 .recalc_rate = clk_main_rc_osc_recalc_rate,
279 .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
282 static struct clk_hw * __init
283 at91_clk_register_main_rc_osc(struct regmap *regmap,
285 u32 frequency, u32 accuracy)
287 struct clk_main_rc_osc *osc;
288 struct clk_init_data init;
292 if (!name || !frequency)
293 return ERR_PTR(-EINVAL);
295 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
297 return ERR_PTR(-ENOMEM);
300 init.ops = &main_rc_osc_ops;
301 init.parent_names = NULL;
302 init.num_parents = 0;
303 init.flags = CLK_IGNORE_UNUSED;
305 osc->hw.init = &init;
306 osc->regmap = regmap;
307 osc->frequency = frequency;
308 osc->accuracy = accuracy;
311 ret = clk_hw_register(NULL, hw);
320 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
325 const char *name = np->name;
326 struct regmap *regmap;
328 of_property_read_string(np, "clock-output-names", &name);
329 of_property_read_u32(np, "clock-frequency", &frequency);
330 of_property_read_u32(np, "clock-accuracy", &accuracy);
332 regmap = syscon_node_to_regmap(of_get_parent(np));
336 hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
340 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
342 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
343 of_at91sam9x5_clk_main_rc_osc_setup);
346 static int clk_main_probe_frequency(struct regmap *regmap)
348 unsigned long prep_time, timeout;
351 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
354 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
355 if (mcfr & AT91_PMC_MAINRDY)
357 if (system_state < SYSTEM_RUNNING)
358 udelay(MAINF_LOOP_MIN_WAIT);
360 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
361 } while (time_before(prep_time, timeout));
366 static unsigned long clk_main_recalc_rate(struct regmap *regmap,
367 unsigned long parent_rate)
374 pr_warn("Main crystal frequency not set, using approximate value\n");
375 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
376 if (!(mcfr & AT91_PMC_MAINRDY))
379 return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
382 static int clk_rm9200_main_prepare(struct clk_hw *hw)
384 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
386 return clk_main_probe_frequency(clkmain->regmap);
389 static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
391 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
394 regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
396 return status & AT91_PMC_MAINRDY ? 1 : 0;
399 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
400 unsigned long parent_rate)
402 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
404 return clk_main_recalc_rate(clkmain->regmap, parent_rate);
407 static const struct clk_ops rm9200_main_ops = {
408 .prepare = clk_rm9200_main_prepare,
409 .is_prepared = clk_rm9200_main_is_prepared,
410 .recalc_rate = clk_rm9200_main_recalc_rate,
413 static struct clk_hw * __init
414 at91_clk_register_rm9200_main(struct regmap *regmap,
416 const char *parent_name)
418 struct clk_rm9200_main *clkmain;
419 struct clk_init_data init;
424 return ERR_PTR(-EINVAL);
427 return ERR_PTR(-EINVAL);
429 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
431 return ERR_PTR(-ENOMEM);
434 init.ops = &rm9200_main_ops;
435 init.parent_names = &parent_name;
436 init.num_parents = 1;
439 clkmain->hw.init = &init;
440 clkmain->regmap = regmap;
443 ret = clk_hw_register(NULL, &clkmain->hw);
452 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
455 const char *parent_name;
456 const char *name = np->name;
457 struct regmap *regmap;
459 parent_name = of_clk_get_parent_name(np, 0);
460 of_property_read_string(np, "clock-output-names", &name);
462 regmap = syscon_node_to_regmap(of_get_parent(np));
466 hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
470 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
472 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
473 of_at91rm9200_clk_main_setup);
475 static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
479 regmap_read(regmap, AT91_PMC_SR, &status);
481 return status & AT91_PMC_MOSCSELS ? 1 : 0;
484 static int clk_sam9x5_main_prepare(struct clk_hw *hw)
486 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
487 struct regmap *regmap = clkmain->regmap;
489 while (!clk_sam9x5_main_ready(regmap))
492 return clk_main_probe_frequency(regmap);
495 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
497 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
499 return clk_sam9x5_main_ready(clkmain->regmap);
502 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
503 unsigned long parent_rate)
505 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
507 return clk_main_recalc_rate(clkmain->regmap, parent_rate);
510 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
512 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
513 struct regmap *regmap = clkmain->regmap;
519 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
521 if (index && !(tmp & AT91_PMC_MOSCSEL))
522 tmp = AT91_PMC_MOSCSEL;
523 else if (!index && (tmp & AT91_PMC_MOSCSEL))
528 regmap_update_bits(regmap, AT91_CKGR_MOR,
529 AT91_PMC_MOSCSEL | MOR_KEY_MASK,
532 while (!clk_sam9x5_main_ready(regmap))
538 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
540 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
543 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
545 return clk_main_parent_select(status);
548 static const struct clk_ops sam9x5_main_ops = {
549 .prepare = clk_sam9x5_main_prepare,
550 .is_prepared = clk_sam9x5_main_is_prepared,
551 .recalc_rate = clk_sam9x5_main_recalc_rate,
552 .set_parent = clk_sam9x5_main_set_parent,
553 .get_parent = clk_sam9x5_main_get_parent,
556 static struct clk_hw * __init
557 at91_clk_register_sam9x5_main(struct regmap *regmap,
559 const char **parent_names,
562 struct clk_sam9x5_main *clkmain;
563 struct clk_init_data init;
569 return ERR_PTR(-EINVAL);
571 if (!parent_names || !num_parents)
572 return ERR_PTR(-EINVAL);
574 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
576 return ERR_PTR(-ENOMEM);
579 init.ops = &sam9x5_main_ops;
580 init.parent_names = parent_names;
581 init.num_parents = num_parents;
582 init.flags = CLK_SET_PARENT_GATE;
584 clkmain->hw.init = &init;
585 clkmain->regmap = regmap;
586 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
587 clkmain->parent = clk_main_parent_select(status);
590 ret = clk_hw_register(NULL, &clkmain->hw);
599 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
602 const char *parent_names[2];
603 unsigned int num_parents;
604 const char *name = np->name;
605 struct regmap *regmap;
607 num_parents = of_clk_get_parent_count(np);
608 if (num_parents == 0 || num_parents > 2)
611 of_clk_parent_fill(np, parent_names, num_parents);
612 regmap = syscon_node_to_regmap(of_get_parent(np));
616 of_property_read_string(np, "clock-output-names", &name);
618 hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
623 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
625 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
626 of_at91sam9x5_clk_main_setup);