2 * Copyright (C) 2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 * DESCRIPTION: The Broadcom iProc RNG200 Driver
17 #include <linux/hw_random.h>
18 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
28 #define RNG_CTRL_OFFSET 0x00
29 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
30 #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
31 #define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000
33 #define RNG_SOFT_RESET_OFFSET 0x04
34 #define RNG_SOFT_RESET 0x00000001
36 #define RBG_SOFT_RESET_OFFSET 0x08
37 #define RBG_SOFT_RESET 0x00000001
39 #define RNG_INT_STATUS_OFFSET 0x18
40 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
41 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
42 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
43 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
45 #define RNG_FIFO_DATA_OFFSET 0x20
47 #define RNG_FIFO_COUNT_OFFSET 0x24
48 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
50 struct iproc_rng200_dev {
55 #define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng)
57 static void iproc_rng200_restart(void __iomem *rng_base)
62 val = ioread32(rng_base + RNG_CTRL_OFFSET);
63 val &= ~RNG_CTRL_RNG_RBGEN_MASK;
64 val |= RNG_CTRL_RNG_RBGEN_DISABLE;
65 iowrite32(val, rng_base + RNG_CTRL_OFFSET);
67 /* Clear all interrupt status */
68 iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
70 /* Reset RNG and RBG */
71 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
72 val |= RBG_SOFT_RESET;
73 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
75 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
76 val |= RNG_SOFT_RESET;
77 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
79 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
80 val &= ~RNG_SOFT_RESET;
81 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
83 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
84 val &= ~RBG_SOFT_RESET;
85 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
88 val = ioread32(rng_base + RNG_CTRL_OFFSET);
89 val &= ~RNG_CTRL_RNG_RBGEN_MASK;
90 val |= RNG_CTRL_RNG_RBGEN_ENABLE;
91 iowrite32(val, rng_base + RNG_CTRL_OFFSET);
94 static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
97 struct iproc_rng200_dev *priv = to_rng_priv(rng);
98 uint32_t num_remaining = max;
101 #define MAX_RESETS_PER_READ 1
102 uint32_t num_resets = 0;
104 #define MAX_IDLE_TIME (1 * HZ)
105 unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
107 while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
109 /* Is RNG sane? If not, reset it. */
110 status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
111 if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
112 RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
114 if (num_resets >= MAX_RESETS_PER_READ)
115 return max - num_remaining;
117 iproc_rng200_restart(priv->base);
121 /* Are there any random numbers available? */
122 if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
123 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
125 if (num_remaining >= sizeof(uint32_t)) {
126 /* Buffer has room to store entire word */
127 *(uint32_t *)buf = ioread32(priv->base +
128 RNG_FIFO_DATA_OFFSET);
129 buf += sizeof(uint32_t);
130 num_remaining -= sizeof(uint32_t);
132 /* Buffer can only store partial word */
133 uint32_t rnd_number = ioread32(priv->base +
134 RNG_FIFO_DATA_OFFSET);
135 memcpy(buf, &rnd_number, num_remaining);
136 buf += num_remaining;
140 /* Reset the IDLE timeout */
141 idle_endtime = jiffies + MAX_IDLE_TIME;
144 /* Cannot wait, return immediately */
145 return max - num_remaining;
147 /* Can wait, give others chance to run */
148 usleep_range(min(num_remaining * 10, 500U), 500);
152 return max - num_remaining;
155 static int iproc_rng200_init(struct hwrng *rng)
157 struct iproc_rng200_dev *priv = to_rng_priv(rng);
161 val = ioread32(priv->base + RNG_CTRL_OFFSET);
162 val &= ~RNG_CTRL_RNG_RBGEN_MASK;
163 val |= RNG_CTRL_RNG_RBGEN_ENABLE;
164 iowrite32(val, priv->base + RNG_CTRL_OFFSET);
169 static void iproc_rng200_cleanup(struct hwrng *rng)
171 struct iproc_rng200_dev *priv = to_rng_priv(rng);
174 /* Disable RNG hardware */
175 val = ioread32(priv->base + RNG_CTRL_OFFSET);
176 val &= ~RNG_CTRL_RNG_RBGEN_MASK;
177 val |= RNG_CTRL_RNG_RBGEN_DISABLE;
178 iowrite32(val, priv->base + RNG_CTRL_OFFSET);
181 static int iproc_rng200_probe(struct platform_device *pdev)
183 struct iproc_rng200_dev *priv;
184 struct device *dev = &pdev->dev;
187 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
192 priv->base = devm_platform_ioremap_resource(pdev, 0);
193 if (IS_ERR(priv->base)) {
194 dev_err(dev, "failed to remap rng regs\n");
195 return PTR_ERR(priv->base);
198 dev_set_drvdata(dev, priv);
200 priv->rng.name = "iproc-rng200";
201 priv->rng.read = iproc_rng200_read;
202 priv->rng.init = iproc_rng200_init;
203 priv->rng.cleanup = iproc_rng200_cleanup;
205 /* Register driver */
206 ret = devm_hwrng_register(dev, &priv->rng);
208 dev_err(dev, "hwrng registration failed\n");
212 dev_info(dev, "hwrng registered\n");
217 static int __maybe_unused iproc_rng200_suspend(struct device *dev)
219 struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
221 iproc_rng200_cleanup(&priv->rng);
226 static int __maybe_unused iproc_rng200_resume(struct device *dev)
228 struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
230 iproc_rng200_init(&priv->rng);
235 static const struct dev_pm_ops iproc_rng200_pm_ops = {
236 SET_SYSTEM_SLEEP_PM_OPS(iproc_rng200_suspend, iproc_rng200_resume)
239 static const struct of_device_id iproc_rng200_of_match[] = {
240 { .compatible = "brcm,bcm2711-rng200", },
241 { .compatible = "brcm,bcm7211-rng200", },
242 { .compatible = "brcm,bcm7278-rng200", },
243 { .compatible = "brcm,iproc-rng200", },
246 MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
248 static struct platform_driver iproc_rng200_driver = {
250 .name = "iproc-rng200",
251 .of_match_table = iproc_rng200_of_match,
252 .pm = &iproc_rng200_pm_ops,
254 .probe = iproc_rng200_probe,
256 module_platform_driver(iproc_rng200_driver);
258 MODULE_AUTHOR("Broadcom");
259 MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
260 MODULE_LICENSE("GPL v2");