2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/kernel.h>
21 #include <linux/pagemap.h>
22 #include <linux/agp_backend.h>
23 #include <linux/delay.h>
26 #include "intel-agp.h"
27 #include <drm/intel-gtt.h>
30 * If we have Intel graphics, we're not going to have anything other than
31 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
32 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
33 * Only newer chipsets need to bother with this, of course.
35 #ifdef CONFIG_INTEL_IOMMU
36 #define USE_PCI_DMA_API 1
38 #define USE_PCI_DMA_API 0
41 struct intel_gtt_driver {
43 unsigned int is_g33 : 1;
44 unsigned int is_pineview : 1;
45 unsigned int is_ironlake : 1;
46 unsigned int has_pgtbl_enable : 1;
47 unsigned int dma_mask_size : 8;
48 /* Chipset specific GTT setup */
50 /* This should undo anything done in ->setup() save the unmapping
51 * of the mmio register file, that's done in the generic code. */
52 void (*cleanup)(void);
53 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
54 /* Flags is a more or less chipset specific opaque value.
55 * For chipsets that need to support old ums (non-gem) code, this
56 * needs to be identical to the various supported agp memory types! */
57 bool (*check_flags)(unsigned int flags);
58 void (*chipset_flush)(void);
61 static struct _intel_private {
62 const struct intel_gtt_driver *driver;
63 struct pci_dev *pcidev; /* device one */
64 struct pci_dev *bridge_dev;
65 u8 __iomem *registers;
66 phys_addr_t gtt_phys_addr;
68 u32 __iomem *gtt; /* I915G */
69 bool clear_fake_agp; /* on first access via agp, fill with scratch */
70 int num_dcache_entries;
71 void __iomem *i9xx_flush_page;
73 struct resource ifp_resource;
75 struct page *scratch_page;
76 phys_addr_t scratch_page_dma;
78 /* Whether i915 needs to use the dmar apis or not. */
79 unsigned int needs_dmar : 1;
80 phys_addr_t gma_bus_addr;
81 /* Size of memory reserved for graphics by the BIOS */
82 unsigned int stolen_size;
83 /* Total number of gtt entries. */
84 unsigned int gtt_total_entries;
85 /* Part of the gtt that is mappable by the cpu, for those chips where
86 * this is not the full gtt. */
87 unsigned int gtt_mappable_entries;
90 #define INTEL_GTT_GEN intel_private.driver->gen
91 #define IS_G33 intel_private.driver->is_g33
92 #define IS_PINEVIEW intel_private.driver->is_pineview
93 #define IS_IRONLAKE intel_private.driver->is_ironlake
94 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
96 #if IS_ENABLED(CONFIG_AGP_INTEL)
97 static int intel_gtt_map_memory(struct page **pages,
98 unsigned int num_entries,
101 struct scatterlist *sg;
104 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
106 if (sg_alloc_table(st, num_entries, GFP_KERNEL))
109 for_each_sg(st->sgl, sg, num_entries, i)
110 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
112 if (!pci_map_sg(intel_private.pcidev,
113 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
123 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
126 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
128 pci_unmap_sg(intel_private.pcidev, sg_list,
129 num_sg, PCI_DMA_BIDIRECTIONAL);
132 st.orig_nents = st.nents = num_sg;
137 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
142 /* Exists to support ARGB cursors */
143 static struct page *i8xx_alloc_pages(void)
147 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
151 if (set_pages_uc(page, 4) < 0) {
152 set_pages_wb(page, 4);
153 __free_pages(page, 2);
156 atomic_inc(&agp_bridge->current_memory_agp);
160 static void i8xx_destroy_pages(struct page *page)
165 set_pages_wb(page, 4);
166 __free_pages(page, 2);
167 atomic_dec(&agp_bridge->current_memory_agp);
171 #define I810_GTT_ORDER 4
172 static int i810_setup(void)
174 phys_addr_t reg_addr;
177 /* i81x does not preallocate the gtt. It's always 64kb in size. */
178 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
179 if (gtt_table == NULL)
181 intel_private.i81x_gtt_table = gtt_table;
183 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
185 intel_private.registers = ioremap(reg_addr, KB(64));
186 if (!intel_private.registers)
189 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
190 intel_private.registers+I810_PGETBL_CTL);
192 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
194 if ((readl(intel_private.registers+I810_DRAM_CTL)
195 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
196 dev_info(&intel_private.pcidev->dev,
197 "detected 4MB dedicated video ram\n");
198 intel_private.num_dcache_entries = 1024;
204 static void i810_cleanup(void)
206 writel(0, intel_private.registers+I810_PGETBL_CTL);
207 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
210 #if IS_ENABLED(CONFIG_AGP_INTEL)
211 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
216 if ((pg_start + mem->page_count)
217 > intel_private.num_dcache_entries)
220 if (!mem->is_flushed)
221 global_cache_flush();
223 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
224 dma_addr_t addr = i << PAGE_SHIFT;
225 intel_private.driver->write_entry(addr,
234 * The i810/i830 requires a physical address to program its mouse
235 * pointer into hardware.
236 * However the Xserver still writes to it through the agp aperture.
238 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
240 struct agp_memory *new;
244 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
247 /* kludge to get 4 physical pages for ARGB cursor */
248 page = i8xx_alloc_pages();
257 new = agp_create_memory(pg_count);
261 new->pages[0] = page;
263 /* kludge to get 4 physical pages for ARGB cursor */
264 new->pages[1] = new->pages[0] + 1;
265 new->pages[2] = new->pages[1] + 1;
266 new->pages[3] = new->pages[2] + 1;
268 new->page_count = pg_count;
269 new->num_scratch_pages = pg_count;
270 new->type = AGP_PHYS_MEMORY;
271 new->physical = page_to_phys(new->pages[0]);
275 static void intel_i810_free_by_type(struct agp_memory *curr)
277 agp_free_key(curr->key);
278 if (curr->type == AGP_PHYS_MEMORY) {
279 if (curr->page_count == 4)
280 i8xx_destroy_pages(curr->pages[0]);
282 agp_bridge->driver->agp_destroy_page(curr->pages[0],
283 AGP_PAGE_DESTROY_UNMAP);
284 agp_bridge->driver->agp_destroy_page(curr->pages[0],
285 AGP_PAGE_DESTROY_FREE);
287 agp_free_page_array(curr);
293 static int intel_gtt_setup_scratch_page(void)
298 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
301 set_pages_uc(page, 1);
303 if (intel_private.needs_dmar) {
304 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
305 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
306 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) {
311 intel_private.scratch_page_dma = dma_addr;
313 intel_private.scratch_page_dma = page_to_phys(page);
315 intel_private.scratch_page = page;
320 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
323 u32 pte_flags = I810_PTE_VALID;
326 case AGP_DCACHE_MEMORY:
327 pte_flags |= I810_PTE_LOCAL;
329 case AGP_USER_CACHED_MEMORY:
330 pte_flags |= I830_PTE_SYSTEM_CACHED;
334 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
337 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
345 static unsigned int intel_gtt_stolen_size(void)
350 static const int ddt[4] = { 0, 16, 32, 64 };
351 unsigned int stolen_size = 0;
353 if (INTEL_GTT_GEN == 1)
354 return 0; /* no stolen mem on i81x */
356 pci_read_config_word(intel_private.bridge_dev,
357 I830_GMCH_CTRL, &gmch_ctrl);
359 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
360 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
361 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
362 case I830_GMCH_GMS_STOLEN_512:
363 stolen_size = KB(512);
365 case I830_GMCH_GMS_STOLEN_1024:
368 case I830_GMCH_GMS_STOLEN_8192:
371 case I830_GMCH_GMS_LOCAL:
372 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
373 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
374 MB(ddt[I830_RDRAM_DDT(rdct)]);
382 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
383 case I855_GMCH_GMS_STOLEN_1M:
386 case I855_GMCH_GMS_STOLEN_4M:
389 case I855_GMCH_GMS_STOLEN_8M:
392 case I855_GMCH_GMS_STOLEN_16M:
393 stolen_size = MB(16);
395 case I855_GMCH_GMS_STOLEN_32M:
396 stolen_size = MB(32);
398 case I915_GMCH_GMS_STOLEN_48M:
399 stolen_size = MB(48);
401 case I915_GMCH_GMS_STOLEN_64M:
402 stolen_size = MB(64);
404 case G33_GMCH_GMS_STOLEN_128M:
405 stolen_size = MB(128);
407 case G33_GMCH_GMS_STOLEN_256M:
408 stolen_size = MB(256);
410 case INTEL_GMCH_GMS_STOLEN_96M:
411 stolen_size = MB(96);
413 case INTEL_GMCH_GMS_STOLEN_160M:
414 stolen_size = MB(160);
416 case INTEL_GMCH_GMS_STOLEN_224M:
417 stolen_size = MB(224);
419 case INTEL_GMCH_GMS_STOLEN_352M:
420 stolen_size = MB(352);
428 if (stolen_size > 0) {
429 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
430 stolen_size / KB(1), local ? "local" : "stolen");
432 dev_info(&intel_private.bridge_dev->dev,
433 "no pre-allocated video memory detected\n");
440 static void i965_adjust_pgetbl_size(unsigned int size_flag)
442 u32 pgetbl_ctl, pgetbl_ctl2;
444 /* ensure that ppgtt is disabled */
445 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
446 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
447 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
449 /* write the new ggtt size */
450 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
451 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
452 pgetbl_ctl |= size_flag;
453 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
456 static unsigned int i965_gtt_total_entries(void)
462 pci_read_config_word(intel_private.bridge_dev,
463 I830_GMCH_CTRL, &gmch_ctl);
465 if (INTEL_GTT_GEN == 5) {
466 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
467 case G4x_GMCH_SIZE_1M:
468 case G4x_GMCH_SIZE_VT_1M:
469 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
471 case G4x_GMCH_SIZE_VT_1_5M:
472 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
474 case G4x_GMCH_SIZE_2M:
475 case G4x_GMCH_SIZE_VT_2M:
476 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
481 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
483 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
484 case I965_PGETBL_SIZE_128KB:
487 case I965_PGETBL_SIZE_256KB:
490 case I965_PGETBL_SIZE_512KB:
493 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
494 case I965_PGETBL_SIZE_1MB:
497 case I965_PGETBL_SIZE_2MB:
500 case I965_PGETBL_SIZE_1_5MB:
501 size = KB(1024 + 512);
504 dev_info(&intel_private.pcidev->dev,
505 "unknown page table size, assuming 512KB\n");
512 static unsigned int intel_gtt_total_entries(void)
514 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
515 return i965_gtt_total_entries();
517 /* On previous hardware, the GTT size was just what was
518 * required to map the aperture.
520 return intel_private.gtt_mappable_entries;
524 static unsigned int intel_gtt_mappable_entries(void)
526 unsigned int aperture_size;
528 if (INTEL_GTT_GEN == 1) {
531 pci_read_config_dword(intel_private.bridge_dev,
532 I810_SMRAM_MISCC, &smram_miscc);
534 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
535 == I810_GFX_MEM_WIN_32M)
536 aperture_size = MB(32);
538 aperture_size = MB(64);
539 } else if (INTEL_GTT_GEN == 2) {
542 pci_read_config_word(intel_private.bridge_dev,
543 I830_GMCH_CTRL, &gmch_ctrl);
545 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
546 aperture_size = MB(64);
548 aperture_size = MB(128);
550 /* 9xx supports large sizes, just look at the length */
551 aperture_size = pci_resource_len(intel_private.pcidev, 2);
554 return aperture_size >> PAGE_SHIFT;
557 static void intel_gtt_teardown_scratch_page(void)
559 set_pages_wb(intel_private.scratch_page, 1);
560 if (intel_private.needs_dmar)
561 pci_unmap_page(intel_private.pcidev,
562 intel_private.scratch_page_dma,
563 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
564 __free_page(intel_private.scratch_page);
567 static void intel_gtt_cleanup(void)
569 intel_private.driver->cleanup();
571 iounmap(intel_private.gtt);
572 iounmap(intel_private.registers);
574 intel_gtt_teardown_scratch_page();
577 /* Certain Gen5 chipsets require require idling the GPU before
578 * unmapping anything from the GTT when VT-d is enabled.
580 static inline int needs_ilk_vtd_wa(void)
582 #ifdef CONFIG_INTEL_IOMMU
583 const unsigned short gpu_devid = intel_private.pcidev->device;
585 /* Query intel_iommu to see if we need the workaround. Presumably that
588 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||
589 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
590 intel_iommu_gfx_mapped)
596 static bool intel_gtt_can_wc(void)
598 if (INTEL_GTT_GEN <= 2)
601 if (INTEL_GTT_GEN >= 6)
604 /* Reports of major corruption with ILK vt'd enabled */
605 if (needs_ilk_vtd_wa())
611 static int intel_gtt_init(void)
616 ret = intel_private.driver->setup();
620 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
621 intel_private.gtt_total_entries = intel_gtt_total_entries();
623 /* save the PGETBL reg for resume */
624 intel_private.PGETBL_save =
625 readl(intel_private.registers+I810_PGETBL_CTL)
626 & ~I810_PGETBL_ENABLED;
627 /* we only ever restore the register when enabling the PGTBL... */
629 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
631 dev_info(&intel_private.bridge_dev->dev,
632 "detected gtt size: %dK total, %dK mappable\n",
633 intel_private.gtt_total_entries * 4,
634 intel_private.gtt_mappable_entries * 4);
636 gtt_map_size = intel_private.gtt_total_entries * 4;
638 intel_private.gtt = NULL;
639 if (intel_gtt_can_wc())
640 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
642 if (intel_private.gtt == NULL)
643 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
645 if (intel_private.gtt == NULL) {
646 intel_private.driver->cleanup();
647 iounmap(intel_private.registers);
651 #if IS_ENABLED(CONFIG_AGP_INTEL)
652 global_cache_flush(); /* FIXME: ? */
655 intel_private.stolen_size = intel_gtt_stolen_size();
657 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
659 ret = intel_gtt_setup_scratch_page();
665 if (INTEL_GTT_GEN <= 2)
666 bar = I810_GMADR_BAR;
668 bar = I915_GMADR_BAR;
670 intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
674 #if IS_ENABLED(CONFIG_AGP_INTEL)
675 static int intel_fake_agp_fetch_size(void)
677 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
678 unsigned int aper_size;
681 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
683 for (i = 0; i < num_sizes; i++) {
684 if (aper_size == intel_fake_agp_sizes[i].size) {
685 agp_bridge->current_size =
686 (void *) (intel_fake_agp_sizes + i);
695 static void i830_cleanup(void)
699 /* The chipset_flush interface needs to get data that has already been
700 * flushed out of the CPU all the way out to main memory, because the GPU
701 * doesn't snoop those buffers.
703 * The 8xx series doesn't have the same lovely interface for flushing the
704 * chipset write buffers that the later chips do. According to the 865
705 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
706 * that buffer out, we just fill 1KB and clflush it out, on the assumption
707 * that it'll push whatever was in there out. It appears to work.
709 static void i830_chipset_flush(void)
711 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
713 /* Forcibly evict everything from the CPU write buffers.
714 * clflush appears to be insufficient.
716 wbinvd_on_all_cpus();
718 /* Now we've only seen documents for this magic bit on 855GM,
719 * we hope it exists for the other gen2 chipsets...
721 * Also works as advertised on my 845G.
723 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
724 intel_private.registers+I830_HIC);
726 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
727 if (time_after(jiffies, timeout))
734 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
737 u32 pte_flags = I810_PTE_VALID;
739 if (flags == AGP_USER_CACHED_MEMORY)
740 pte_flags |= I830_PTE_SYSTEM_CACHED;
742 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
745 bool intel_enable_gtt(void)
749 if (INTEL_GTT_GEN == 2) {
752 pci_read_config_word(intel_private.bridge_dev,
753 I830_GMCH_CTRL, &gmch_ctrl);
754 gmch_ctrl |= I830_GMCH_ENABLED;
755 pci_write_config_word(intel_private.bridge_dev,
756 I830_GMCH_CTRL, gmch_ctrl);
758 pci_read_config_word(intel_private.bridge_dev,
759 I830_GMCH_CTRL, &gmch_ctrl);
760 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
761 dev_err(&intel_private.pcidev->dev,
762 "failed to enable the GTT: GMCH_CTRL=%x\n",
768 /* On the resume path we may be adjusting the PGTBL value, so
769 * be paranoid and flush all chipset write buffers...
771 if (INTEL_GTT_GEN >= 3)
772 writel(0, intel_private.registers+GFX_FLSH_CNTL);
774 reg = intel_private.registers+I810_PGETBL_CTL;
775 writel(intel_private.PGETBL_save, reg);
776 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
777 dev_err(&intel_private.pcidev->dev,
778 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
779 readl(reg), intel_private.PGETBL_save);
783 if (INTEL_GTT_GEN >= 3)
784 writel(0, intel_private.registers+GFX_FLSH_CNTL);
788 EXPORT_SYMBOL(intel_enable_gtt);
790 static int i830_setup(void)
792 phys_addr_t reg_addr;
794 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
796 intel_private.registers = ioremap(reg_addr, KB(64));
797 if (!intel_private.registers)
800 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
805 #if IS_ENABLED(CONFIG_AGP_INTEL)
806 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
808 agp_bridge->gatt_table_real = NULL;
809 agp_bridge->gatt_table = NULL;
810 agp_bridge->gatt_bus_addr = 0;
815 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
820 static int intel_fake_agp_configure(void)
822 if (!intel_enable_gtt())
825 intel_private.clear_fake_agp = true;
826 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
832 static bool i830_check_flags(unsigned int flags)
836 case AGP_PHYS_MEMORY:
837 case AGP_USER_CACHED_MEMORY:
838 case AGP_USER_MEMORY:
845 void intel_gtt_insert_page(dma_addr_t addr,
849 intel_private.driver->write_entry(addr, pg, flags);
850 readl(intel_private.gtt + pg);
851 if (intel_private.driver->chipset_flush)
852 intel_private.driver->chipset_flush();
854 EXPORT_SYMBOL(intel_gtt_insert_page);
856 void intel_gtt_insert_sg_entries(struct sg_table *st,
857 unsigned int pg_start,
860 struct scatterlist *sg;
866 /* sg may merge pages, but we have to separate
867 * per-page addr for GTT */
868 for_each_sg(st->sgl, sg, st->nents, i) {
869 len = sg_dma_len(sg) >> PAGE_SHIFT;
870 for (m = 0; m < len; m++) {
871 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
872 intel_private.driver->write_entry(addr, j, flags);
876 readl(intel_private.gtt + j - 1);
877 if (intel_private.driver->chipset_flush)
878 intel_private.driver->chipset_flush();
880 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
882 #if IS_ENABLED(CONFIG_AGP_INTEL)
883 static void intel_gtt_insert_pages(unsigned int first_entry,
884 unsigned int num_entries,
890 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
891 dma_addr_t addr = page_to_phys(pages[i]);
892 intel_private.driver->write_entry(addr,
898 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
899 off_t pg_start, int type)
903 if (intel_private.clear_fake_agp) {
904 int start = intel_private.stolen_size / PAGE_SIZE;
905 int end = intel_private.gtt_mappable_entries;
906 intel_gtt_clear_range(start, end - start);
907 intel_private.clear_fake_agp = false;
910 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
911 return i810_insert_dcache_entries(mem, pg_start, type);
913 if (mem->page_count == 0)
916 if (pg_start + mem->page_count > intel_private.gtt_total_entries)
919 if (type != mem->type)
922 if (!intel_private.driver->check_flags(type))
925 if (!mem->is_flushed)
926 global_cache_flush();
928 if (intel_private.needs_dmar) {
931 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
935 intel_gtt_insert_sg_entries(&st, pg_start, type);
936 mem->sg_list = st.sgl;
937 mem->num_sg = st.nents;
939 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
945 mem->is_flushed = true;
950 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
954 for (i = first_entry; i < (first_entry + num_entries); i++) {
955 intel_private.driver->write_entry(intel_private.scratch_page_dma,
960 EXPORT_SYMBOL(intel_gtt_clear_range);
962 #if IS_ENABLED(CONFIG_AGP_INTEL)
963 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
964 off_t pg_start, int type)
966 if (mem->page_count == 0)
969 intel_gtt_clear_range(pg_start, mem->page_count);
971 if (intel_private.needs_dmar) {
972 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
980 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
983 struct agp_memory *new;
985 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
986 if (pg_count != intel_private.num_dcache_entries)
989 new = agp_create_memory(1);
993 new->type = AGP_DCACHE_MEMORY;
994 new->page_count = pg_count;
995 new->num_scratch_pages = 0;
996 agp_free_page_array(new);
999 if (type == AGP_PHYS_MEMORY)
1000 return alloc_agpphysmem_i8xx(pg_count, type);
1001 /* always return NULL for other allocation types for now */
1006 static int intel_alloc_chipset_flush_resource(void)
1009 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1010 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1011 pcibios_align_resource, intel_private.bridge_dev);
1016 static void intel_i915_setup_chipset_flush(void)
1021 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1022 if (!(temp & 0x1)) {
1023 intel_alloc_chipset_flush_resource();
1024 intel_private.resource_valid = 1;
1025 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1029 intel_private.resource_valid = 1;
1030 intel_private.ifp_resource.start = temp;
1031 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1032 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1033 /* some BIOSes reserve this area in a pnp some don't */
1035 intel_private.resource_valid = 0;
1039 static void intel_i965_g33_setup_chipset_flush(void)
1041 u32 temp_hi, temp_lo;
1044 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1045 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1047 if (!(temp_lo & 0x1)) {
1049 intel_alloc_chipset_flush_resource();
1051 intel_private.resource_valid = 1;
1052 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1053 upper_32_bits(intel_private.ifp_resource.start));
1054 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1059 l64 = ((u64)temp_hi << 32) | temp_lo;
1061 intel_private.resource_valid = 1;
1062 intel_private.ifp_resource.start = l64;
1063 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1064 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1065 /* some BIOSes reserve this area in a pnp some don't */
1067 intel_private.resource_valid = 0;
1071 static void intel_i9xx_setup_flush(void)
1073 /* return if already configured */
1074 if (intel_private.ifp_resource.start)
1077 if (INTEL_GTT_GEN == 6)
1080 /* setup a resource for this object */
1081 intel_private.ifp_resource.name = "Intel Flush Page";
1082 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1084 /* Setup chipset flush for 915 */
1085 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1086 intel_i965_g33_setup_chipset_flush();
1088 intel_i915_setup_chipset_flush();
1091 if (intel_private.ifp_resource.start)
1092 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1093 if (!intel_private.i9xx_flush_page)
1094 dev_err(&intel_private.pcidev->dev,
1095 "can't ioremap flush page - no chipset flushing\n");
1098 static void i9xx_cleanup(void)
1100 if (intel_private.i9xx_flush_page)
1101 iounmap(intel_private.i9xx_flush_page);
1102 if (intel_private.resource_valid)
1103 release_resource(&intel_private.ifp_resource);
1104 intel_private.ifp_resource.start = 0;
1105 intel_private.resource_valid = 0;
1108 static void i9xx_chipset_flush(void)
1111 if (intel_private.i9xx_flush_page)
1112 writel(1, intel_private.i9xx_flush_page);
1115 static void i965_write_entry(dma_addr_t addr,
1121 pte_flags = I810_PTE_VALID;
1122 if (flags == AGP_USER_CACHED_MEMORY)
1123 pte_flags |= I830_PTE_SYSTEM_CACHED;
1125 /* Shift high bits down */
1126 addr |= (addr >> 28) & 0xf0;
1127 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1130 static int i9xx_setup(void)
1132 phys_addr_t reg_addr;
1135 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1137 intel_private.registers = ioremap(reg_addr, size);
1138 if (!intel_private.registers)
1141 switch (INTEL_GTT_GEN) {
1143 intel_private.gtt_phys_addr =
1144 pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1147 intel_private.gtt_phys_addr = reg_addr + MB(2);
1150 intel_private.gtt_phys_addr = reg_addr + KB(512);
1154 intel_i9xx_setup_flush();
1159 #if IS_ENABLED(CONFIG_AGP_INTEL)
1160 static const struct agp_bridge_driver intel_fake_agp_driver = {
1161 .owner = THIS_MODULE,
1162 .size_type = FIXED_APER_SIZE,
1163 .aperture_sizes = intel_fake_agp_sizes,
1164 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1165 .configure = intel_fake_agp_configure,
1166 .fetch_size = intel_fake_agp_fetch_size,
1167 .cleanup = intel_gtt_cleanup,
1168 .agp_enable = intel_fake_agp_enable,
1169 .cache_flush = global_cache_flush,
1170 .create_gatt_table = intel_fake_agp_create_gatt_table,
1171 .free_gatt_table = intel_fake_agp_free_gatt_table,
1172 .insert_memory = intel_fake_agp_insert_entries,
1173 .remove_memory = intel_fake_agp_remove_entries,
1174 .alloc_by_type = intel_fake_agp_alloc_by_type,
1175 .free_by_type = intel_i810_free_by_type,
1176 .agp_alloc_page = agp_generic_alloc_page,
1177 .agp_alloc_pages = agp_generic_alloc_pages,
1178 .agp_destroy_page = agp_generic_destroy_page,
1179 .agp_destroy_pages = agp_generic_destroy_pages,
1183 static const struct intel_gtt_driver i81x_gtt_driver = {
1185 .has_pgtbl_enable = 1,
1186 .dma_mask_size = 32,
1187 .setup = i810_setup,
1188 .cleanup = i810_cleanup,
1189 .check_flags = i830_check_flags,
1190 .write_entry = i810_write_entry,
1192 static const struct intel_gtt_driver i8xx_gtt_driver = {
1194 .has_pgtbl_enable = 1,
1195 .setup = i830_setup,
1196 .cleanup = i830_cleanup,
1197 .write_entry = i830_write_entry,
1198 .dma_mask_size = 32,
1199 .check_flags = i830_check_flags,
1200 .chipset_flush = i830_chipset_flush,
1202 static const struct intel_gtt_driver i915_gtt_driver = {
1204 .has_pgtbl_enable = 1,
1205 .setup = i9xx_setup,
1206 .cleanup = i9xx_cleanup,
1207 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1208 .write_entry = i830_write_entry,
1209 .dma_mask_size = 32,
1210 .check_flags = i830_check_flags,
1211 .chipset_flush = i9xx_chipset_flush,
1213 static const struct intel_gtt_driver g33_gtt_driver = {
1216 .setup = i9xx_setup,
1217 .cleanup = i9xx_cleanup,
1218 .write_entry = i965_write_entry,
1219 .dma_mask_size = 36,
1220 .check_flags = i830_check_flags,
1221 .chipset_flush = i9xx_chipset_flush,
1223 static const struct intel_gtt_driver pineview_gtt_driver = {
1225 .is_pineview = 1, .is_g33 = 1,
1226 .setup = i9xx_setup,
1227 .cleanup = i9xx_cleanup,
1228 .write_entry = i965_write_entry,
1229 .dma_mask_size = 36,
1230 .check_flags = i830_check_flags,
1231 .chipset_flush = i9xx_chipset_flush,
1233 static const struct intel_gtt_driver i965_gtt_driver = {
1235 .has_pgtbl_enable = 1,
1236 .setup = i9xx_setup,
1237 .cleanup = i9xx_cleanup,
1238 .write_entry = i965_write_entry,
1239 .dma_mask_size = 36,
1240 .check_flags = i830_check_flags,
1241 .chipset_flush = i9xx_chipset_flush,
1243 static const struct intel_gtt_driver g4x_gtt_driver = {
1245 .setup = i9xx_setup,
1246 .cleanup = i9xx_cleanup,
1247 .write_entry = i965_write_entry,
1248 .dma_mask_size = 36,
1249 .check_flags = i830_check_flags,
1250 .chipset_flush = i9xx_chipset_flush,
1252 static const struct intel_gtt_driver ironlake_gtt_driver = {
1255 .setup = i9xx_setup,
1256 .cleanup = i9xx_cleanup,
1257 .write_entry = i965_write_entry,
1258 .dma_mask_size = 36,
1259 .check_flags = i830_check_flags,
1260 .chipset_flush = i9xx_chipset_flush,
1263 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1264 * driver and gmch_driver must be non-null, and find_gmch will determine
1265 * which one should be used if a gmch_chip_id is present.
1267 static const struct intel_gtt_driver_description {
1268 unsigned int gmch_chip_id;
1270 const struct intel_gtt_driver *gtt_driver;
1271 } intel_gtt_chipsets[] = {
1272 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1274 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1276 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1278 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1280 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1282 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1284 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1286 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1288 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1290 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1292 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1294 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1296 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1298 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1300 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1302 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1304 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1306 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1308 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1310 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1312 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1314 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1316 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1318 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1320 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1321 &pineview_gtt_driver },
1322 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1323 &pineview_gtt_driver },
1324 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1326 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1328 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1330 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1332 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1334 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1336 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1338 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1339 "HD Graphics", &ironlake_gtt_driver },
1340 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1341 "HD Graphics", &ironlake_gtt_driver },
1345 static int find_gmch(u16 device)
1347 struct pci_dev *gmch_device;
1349 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1350 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1351 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1352 device, gmch_device);
1358 intel_private.pcidev = gmch_device;
1362 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1363 struct agp_bridge_data *bridge)
1367 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1369 if (gpu_pdev->device ==
1370 intel_gtt_chipsets[i].gmch_chip_id) {
1371 intel_private.pcidev = pci_dev_get(gpu_pdev);
1372 intel_private.driver =
1373 intel_gtt_chipsets[i].gtt_driver;
1377 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1378 intel_private.driver =
1379 intel_gtt_chipsets[i].gtt_driver;
1384 if (!intel_private.driver)
1387 #if IS_ENABLED(CONFIG_AGP_INTEL)
1389 if (INTEL_GTT_GEN > 1)
1392 bridge->driver = &intel_fake_agp_driver;
1393 bridge->dev_private_data = &intel_private;
1394 bridge->dev = bridge_pdev;
1400 * Can be called from the fake agp driver but also directly from
1401 * drm/i915.ko. Hence we need to check whether everything is set up
1404 if (intel_private.refcount++)
1407 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1409 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1411 mask = intel_private.driver->dma_mask_size;
1412 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1413 dev_err(&intel_private.pcidev->dev,
1414 "set gfx device dma mask %d-bit failed!\n", mask);
1416 pci_set_consistent_dma_mask(intel_private.pcidev,
1417 DMA_BIT_MASK(mask));
1419 if (intel_gtt_init() != 0) {
1420 intel_gmch_remove();
1427 EXPORT_SYMBOL(intel_gmch_probe);
1429 void intel_gtt_get(u64 *gtt_total, size_t *stolen_size,
1430 phys_addr_t *mappable_base, u64 *mappable_end)
1432 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1433 *stolen_size = intel_private.stolen_size;
1434 *mappable_base = intel_private.gma_bus_addr;
1435 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1437 EXPORT_SYMBOL(intel_gtt_get);
1439 void intel_gtt_chipset_flush(void)
1441 if (intel_private.driver->chipset_flush)
1442 intel_private.driver->chipset_flush();
1444 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1446 void intel_gmch_remove(void)
1448 if (--intel_private.refcount)
1451 if (intel_private.scratch_page)
1452 intel_gtt_teardown_scratch_page();
1453 if (intel_private.pcidev)
1454 pci_dev_put(intel_private.pcidev);
1455 if (intel_private.bridge_dev)
1456 pci_dev_put(intel_private.bridge_dev);
1457 intel_private.driver = NULL;
1459 EXPORT_SYMBOL(intel_gmch_remove);
1461 MODULE_AUTHOR("Dave Jones, Various @Intel");
1462 MODULE_LICENSE("GPL and additional rights");