drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pagemap.h>
  22 #include <linux/agp_backend.h>
  23 #include <linux/intel-iommu.h>
  24 #include <linux/delay.h>
  25 #include <asm/smp.h>
  26 #include "agp.h"
  27 #include "intel-agp.h"
  28 #include <drm/intel-gtt.h>
  29 #include <asm/set_memory.h>
  30
  31 /*
  32  * If we have Intel graphics, we're not going to have anything other than
  33  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  34  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
  35  * Only newer chipsets need to bother with this, of course.
  36  */
  37 #ifdef CONFIG_INTEL_IOMMU
  38 #define USE_PCI_DMA_API 1
  39 #else
  40 #define USE_PCI_DMA_API 0
  41 #endif
  42
  43 struct intel_gtt_driver {
  44         unsigned int gen : 8;
  45         unsigned int is_g33 : 1;
  46         unsigned int is_pineview : 1;
  47         unsigned int is_ironlake : 1;
  48         unsigned int has_pgtbl_enable : 1;
  49         unsigned int dma_mask_size : 8;
  50         /* Chipset specific GTT setup */
  51         int (*setup)(void);
  52         /* This should undo anything done in ->setup() save the unmapping
  53          * of the mmio register file, that's done in the generic code. */
  54         void (*cleanup)(void);
  55         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  56         /* Flags is a more or less chipset specific opaque value.
  57          * For chipsets that need to support old ums (non-gem) code, this
  58          * needs to be identical to the various supported agp memory types! */
  59         bool (*check_flags)(unsigned int flags);
  60         void (*chipset_flush)(void);
  61 };
  62
  63 static struct _intel_private {
  64         const struct intel_gtt_driver *driver;
  65         struct pci_dev *pcidev; /* device one */
  66         struct pci_dev *bridge_dev;
  67         u8 __iomem *registers;
  68         phys_addr_t gtt_phys_addr;
  69         u32 PGETBL_save;
  70         u32 __iomem *gtt;               /* I915G */
  71         bool clear_fake_agp; /* on first access via agp, fill with scratch */
  72         int num_dcache_entries;
  73         void __iomem *i9xx_flush_page;
  74         char *i81x_gtt_table;
  75         struct resource ifp_resource;
  76         int resource_valid;
  77         struct page *scratch_page;
  78         phys_addr_t scratch_page_dma;
  79         int refcount;
  80         /* Whether i915 needs to use the dmar apis or not. */
  81         unsigned int needs_dmar : 1;
  82         phys_addr_t gma_bus_addr;
  83         /*  Size of memory reserved for graphics by the BIOS */
  84         resource_size_t stolen_size;
  85         /* Total number of gtt entries. */
  86         unsigned int gtt_total_entries;
  87         /* Part of the gtt that is mappable by the cpu, for those chips where
  88          * this is not the full gtt. */
  89         unsigned int gtt_mappable_entries;
  90 } intel_private;
  91
  92 #define INTEL_GTT_GEN   intel_private.driver->gen
  93 #define IS_G33          intel_private.driver->is_g33
  94 #define IS_PINEVIEW     intel_private.driver->is_pineview
  95 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  96 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  97
  98 #if IS_ENABLED(CONFIG_AGP_INTEL)
  99 static int intel_gtt_map_memory(struct page **pages,
 100                                 unsigned int num_entries,
 101                                 struct sg_table *st)
 102 {
 103         struct scatterlist *sg;
 104         int i;
 105
 106         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
 107
 108         if (sg_alloc_table(st, num_entries, GFP_KERNEL))
 109                 goto err;
 110
 111         for_each_sg(st->sgl, sg, num_entries, i)
 112                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
 113
 114         if (!dma_map_sg(&intel_private.pcidev->dev, st->sgl, st->nents,
 115                         DMA_BIDIRECTIONAL))
 116                 goto err;
 117
 118         return 0;
 119
 120 err:
 121         sg_free_table(st);
 122         return -ENOMEM;
 123 }
 124
 125 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
 126 {
 127         struct sg_table st;
 128         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 129
 130         dma_unmap_sg(&intel_private.pcidev->dev, sg_list, num_sg,
 131                      DMA_BIDIRECTIONAL);
 132
 133         st.sgl = sg_list;
 134         st.orig_nents = st.nents = num_sg;
 135
 136         sg_free_table(&st);
 137 }
 138
 139 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 140 {
 141         return;
 142 }
 143
 144 /* Exists to support ARGB cursors */
 145 static struct page *i8xx_alloc_pages(void)
 146 {
 147         struct page *page;
 148
 149         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 150         if (page == NULL)
 151                 return NULL;
 152
 153         if (set_pages_uc(page, 4) < 0) {
 154                 set_pages_wb(page, 4);
 155                 __free_pages(page, 2);
 156                 return NULL;
 157         }
 158         atomic_inc(&agp_bridge->current_memory_agp);
 159         return page;
 160 }
 161
 162 static void i8xx_destroy_pages(struct page *page)
 163 {
 164         if (page == NULL)
 165                 return;
 166
 167         set_pages_wb(page, 4);
 168         __free_pages(page, 2);
 169         atomic_dec(&agp_bridge->current_memory_agp);
 170 }
 171 #endif
 172
 173 #define I810_GTT_ORDER 4
 174 static int i810_setup(void)
 175 {
 176         phys_addr_t reg_addr;
 177         char *gtt_table;
 178
 179         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 180         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 181         if (gtt_table == NULL)
 182                 return -ENOMEM;
 183         intel_private.i81x_gtt_table = gtt_table;
 184
 185         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 186
 187         intel_private.registers = ioremap(reg_addr, KB(64));
 188         if (!intel_private.registers)
 189                 return -ENOMEM;
 190
 191         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 192                intel_private.registers+I810_PGETBL_CTL);
 193
 194         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 195
 196         if ((readl(intel_private.registers+I810_DRAM_CTL)
 197                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 198                 dev_info(&intel_private.pcidev->dev,
 199                          "detected 4MB dedicated video ram\n");
 200                 intel_private.num_dcache_entries = 1024;
 201         }
 202
 203         return 0;
 204 }
 205
 206 static void i810_cleanup(void)
 207 {
 208         writel(0, intel_private.registers+I810_PGETBL_CTL);
 209         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 210 }
 211
 212 #if IS_ENABLED(CONFIG_AGP_INTEL)
 213 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 214                                       int type)
 215 {
 216         int i;
 217
 218         if ((pg_start + mem->page_count)
 219                         > intel_private.num_dcache_entries)
 220                 return -EINVAL;
 221
 222         if (!mem->is_flushed)
 223                 global_cache_flush();
 224
 225         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 226                 dma_addr_t addr = i << PAGE_SHIFT;
 227                 intel_private.driver->write_entry(addr,
 228                                                   i, type);
 229         }
 230         wmb();
 231
 232         return 0;
 233 }
 234
 235 /*
 236  * The i810/i830 requires a physical address to program its mouse
 237  * pointer into hardware.
 238  * However the Xserver still writes to it through the agp aperture.
 239  */
 240 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 241 {
 242         struct agp_memory *new;
 243         struct page *page;
 244
 245         switch (pg_count) {
 246         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 247                 break;
 248         case 4:
 249                 /* kludge to get 4 physical pages for ARGB cursor */
 250                 page = i8xx_alloc_pages();
 251                 break;
 252         default:
 253                 return NULL;
 254         }
 255
 256         if (page == NULL)
 257                 return NULL;
 258
 259         new = agp_create_memory(pg_count);
 260         if (new == NULL)
 261                 return NULL;
 262
 263         new->pages[0] = page;
 264         if (pg_count == 4) {
 265                 /* kludge to get 4 physical pages for ARGB cursor */
 266                 new->pages[1] = new->pages[0] + 1;
 267                 new->pages[2] = new->pages[1] + 1;
 268                 new->pages[3] = new->pages[2] + 1;
 269         }
 270         new->page_count = pg_count;
 271         new->num_scratch_pages = pg_count;
 272         new->type = AGP_PHYS_MEMORY;
 273         new->physical = page_to_phys(new->pages[0]);
 274         return new;
 275 }
 276
 277 static void intel_i810_free_by_type(struct agp_memory *curr)
 278 {
 279         agp_free_key(curr->key);
 280         if (curr->type == AGP_PHYS_MEMORY) {
 281                 if (curr->page_count == 4)
 282                         i8xx_destroy_pages(curr->pages[0]);
 283                 else {
 284                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 285                                                              AGP_PAGE_DESTROY_UNMAP);
 286                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 287                                                              AGP_PAGE_DESTROY_FREE);
 288                 }
 289                 agp_free_page_array(curr);
 290         }
 291         kfree(curr);
 292 }
 293 #endif
 294
 295 static int intel_gtt_setup_scratch_page(void)
 296 {
 297         struct page *page;
 298         dma_addr_t dma_addr;
 299
 300         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 301         if (page == NULL)
 302                 return -ENOMEM;
 303         set_pages_uc(page, 1);
 304
 305         if (intel_private.needs_dmar) {
 306                 dma_addr = dma_map_page(&intel_private.pcidev->dev, page, 0,
 307                                         PAGE_SIZE, DMA_BIDIRECTIONAL);
 308                 if (dma_mapping_error(&intel_private.pcidev->dev, dma_addr)) {
 309                         __free_page(page);
 310                         return -EINVAL;
 311                 }
 312
 313                 intel_private.scratch_page_dma = dma_addr;
 314         } else
 315                 intel_private.scratch_page_dma = page_to_phys(page);
 316
 317         intel_private.scratch_page = page;
 318
 319         return 0;
 320 }
 321
 322 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 323                              unsigned int flags)
 324 {
 325         u32 pte_flags = I810_PTE_VALID;
 326
 327         switch (flags) {
 328         case AGP_DCACHE_MEMORY:
 329                 pte_flags |= I810_PTE_LOCAL;
 330                 break;
 331         case AGP_USER_CACHED_MEMORY:
 332                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 333                 break;
 334         }
 335
 336         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 337 }
 338
 339 static resource_size_t intel_gtt_stolen_size(void)
 340 {
 341         u16 gmch_ctrl;
 342         u8 rdct;
 343         int local = 0;
 344         static const int ddt[4] = { 0, 16, 32, 64 };
 345         resource_size_t stolen_size = 0;
 346
 347         if (INTEL_GTT_GEN == 1)
 348                 return 0; /* no stolen mem on i81x */
 349
 350         pci_read_config_word(intel_private.bridge_dev,
 351                              I830_GMCH_CTRL, &gmch_ctrl);
 352
 353         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 354             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 355                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 356                 case I830_GMCH_GMS_STOLEN_512:
 357                         stolen_size = KB(512);
 358                         break;
 359                 case I830_GMCH_GMS_STOLEN_1024:
 360                         stolen_size = MB(1);
 361                         break;
 362                 case I830_GMCH_GMS_STOLEN_8192:
 363                         stolen_size = MB(8);
 364                         break;
 365                 case I830_GMCH_GMS_LOCAL:
 366                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 367                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 368                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 369                         local = 1;
 370                         break;
 371                 default:
 372                         stolen_size = 0;
 373                         break;
 374                 }
 375         } else {
 376                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 377                 case I855_GMCH_GMS_STOLEN_1M:
 378                         stolen_size = MB(1);
 379                         break;
 380                 case I855_GMCH_GMS_STOLEN_4M:
 381                         stolen_size = MB(4);
 382                         break;
 383                 case I855_GMCH_GMS_STOLEN_8M:
 384                         stolen_size = MB(8);
 385                         break;
 386                 case I855_GMCH_GMS_STOLEN_16M:
 387                         stolen_size = MB(16);
 388                         break;
 389                 case I855_GMCH_GMS_STOLEN_32M:
 390                         stolen_size = MB(32);
 391                         break;
 392                 case I915_GMCH_GMS_STOLEN_48M:
 393                         stolen_size = MB(48);
 394                         break;
 395                 case I915_GMCH_GMS_STOLEN_64M:
 396                         stolen_size = MB(64);
 397                         break;
 398                 case G33_GMCH_GMS_STOLEN_128M:
 399                         stolen_size = MB(128);
 400                         break;
 401                 case G33_GMCH_GMS_STOLEN_256M:
 402                         stolen_size = MB(256);
 403                         break;
 404                 case INTEL_GMCH_GMS_STOLEN_96M:
 405                         stolen_size = MB(96);
 406                         break;
 407                 case INTEL_GMCH_GMS_STOLEN_160M:
 408                         stolen_size = MB(160);
 409                         break;
 410                 case INTEL_GMCH_GMS_STOLEN_224M:
 411                         stolen_size = MB(224);
 412                         break;
 413                 case INTEL_GMCH_GMS_STOLEN_352M:
 414                         stolen_size = MB(352);
 415                         break;
 416                 default:
 417                         stolen_size = 0;
 418                         break;
 419                 }
 420         }
 421
 422         if (stolen_size > 0) {
 423                 dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n",
 424                        (u64)stolen_size / KB(1), local ? "local" : "stolen");
 425         } else {
 426                 dev_info(&intel_private.bridge_dev->dev,
 427                        "no pre-allocated video memory detected\n");
 428                 stolen_size = 0;
 429         }
 430
 431         return stolen_size;
 432 }
 433
 434 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 435 {
 436         u32 pgetbl_ctl, pgetbl_ctl2;
 437
 438         /* ensure that ppgtt is disabled */
 439         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 440         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 441         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 442
 443         /* write the new ggtt size */
 444         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 445         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 446         pgetbl_ctl |= size_flag;
 447         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 448 }
 449
 450 static unsigned int i965_gtt_total_entries(void)
 451 {
 452         int size;
 453         u32 pgetbl_ctl;
 454         u16 gmch_ctl;
 455
 456         pci_read_config_word(intel_private.bridge_dev,
 457                              I830_GMCH_CTRL, &gmch_ctl);
 458
 459         if (INTEL_GTT_GEN == 5) {
 460                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 461                 case G4x_GMCH_SIZE_1M:
 462                 case G4x_GMCH_SIZE_VT_1M:
 463                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 464                         break;
 465                 case G4x_GMCH_SIZE_VT_1_5M:
 466                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 467                         break;
 468                 case G4x_GMCH_SIZE_2M:
 469                 case G4x_GMCH_SIZE_VT_2M:
 470                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 471                         break;
 472                 }
 473         }
 474
 475         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 476
 477         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 478         case I965_PGETBL_SIZE_128KB:
 479                 size = KB(128);
 480                 break;
 481         case I965_PGETBL_SIZE_256KB:
 482                 size = KB(256);
 483                 break;
 484         case I965_PGETBL_SIZE_512KB:
 485                 size = KB(512);
 486                 break;
 487         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 488         case I965_PGETBL_SIZE_1MB:
 489                 size = KB(1024);
 490                 break;
 491         case I965_PGETBL_SIZE_2MB:
 492                 size = KB(2048);
 493                 break;
 494         case I965_PGETBL_SIZE_1_5MB:
 495                 size = KB(1024 + 512);
 496                 break;
 497         default:
 498                 dev_info(&intel_private.pcidev->dev,
 499                          "unknown page table size, assuming 512KB\n");
 500                 size = KB(512);
 501         }
 502
 503         return size/4;
 504 }
 505
 506 static unsigned int intel_gtt_total_entries(void)
 507 {
 508         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 509                 return i965_gtt_total_entries();
 510         else {
 511                 /* On previous hardware, the GTT size was just what was
 512                  * required to map the aperture.
 513                  */
 514                 return intel_private.gtt_mappable_entries;
 515         }
 516 }
 517
 518 static unsigned int intel_gtt_mappable_entries(void)
 519 {
 520         unsigned int aperture_size;
 521
 522         if (INTEL_GTT_GEN == 1) {
 523                 u32 smram_miscc;
 524
 525                 pci_read_config_dword(intel_private.bridge_dev,
 526                                       I810_SMRAM_MISCC, &smram_miscc);
 527
 528                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 529                                 == I810_GFX_MEM_WIN_32M)
 530                         aperture_size = MB(32);
 531                 else
 532                         aperture_size = MB(64);
 533         } else if (INTEL_GTT_GEN == 2) {
 534                 u16 gmch_ctrl;
 535
 536                 pci_read_config_word(intel_private.bridge_dev,
 537                                      I830_GMCH_CTRL, &gmch_ctrl);
 538
 539                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 540                         aperture_size = MB(64);
 541                 else
 542                         aperture_size = MB(128);
 543         } else {
 544                 /* 9xx supports large sizes, just look at the length */
 545                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 546         }
 547
 548         return aperture_size >> PAGE_SHIFT;
 549 }
 550
 551 static void intel_gtt_teardown_scratch_page(void)
 552 {
 553         set_pages_wb(intel_private.scratch_page, 1);
 554         if (intel_private.needs_dmar)
 555                 dma_unmap_page(&intel_private.pcidev->dev,
 556                                intel_private.scratch_page_dma, PAGE_SIZE,
 557                                DMA_BIDIRECTIONAL);
 558         __free_page(intel_private.scratch_page);
 559 }
 560
 561 static void intel_gtt_cleanup(void)
 562 {
 563         intel_private.driver->cleanup();
 564
 565         iounmap(intel_private.gtt);
 566         iounmap(intel_private.registers);
 567
 568         intel_gtt_teardown_scratch_page();
 569 }
 570
 571 /* Certain Gen5 chipsets require require idling the GPU before
 572  * unmapping anything from the GTT when VT-d is enabled.
 573  */
 574 static inline int needs_ilk_vtd_wa(void)
 575 {
 576 #ifdef CONFIG_INTEL_IOMMU
 577         const unsigned short gpu_devid = intel_private.pcidev->device;
 578
 579         /* Query intel_iommu to see if we need the workaround. Presumably that
 580          * was loaded first.
 581          */
 582         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||
 583              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
 584              intel_iommu_gfx_mapped)
 585                 return 1;
 586 #endif
 587         return 0;
 588 }
 589
 590 static bool intel_gtt_can_wc(void)
 591 {
 592         if (INTEL_GTT_GEN <= 2)
 593                 return false;
 594
 595         if (INTEL_GTT_GEN >= 6)
 596                 return false;
 597
 598         /* Reports of major corruption with ILK vt'd enabled */
 599         if (needs_ilk_vtd_wa())
 600                 return false;
 601
 602         return true;
 603 }
 604
 605 static int intel_gtt_init(void)
 606 {
 607         u32 gtt_map_size;
 608         int ret, bar;
 609
 610         ret = intel_private.driver->setup();
 611         if (ret != 0)
 612                 return ret;
 613
 614         intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
 615         intel_private.gtt_total_entries = intel_gtt_total_entries();
 616
 617         /* save the PGETBL reg for resume */
 618         intel_private.PGETBL_save =
 619                 readl(intel_private.registers+I810_PGETBL_CTL)
 620                         & ~I810_PGETBL_ENABLED;
 621         /* we only ever restore the register when enabling the PGTBL... */
 622         if (HAS_PGTBL_EN)
 623                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 624
 625         dev_info(&intel_private.bridge_dev->dev,
 626                         "detected gtt size: %dK total, %dK mappable\n",
 627                         intel_private.gtt_total_entries * 4,
 628                         intel_private.gtt_mappable_entries * 4);
 629
 630         gtt_map_size = intel_private.gtt_total_entries * 4;
 631
 632         intel_private.gtt = NULL;
 633         if (intel_gtt_can_wc())
 634                 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
 635                                                gtt_map_size);
 636         if (intel_private.gtt == NULL)
 637                 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
 638                                             gtt_map_size);
 639         if (intel_private.gtt == NULL) {
 640                 intel_private.driver->cleanup();
 641                 iounmap(intel_private.registers);
 642                 return -ENOMEM;
 643         }
 644
 645 #if IS_ENABLED(CONFIG_AGP_INTEL)
 646         global_cache_flush();   /* FIXME: ? */
 647 #endif
 648
 649         intel_private.stolen_size = intel_gtt_stolen_size();
 650
 651         intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
 652
 653         ret = intel_gtt_setup_scratch_page();
 654         if (ret != 0) {
 655                 intel_gtt_cleanup();
 656                 return ret;
 657         }
 658
 659         if (INTEL_GTT_GEN <= 2)
 660                 bar = I810_GMADR_BAR;
 661         else
 662                 bar = I915_GMADR_BAR;
 663
 664         intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
 665         return 0;
 666 }
 667
 668 #if IS_ENABLED(CONFIG_AGP_INTEL)
 669 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
 670         {32, 8192, 3},
 671         {64, 16384, 4},
 672         {128, 32768, 5},
 673         {256, 65536, 6},
 674         {512, 131072, 7},
 675 };
 676
 677 static int intel_fake_agp_fetch_size(void)
 678 {
 679         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 680         unsigned int aper_size;
 681         int i;
 682
 683         aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
 684
 685         for (i = 0; i < num_sizes; i++) {
 686                 if (aper_size == intel_fake_agp_sizes[i].size) {
 687                         agp_bridge->current_size =
 688                                 (void *) (intel_fake_agp_sizes + i);
 689                         return aper_size;
 690                 }
 691         }
 692
 693         return 0;
 694 }
 695 #endif
 696
 697 static void i830_cleanup(void)
 698 {
 699 }
 700
 701 /* The chipset_flush interface needs to get data that has already been
 702  * flushed out of the CPU all the way out to main memory, because the GPU
 703  * doesn't snoop those buffers.
 704  *
 705  * The 8xx series doesn't have the same lovely interface for flushing the
 706  * chipset write buffers that the later chips do. According to the 865
 707  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 708  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 709  * that it'll push whatever was in there out.  It appears to work.
 710  */
 711 static void i830_chipset_flush(void)
 712 {
 713         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 714
 715         /* Forcibly evict everything from the CPU write buffers.
 716          * clflush appears to be insufficient.
 717          */
 718         wbinvd_on_all_cpus();
 719
 720         /* Now we've only seen documents for this magic bit on 855GM,
 721          * we hope it exists for the other gen2 chipsets...
 722          *
 723          * Also works as advertised on my 845G.
 724          */
 725         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
 726                intel_private.registers+I830_HIC);
 727
 728         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
 729                 if (time_after(jiffies, timeout))
 730                         break;
 731
 732                 udelay(50);
 733         }
 734 }
 735
 736 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 737                              unsigned int flags)
 738 {
 739         u32 pte_flags = I810_PTE_VALID;
 740
 741         if (flags ==  AGP_USER_CACHED_MEMORY)
 742                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 743
 744         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 745 }
 746
 747 bool intel_enable_gtt(void)
 748 {
 749         u8 __iomem *reg;
 750
 751         if (INTEL_GTT_GEN == 2) {
 752                 u16 gmch_ctrl;
 753
 754                 pci_read_config_word(intel_private.bridge_dev,
 755                                      I830_GMCH_CTRL, &gmch_ctrl);
 756                 gmch_ctrl |= I830_GMCH_ENABLED;
 757                 pci_write_config_word(intel_private.bridge_dev,
 758                                       I830_GMCH_CTRL, gmch_ctrl);
 759
 760                 pci_read_config_word(intel_private.bridge_dev,
 761                                      I830_GMCH_CTRL, &gmch_ctrl);
 762                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 763                         dev_err(&intel_private.pcidev->dev,
 764                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 765                                 gmch_ctrl);
 766                         return false;
 767                 }
 768         }
 769
 770         /* On the resume path we may be adjusting the PGTBL value, so
 771          * be paranoid and flush all chipset write buffers...
 772          */
 773         if (INTEL_GTT_GEN >= 3)
 774                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 775
 776         reg = intel_private.registers+I810_PGETBL_CTL;
 777         writel(intel_private.PGETBL_save, reg);
 778         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 779                 dev_err(&intel_private.pcidev->dev,
 780                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 781                         readl(reg), intel_private.PGETBL_save);
 782                 return false;
 783         }
 784
 785         if (INTEL_GTT_GEN >= 3)
 786                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 787
 788         return true;
 789 }
 790 EXPORT_SYMBOL(intel_enable_gtt);
 791
 792 static int i830_setup(void)
 793 {
 794         phys_addr_t reg_addr;
 795
 796         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 797
 798         intel_private.registers = ioremap(reg_addr, KB(64));
 799         if (!intel_private.registers)
 800                 return -ENOMEM;
 801
 802         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 803
 804         return 0;
 805 }
 806
 807 #if IS_ENABLED(CONFIG_AGP_INTEL)
 808 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 809 {
 810         agp_bridge->gatt_table_real = NULL;
 811         agp_bridge->gatt_table = NULL;
 812         agp_bridge->gatt_bus_addr = 0;
 813
 814         return 0;
 815 }
 816
 817 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 818 {
 819         return 0;
 820 }
 821
 822 static int intel_fake_agp_configure(void)
 823 {
 824         if (!intel_enable_gtt())
 825             return -EIO;
 826
 827         intel_private.clear_fake_agp = true;
 828         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
 829
 830         return 0;
 831 }
 832 #endif
 833
 834 static bool i830_check_flags(unsigned int flags)
 835 {
 836         switch (flags) {
 837         case 0:
 838         case AGP_PHYS_MEMORY:
 839         case AGP_USER_CACHED_MEMORY:
 840         case AGP_USER_MEMORY:
 841                 return true;
 842         }
 843
 844         return false;
 845 }
 846
 847 void intel_gtt_insert_page(dma_addr_t addr,
 848                            unsigned int pg,
 849                            unsigned int flags)
 850 {
 851         intel_private.driver->write_entry(addr, pg, flags);
 852         readl(intel_private.gtt + pg);
 853         if (intel_private.driver->chipset_flush)
 854                 intel_private.driver->chipset_flush();
 855 }
 856 EXPORT_SYMBOL(intel_gtt_insert_page);
 857
 858 void intel_gtt_insert_sg_entries(struct sg_table *st,
 859                                  unsigned int pg_start,
 860                                  unsigned int flags)
 861 {
 862         struct scatterlist *sg;
 863         unsigned int len, m;
 864         int i, j;
 865
 866         j = pg_start;
 867
 868         /* sg may merge pages, but we have to separate
 869          * per-page addr for GTT */
 870         for_each_sg(st->sgl, sg, st->nents, i) {
 871                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 872                 for (m = 0; m < len; m++) {
 873                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 874                         intel_private.driver->write_entry(addr, j, flags);
 875                         j++;
 876                 }
 877         }
 878         readl(intel_private.gtt + j - 1);
 879         if (intel_private.driver->chipset_flush)
 880                 intel_private.driver->chipset_flush();
 881 }
 882 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 883
 884 #if IS_ENABLED(CONFIG_AGP_INTEL)
 885 static void intel_gtt_insert_pages(unsigned int first_entry,
 886                                    unsigned int num_entries,
 887                                    struct page **pages,
 888                                    unsigned int flags)
 889 {
 890         int i, j;
 891
 892         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
 893                 dma_addr_t addr = page_to_phys(pages[i]);
 894                 intel_private.driver->write_entry(addr,
 895                                                   j, flags);
 896         }
 897         wmb();
 898 }
 899
 900 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 901                                          off_t pg_start, int type)
 902 {
 903         int ret = -EINVAL;
 904
 905         if (intel_private.clear_fake_agp) {
 906                 int start = intel_private.stolen_size / PAGE_SIZE;
 907                 int end = intel_private.gtt_mappable_entries;
 908                 intel_gtt_clear_range(start, end - start);
 909                 intel_private.clear_fake_agp = false;
 910         }
 911
 912         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 913                 return i810_insert_dcache_entries(mem, pg_start, type);
 914
 915         if (mem->page_count == 0)
 916                 goto out;
 917
 918         if (pg_start + mem->page_count > intel_private.gtt_total_entries)
 919                 goto out_err;
 920
 921         if (type != mem->type)
 922                 goto out_err;
 923
 924         if (!intel_private.driver->check_flags(type))
 925                 goto out_err;
 926
 927         if (!mem->is_flushed)
 928                 global_cache_flush();
 929
 930         if (intel_private.needs_dmar) {
 931                 struct sg_table st;
 932
 933                 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
 934                 if (ret != 0)
 935                         return ret;
 936
 937                 intel_gtt_insert_sg_entries(&st, pg_start, type);
 938                 mem->sg_list = st.sgl;
 939                 mem->num_sg = st.nents;
 940         } else
 941                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
 942                                        type);
 943
 944 out:
 945         ret = 0;
 946 out_err:
 947         mem->is_flushed = true;
 948         return ret;
 949 }
 950 #endif
 951
 952 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 953 {
 954         unsigned int i;
 955
 956         for (i = first_entry; i < (first_entry + num_entries); i++) {
 957                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
 958                                                   i, 0);
 959         }
 960         wmb();
 961 }
 962 EXPORT_SYMBOL(intel_gtt_clear_range);
 963
 964 #if IS_ENABLED(CONFIG_AGP_INTEL)
 965 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
 966                                          off_t pg_start, int type)
 967 {
 968         if (mem->page_count == 0)
 969                 return 0;
 970
 971         intel_gtt_clear_range(pg_start, mem->page_count);
 972
 973         if (intel_private.needs_dmar) {
 974                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
 975                 mem->sg_list = NULL;
 976                 mem->num_sg = 0;
 977         }
 978
 979         return 0;
 980 }
 981
 982 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
 983                                                        int type)
 984 {
 985         struct agp_memory *new;
 986
 987         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
 988                 if (pg_count != intel_private.num_dcache_entries)
 989                         return NULL;
 990
 991                 new = agp_create_memory(1);
 992                 if (new == NULL)
 993                         return NULL;
 994
 995                 new->type = AGP_DCACHE_MEMORY;
 996                 new->page_count = pg_count;
 997                 new->num_scratch_pages = 0;
 998                 agp_free_page_array(new);
 999                 return new;
1000         }
1001         if (type == AGP_PHYS_MEMORY)
1002                 return alloc_agpphysmem_i8xx(pg_count, type);
1003         /* always return NULL for other allocation types for now */
1004         return NULL;
1005 }
1006 #endif
1007
1008 static int intel_alloc_chipset_flush_resource(void)
1009 {
1010         int ret;
1011         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1012                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1013                                      pcibios_align_resource, intel_private.bridge_dev);
1014
1015         return ret;
1016 }
1017
1018 static void intel_i915_setup_chipset_flush(void)
1019 {
1020         int ret;
1021         u32 temp;
1022
1023         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1024         if (!(temp & 0x1)) {
1025                 intel_alloc_chipset_flush_resource();
1026                 intel_private.resource_valid = 1;
1027                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1028         } else {
1029                 temp &= ~1;
1030
1031                 intel_private.resource_valid = 1;
1032                 intel_private.ifp_resource.start = temp;
1033                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1034                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1035                 /* some BIOSes reserve this area in a pnp some don't */
1036                 if (ret)
1037                         intel_private.resource_valid = 0;
1038         }
1039 }
1040
1041 static void intel_i965_g33_setup_chipset_flush(void)
1042 {
1043         u32 temp_hi, temp_lo;
1044         int ret;
1045
1046         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1047         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1048
1049         if (!(temp_lo & 0x1)) {
1050
1051                 intel_alloc_chipset_flush_resource();
1052
1053                 intel_private.resource_valid = 1;
1054                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1055                         upper_32_bits(intel_private.ifp_resource.start));
1056                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1057         } else {
1058                 u64 l64;
1059
1060                 temp_lo &= ~0x1;
1061                 l64 = ((u64)temp_hi << 32) | temp_lo;
1062
1063                 intel_private.resource_valid = 1;
1064                 intel_private.ifp_resource.start = l64;
1065                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1066                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1067                 /* some BIOSes reserve this area in a pnp some don't */
1068                 if (ret)
1069                         intel_private.resource_valid = 0;
1070         }
1071 }
1072
1073 static void intel_i9xx_setup_flush(void)
1074 {
1075         /* return if already configured */
1076         if (intel_private.ifp_resource.start)
1077                 return;
1078
1079         if (INTEL_GTT_GEN == 6)
1080                 return;
1081
1082         /* setup a resource for this object */
1083         intel_private.ifp_resource.name = "Intel Flush Page";
1084         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1085
1086         /* Setup chipset flush for 915 */
1087         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1088                 intel_i965_g33_setup_chipset_flush();
1089         } else {
1090                 intel_i915_setup_chipset_flush();
1091         }
1092
1093         if (intel_private.ifp_resource.start)
1094                 intel_private.i9xx_flush_page = ioremap(intel_private.ifp_resource.start, PAGE_SIZE);
1095         if (!intel_private.i9xx_flush_page)
1096                 dev_err(&intel_private.pcidev->dev,
1097                         "can't ioremap flush page - no chipset flushing\n");
1098 }
1099
1100 static void i9xx_cleanup(void)
1101 {
1102         if (intel_private.i9xx_flush_page)
1103                 iounmap(intel_private.i9xx_flush_page);
1104         if (intel_private.resource_valid)
1105                 release_resource(&intel_private.ifp_resource);
1106         intel_private.ifp_resource.start = 0;
1107         intel_private.resource_valid = 0;
1108 }
1109
1110 static void i9xx_chipset_flush(void)
1111 {
1112         wmb();
1113         if (intel_private.i9xx_flush_page)
1114                 writel(1, intel_private.i9xx_flush_page);
1115 }
1116
1117 static void i965_write_entry(dma_addr_t addr,
1118                              unsigned int entry,
1119                              unsigned int flags)
1120 {
1121         u32 pte_flags;
1122
1123         pte_flags = I810_PTE_VALID;
1124         if (flags == AGP_USER_CACHED_MEMORY)
1125                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1126
1127         /* Shift high bits down */
1128         addr |= (addr >> 28) & 0xf0;
1129         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1130 }
1131
1132 static int i9xx_setup(void)
1133 {
1134         phys_addr_t reg_addr;
1135         int size = KB(512);
1136
1137         reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1138
1139         intel_private.registers = ioremap(reg_addr, size);
1140         if (!intel_private.registers)
1141                 return -ENOMEM;
1142
1143         switch (INTEL_GTT_GEN) {
1144         case 3:
1145                 intel_private.gtt_phys_addr =
1146                         pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1147                 break;
1148         case 5:
1149                 intel_private.gtt_phys_addr = reg_addr + MB(2);
1150                 break;
1151         default:
1152                 intel_private.gtt_phys_addr = reg_addr + KB(512);
1153                 break;
1154         }
1155
1156         intel_i9xx_setup_flush();
1157
1158         return 0;
1159 }
1160
1161 #if IS_ENABLED(CONFIG_AGP_INTEL)
1162 static const struct agp_bridge_driver intel_fake_agp_driver = {
1163         .owner                  = THIS_MODULE,
1164         .size_type              = FIXED_APER_SIZE,
1165         .aperture_sizes         = intel_fake_agp_sizes,
1166         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1167         .configure              = intel_fake_agp_configure,
1168         .fetch_size             = intel_fake_agp_fetch_size,
1169         .cleanup                = intel_gtt_cleanup,
1170         .agp_enable             = intel_fake_agp_enable,
1171         .cache_flush            = global_cache_flush,
1172         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1173         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1174         .insert_memory          = intel_fake_agp_insert_entries,
1175         .remove_memory          = intel_fake_agp_remove_entries,
1176         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1177         .free_by_type           = intel_i810_free_by_type,
1178         .agp_alloc_page         = agp_generic_alloc_page,
1179         .agp_alloc_pages        = agp_generic_alloc_pages,
1180         .agp_destroy_page       = agp_generic_destroy_page,
1181         .agp_destroy_pages      = agp_generic_destroy_pages,
1182 };
1183 #endif
1184
1185 static const struct intel_gtt_driver i81x_gtt_driver = {
1186         .gen = 1,
1187         .has_pgtbl_enable = 1,
1188         .dma_mask_size = 32,
1189         .setup = i810_setup,
1190         .cleanup = i810_cleanup,
1191         .check_flags = i830_check_flags,
1192         .write_entry = i810_write_entry,
1193 };
1194 static const struct intel_gtt_driver i8xx_gtt_driver = {
1195         .gen = 2,
1196         .has_pgtbl_enable = 1,
1197         .setup = i830_setup,
1198         .cleanup = i830_cleanup,
1199         .write_entry = i830_write_entry,
1200         .dma_mask_size = 32,
1201         .check_flags = i830_check_flags,
1202         .chipset_flush = i830_chipset_flush,
1203 };
1204 static const struct intel_gtt_driver i915_gtt_driver = {
1205         .gen = 3,
1206         .has_pgtbl_enable = 1,
1207         .setup = i9xx_setup,
1208         .cleanup = i9xx_cleanup,
1209         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1210         .write_entry = i830_write_entry,
1211         .dma_mask_size = 32,
1212         .check_flags = i830_check_flags,
1213         .chipset_flush = i9xx_chipset_flush,
1214 };
1215 static const struct intel_gtt_driver g33_gtt_driver = {
1216         .gen = 3,
1217         .is_g33 = 1,
1218         .setup = i9xx_setup,
1219         .cleanup = i9xx_cleanup,
1220         .write_entry = i965_write_entry,
1221         .dma_mask_size = 36,
1222         .check_flags = i830_check_flags,
1223         .chipset_flush = i9xx_chipset_flush,
1224 };
1225 static const struct intel_gtt_driver pineview_gtt_driver = {
1226         .gen = 3,
1227         .is_pineview = 1, .is_g33 = 1,
1228         .setup = i9xx_setup,
1229         .cleanup = i9xx_cleanup,
1230         .write_entry = i965_write_entry,
1231         .dma_mask_size = 36,
1232         .check_flags = i830_check_flags,
1233         .chipset_flush = i9xx_chipset_flush,
1234 };
1235 static const struct intel_gtt_driver i965_gtt_driver = {
1236         .gen = 4,
1237         .has_pgtbl_enable = 1,
1238         .setup = i9xx_setup,
1239         .cleanup = i9xx_cleanup,
1240         .write_entry = i965_write_entry,
1241         .dma_mask_size = 36,
1242         .check_flags = i830_check_flags,
1243         .chipset_flush = i9xx_chipset_flush,
1244 };
1245 static const struct intel_gtt_driver g4x_gtt_driver = {
1246         .gen = 5,
1247         .setup = i9xx_setup,
1248         .cleanup = i9xx_cleanup,
1249         .write_entry = i965_write_entry,
1250         .dma_mask_size = 36,
1251         .check_flags = i830_check_flags,
1252         .chipset_flush = i9xx_chipset_flush,
1253 };
1254 static const struct intel_gtt_driver ironlake_gtt_driver = {
1255         .gen = 5,
1256         .is_ironlake = 1,
1257         .setup = i9xx_setup,
1258         .cleanup = i9xx_cleanup,
1259         .write_entry = i965_write_entry,
1260         .dma_mask_size = 36,
1261         .check_flags = i830_check_flags,
1262         .chipset_flush = i9xx_chipset_flush,
1263 };
1264
1265 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1266  * driver and gmch_driver must be non-null, and find_gmch will determine
1267  * which one should be used if a gmch_chip_id is present.
1268  */
1269 static const struct intel_gtt_driver_description {
1270         unsigned int gmch_chip_id;
1271         char *name;
1272         const struct intel_gtt_driver *gtt_driver;
1273 } intel_gtt_chipsets[] = {
1274         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1275                 &i81x_gtt_driver},
1276         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1277                 &i81x_gtt_driver},
1278         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1279                 &i81x_gtt_driver},
1280         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1281                 &i81x_gtt_driver},
1282         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1283                 &i8xx_gtt_driver},
1284         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1285                 &i8xx_gtt_driver},
1286         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1287                 &i8xx_gtt_driver},
1288         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1289                 &i8xx_gtt_driver},
1290         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1291                 &i8xx_gtt_driver},
1292         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1293                 &i915_gtt_driver },
1294         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1295                 &i915_gtt_driver },
1296         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1297                 &i915_gtt_driver },
1298         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1299                 &i915_gtt_driver },
1300         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1301                 &i915_gtt_driver },
1302         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1303                 &i915_gtt_driver },
1304         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1305                 &i965_gtt_driver },
1306         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1307                 &i965_gtt_driver },
1308         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1309                 &i965_gtt_driver },
1310         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1311                 &i965_gtt_driver },
1312         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1313                 &i965_gtt_driver },
1314         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1315                 &i965_gtt_driver },
1316         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1317                 &g33_gtt_driver },
1318         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1319                 &g33_gtt_driver },
1320         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1321                 &g33_gtt_driver },
1322         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1323                 &pineview_gtt_driver },
1324         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1325                 &pineview_gtt_driver },
1326         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1327                 &g4x_gtt_driver },
1328         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1329                 &g4x_gtt_driver },
1330         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1331                 &g4x_gtt_driver },
1332         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1333                 &g4x_gtt_driver },
1334         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1335                 &g4x_gtt_driver },
1336         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1337                 &g4x_gtt_driver },
1338         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1339                 &g4x_gtt_driver },
1340         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1341             "HD Graphics", &ironlake_gtt_driver },
1342         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1343             "HD Graphics", &ironlake_gtt_driver },
1344         { 0, NULL, NULL }
1345 };
1346
1347 static int find_gmch(u16 device)
1348 {
1349         struct pci_dev *gmch_device;
1350
1351         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1352         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1353                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1354                                              device, gmch_device);
1355         }
1356
1357         if (!gmch_device)
1358                 return 0;
1359
1360         intel_private.pcidev = gmch_device;
1361         return 1;
1362 }
1363
1364 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1365                      struct agp_bridge_data *bridge)
1366 {
1367         int i, mask;
1368
1369         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1370                 if (gpu_pdev) {
1371                         if (gpu_pdev->device ==
1372                             intel_gtt_chipsets[i].gmch_chip_id) {
1373                                 intel_private.pcidev = pci_dev_get(gpu_pdev);
1374                                 intel_private.driver =
1375                                         intel_gtt_chipsets[i].gtt_driver;
1376
1377                                 break;
1378                         }
1379                 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1380                         intel_private.driver =
1381                                 intel_gtt_chipsets[i].gtt_driver;
1382                         break;
1383                 }
1384         }
1385
1386         if (!intel_private.driver)
1387                 return 0;
1388
1389 #if IS_ENABLED(CONFIG_AGP_INTEL)
1390         if (bridge) {
1391                 if (INTEL_GTT_GEN > 1)
1392                         return 0;
1393
1394                 bridge->driver = &intel_fake_agp_driver;
1395                 bridge->dev_private_data = &intel_private;
1396                 bridge->dev = bridge_pdev;
1397         }
1398 #endif
1399
1400
1401         /*
1402          * Can be called from the fake agp driver but also directly from
1403          * drm/i915.ko. Hence we need to check whether everything is set up
1404          * already.
1405          */
1406         if (intel_private.refcount++)
1407                 return 1;
1408
1409         intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1410
1411         dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1412
1413         if (bridge) {
1414                 mask = intel_private.driver->dma_mask_size;
1415                 if (dma_set_mask(&intel_private.pcidev->dev, DMA_BIT_MASK(mask)))
1416                         dev_err(&intel_private.pcidev->dev,
1417                                 "set gfx device dma mask %d-bit failed!\n",
1418                                 mask);
1419                 else
1420                         dma_set_coherent_mask(&intel_private.pcidev->dev,
1421                                               DMA_BIT_MASK(mask));
1422         }
1423
1424         if (intel_gtt_init() != 0) {
1425                 intel_gmch_remove();
1426
1427                 return 0;
1428         }
1429
1430         return 1;
1431 }
1432 EXPORT_SYMBOL(intel_gmch_probe);
1433
1434 void intel_gtt_get(u64 *gtt_total,
1435                    phys_addr_t *mappable_base,
1436                    resource_size_t *mappable_end)
1437 {
1438         *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1439         *mappable_base = intel_private.gma_bus_addr;
1440         *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1441 }
1442 EXPORT_SYMBOL(intel_gtt_get);
1443
1444 void intel_gtt_chipset_flush(void)
1445 {
1446         if (intel_private.driver->chipset_flush)
1447                 intel_private.driver->chipset_flush();
1448 }
1449 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1450
1451 void intel_gmch_remove(void)
1452 {
1453         if (--intel_private.refcount)
1454                 return;
1455
1456         if (intel_private.scratch_page)
1457                 intel_gtt_teardown_scratch_page();
1458         if (intel_private.pcidev)
1459                 pci_dev_put(intel_private.pcidev);
1460         if (intel_private.bridge_dev)
1461                 pci_dev_put(intel_private.bridge_dev);
1462         intel_private.driver = NULL;
1463 }
1464 EXPORT_SYMBOL(intel_gmch_remove);
1465
1466 MODULE_AUTHOR("Dave Jones, Various @Intel");
1467 MODULE_LICENSE("GPL and additional rights");