2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/kernel.h>
21 #include <linux/pagemap.h>
22 #include <linux/agp_backend.h>
23 #include <linux/delay.h>
26 #include "intel-agp.h"
27 #include <drm/intel-gtt.h>
28 #include <asm/set_memory.h>
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
39 #define USE_PCI_DMA_API 0
42 struct intel_gtt_driver {
44 unsigned int is_g33 : 1;
45 unsigned int is_pineview : 1;
46 unsigned int is_ironlake : 1;
47 unsigned int has_pgtbl_enable : 1;
48 unsigned int dma_mask_size : 8;
49 /* Chipset specific GTT setup */
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup)(void);
54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags)(unsigned int flags);
59 void (*chipset_flush)(void);
62 static struct _intel_private {
63 const struct intel_gtt_driver *driver;
64 struct pci_dev *pcidev; /* device one */
65 struct pci_dev *bridge_dev;
66 u8 __iomem *registers;
67 phys_addr_t gtt_phys_addr;
69 u32 __iomem *gtt; /* I915G */
70 bool clear_fake_agp; /* on first access via agp, fill with scratch */
71 int num_dcache_entries;
72 void __iomem *i9xx_flush_page;
74 struct resource ifp_resource;
76 struct page *scratch_page;
77 phys_addr_t scratch_page_dma;
79 /* Whether i915 needs to use the dmar apis or not. */
80 unsigned int needs_dmar : 1;
81 phys_addr_t gma_bus_addr;
82 /* Size of memory reserved for graphics by the BIOS */
83 resource_size_t stolen_size;
84 /* Total number of gtt entries. */
85 unsigned int gtt_total_entries;
86 /* Part of the gtt that is mappable by the cpu, for those chips where
87 * this is not the full gtt. */
88 unsigned int gtt_mappable_entries;
91 #define INTEL_GTT_GEN intel_private.driver->gen
92 #define IS_G33 intel_private.driver->is_g33
93 #define IS_PINEVIEW intel_private.driver->is_pineview
94 #define IS_IRONLAKE intel_private.driver->is_ironlake
95 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
97 #if IS_ENABLED(CONFIG_AGP_INTEL)
98 static int intel_gtt_map_memory(struct page **pages,
99 unsigned int num_entries,
102 struct scatterlist *sg;
105 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
107 if (sg_alloc_table(st, num_entries, GFP_KERNEL))
110 for_each_sg(st->sgl, sg, num_entries, i)
111 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
113 if (!pci_map_sg(intel_private.pcidev,
114 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
124 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
127 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
129 pci_unmap_sg(intel_private.pcidev, sg_list,
130 num_sg, PCI_DMA_BIDIRECTIONAL);
133 st.orig_nents = st.nents = num_sg;
138 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
143 /* Exists to support ARGB cursors */
144 static struct page *i8xx_alloc_pages(void)
148 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
152 if (set_pages_uc(page, 4) < 0) {
153 set_pages_wb(page, 4);
154 __free_pages(page, 2);
157 atomic_inc(&agp_bridge->current_memory_agp);
161 static void i8xx_destroy_pages(struct page *page)
166 set_pages_wb(page, 4);
167 __free_pages(page, 2);
168 atomic_dec(&agp_bridge->current_memory_agp);
172 #define I810_GTT_ORDER 4
173 static int i810_setup(void)
175 phys_addr_t reg_addr;
178 /* i81x does not preallocate the gtt. It's always 64kb in size. */
179 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
180 if (gtt_table == NULL)
182 intel_private.i81x_gtt_table = gtt_table;
184 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
186 intel_private.registers = ioremap(reg_addr, KB(64));
187 if (!intel_private.registers)
190 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
191 intel_private.registers+I810_PGETBL_CTL);
193 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
195 if ((readl(intel_private.registers+I810_DRAM_CTL)
196 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
197 dev_info(&intel_private.pcidev->dev,
198 "detected 4MB dedicated video ram\n");
199 intel_private.num_dcache_entries = 1024;
205 static void i810_cleanup(void)
207 writel(0, intel_private.registers+I810_PGETBL_CTL);
208 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
211 #if IS_ENABLED(CONFIG_AGP_INTEL)
212 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
217 if ((pg_start + mem->page_count)
218 > intel_private.num_dcache_entries)
221 if (!mem->is_flushed)
222 global_cache_flush();
224 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
225 dma_addr_t addr = i << PAGE_SHIFT;
226 intel_private.driver->write_entry(addr,
235 * The i810/i830 requires a physical address to program its mouse
236 * pointer into hardware.
237 * However the Xserver still writes to it through the agp aperture.
239 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
241 struct agp_memory *new;
245 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
248 /* kludge to get 4 physical pages for ARGB cursor */
249 page = i8xx_alloc_pages();
258 new = agp_create_memory(pg_count);
262 new->pages[0] = page;
264 /* kludge to get 4 physical pages for ARGB cursor */
265 new->pages[1] = new->pages[0] + 1;
266 new->pages[2] = new->pages[1] + 1;
267 new->pages[3] = new->pages[2] + 1;
269 new->page_count = pg_count;
270 new->num_scratch_pages = pg_count;
271 new->type = AGP_PHYS_MEMORY;
272 new->physical = page_to_phys(new->pages[0]);
276 static void intel_i810_free_by_type(struct agp_memory *curr)
278 agp_free_key(curr->key);
279 if (curr->type == AGP_PHYS_MEMORY) {
280 if (curr->page_count == 4)
281 i8xx_destroy_pages(curr->pages[0]);
283 agp_bridge->driver->agp_destroy_page(curr->pages[0],
284 AGP_PAGE_DESTROY_UNMAP);
285 agp_bridge->driver->agp_destroy_page(curr->pages[0],
286 AGP_PAGE_DESTROY_FREE);
288 agp_free_page_array(curr);
294 static int intel_gtt_setup_scratch_page(void)
299 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
302 set_pages_uc(page, 1);
304 if (intel_private.needs_dmar) {
305 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
306 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
307 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) {
312 intel_private.scratch_page_dma = dma_addr;
314 intel_private.scratch_page_dma = page_to_phys(page);
316 intel_private.scratch_page = page;
321 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
324 u32 pte_flags = I810_PTE_VALID;
327 case AGP_DCACHE_MEMORY:
328 pte_flags |= I810_PTE_LOCAL;
330 case AGP_USER_CACHED_MEMORY:
331 pte_flags |= I830_PTE_SYSTEM_CACHED;
335 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
338 static resource_size_t intel_gtt_stolen_size(void)
343 static const int ddt[4] = { 0, 16, 32, 64 };
344 resource_size_t stolen_size = 0;
346 if (INTEL_GTT_GEN == 1)
347 return 0; /* no stolen mem on i81x */
349 pci_read_config_word(intel_private.bridge_dev,
350 I830_GMCH_CTRL, &gmch_ctrl);
352 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
353 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
354 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
355 case I830_GMCH_GMS_STOLEN_512:
356 stolen_size = KB(512);
358 case I830_GMCH_GMS_STOLEN_1024:
361 case I830_GMCH_GMS_STOLEN_8192:
364 case I830_GMCH_GMS_LOCAL:
365 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
366 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
367 MB(ddt[I830_RDRAM_DDT(rdct)]);
375 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
376 case I855_GMCH_GMS_STOLEN_1M:
379 case I855_GMCH_GMS_STOLEN_4M:
382 case I855_GMCH_GMS_STOLEN_8M:
385 case I855_GMCH_GMS_STOLEN_16M:
386 stolen_size = MB(16);
388 case I855_GMCH_GMS_STOLEN_32M:
389 stolen_size = MB(32);
391 case I915_GMCH_GMS_STOLEN_48M:
392 stolen_size = MB(48);
394 case I915_GMCH_GMS_STOLEN_64M:
395 stolen_size = MB(64);
397 case G33_GMCH_GMS_STOLEN_128M:
398 stolen_size = MB(128);
400 case G33_GMCH_GMS_STOLEN_256M:
401 stolen_size = MB(256);
403 case INTEL_GMCH_GMS_STOLEN_96M:
404 stolen_size = MB(96);
406 case INTEL_GMCH_GMS_STOLEN_160M:
407 stolen_size = MB(160);
409 case INTEL_GMCH_GMS_STOLEN_224M:
410 stolen_size = MB(224);
412 case INTEL_GMCH_GMS_STOLEN_352M:
413 stolen_size = MB(352);
421 if (stolen_size > 0) {
422 dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n",
423 (u64)stolen_size / KB(1), local ? "local" : "stolen");
425 dev_info(&intel_private.bridge_dev->dev,
426 "no pre-allocated video memory detected\n");
433 static void i965_adjust_pgetbl_size(unsigned int size_flag)
435 u32 pgetbl_ctl, pgetbl_ctl2;
437 /* ensure that ppgtt is disabled */
438 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
439 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
440 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
442 /* write the new ggtt size */
443 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
444 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
445 pgetbl_ctl |= size_flag;
446 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
449 static unsigned int i965_gtt_total_entries(void)
455 pci_read_config_word(intel_private.bridge_dev,
456 I830_GMCH_CTRL, &gmch_ctl);
458 if (INTEL_GTT_GEN == 5) {
459 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
460 case G4x_GMCH_SIZE_1M:
461 case G4x_GMCH_SIZE_VT_1M:
462 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
464 case G4x_GMCH_SIZE_VT_1_5M:
465 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
467 case G4x_GMCH_SIZE_2M:
468 case G4x_GMCH_SIZE_VT_2M:
469 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
474 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
476 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
477 case I965_PGETBL_SIZE_128KB:
480 case I965_PGETBL_SIZE_256KB:
483 case I965_PGETBL_SIZE_512KB:
486 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
487 case I965_PGETBL_SIZE_1MB:
490 case I965_PGETBL_SIZE_2MB:
493 case I965_PGETBL_SIZE_1_5MB:
494 size = KB(1024 + 512);
497 dev_info(&intel_private.pcidev->dev,
498 "unknown page table size, assuming 512KB\n");
505 static unsigned int intel_gtt_total_entries(void)
507 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
508 return i965_gtt_total_entries();
510 /* On previous hardware, the GTT size was just what was
511 * required to map the aperture.
513 return intel_private.gtt_mappable_entries;
517 static unsigned int intel_gtt_mappable_entries(void)
519 unsigned int aperture_size;
521 if (INTEL_GTT_GEN == 1) {
524 pci_read_config_dword(intel_private.bridge_dev,
525 I810_SMRAM_MISCC, &smram_miscc);
527 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
528 == I810_GFX_MEM_WIN_32M)
529 aperture_size = MB(32);
531 aperture_size = MB(64);
532 } else if (INTEL_GTT_GEN == 2) {
535 pci_read_config_word(intel_private.bridge_dev,
536 I830_GMCH_CTRL, &gmch_ctrl);
538 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
539 aperture_size = MB(64);
541 aperture_size = MB(128);
543 /* 9xx supports large sizes, just look at the length */
544 aperture_size = pci_resource_len(intel_private.pcidev, 2);
547 return aperture_size >> PAGE_SHIFT;
550 static void intel_gtt_teardown_scratch_page(void)
552 set_pages_wb(intel_private.scratch_page, 1);
553 if (intel_private.needs_dmar)
554 pci_unmap_page(intel_private.pcidev,
555 intel_private.scratch_page_dma,
556 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
557 __free_page(intel_private.scratch_page);
560 static void intel_gtt_cleanup(void)
562 intel_private.driver->cleanup();
564 iounmap(intel_private.gtt);
565 iounmap(intel_private.registers);
567 intel_gtt_teardown_scratch_page();
570 /* Certain Gen5 chipsets require require idling the GPU before
571 * unmapping anything from the GTT when VT-d is enabled.
573 static inline int needs_ilk_vtd_wa(void)
575 #ifdef CONFIG_INTEL_IOMMU
576 const unsigned short gpu_devid = intel_private.pcidev->device;
578 /* Query intel_iommu to see if we need the workaround. Presumably that
581 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||
582 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
583 intel_iommu_gfx_mapped)
589 static bool intel_gtt_can_wc(void)
591 if (INTEL_GTT_GEN <= 2)
594 if (INTEL_GTT_GEN >= 6)
597 /* Reports of major corruption with ILK vt'd enabled */
598 if (needs_ilk_vtd_wa())
604 static int intel_gtt_init(void)
609 ret = intel_private.driver->setup();
613 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
614 intel_private.gtt_total_entries = intel_gtt_total_entries();
616 /* save the PGETBL reg for resume */
617 intel_private.PGETBL_save =
618 readl(intel_private.registers+I810_PGETBL_CTL)
619 & ~I810_PGETBL_ENABLED;
620 /* we only ever restore the register when enabling the PGTBL... */
622 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
624 dev_info(&intel_private.bridge_dev->dev,
625 "detected gtt size: %dK total, %dK mappable\n",
626 intel_private.gtt_total_entries * 4,
627 intel_private.gtt_mappable_entries * 4);
629 gtt_map_size = intel_private.gtt_total_entries * 4;
631 intel_private.gtt = NULL;
632 if (intel_gtt_can_wc())
633 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
635 if (intel_private.gtt == NULL)
636 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
638 if (intel_private.gtt == NULL) {
639 intel_private.driver->cleanup();
640 iounmap(intel_private.registers);
644 #if IS_ENABLED(CONFIG_AGP_INTEL)
645 global_cache_flush(); /* FIXME: ? */
648 intel_private.stolen_size = intel_gtt_stolen_size();
650 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
652 ret = intel_gtt_setup_scratch_page();
658 if (INTEL_GTT_GEN <= 2)
659 bar = I810_GMADR_BAR;
661 bar = I915_GMADR_BAR;
663 intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
667 #if IS_ENABLED(CONFIG_AGP_INTEL)
668 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
676 static int intel_fake_agp_fetch_size(void)
678 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
679 unsigned int aper_size;
682 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
684 for (i = 0; i < num_sizes; i++) {
685 if (aper_size == intel_fake_agp_sizes[i].size) {
686 agp_bridge->current_size =
687 (void *) (intel_fake_agp_sizes + i);
696 static void i830_cleanup(void)
700 /* The chipset_flush interface needs to get data that has already been
701 * flushed out of the CPU all the way out to main memory, because the GPU
702 * doesn't snoop those buffers.
704 * The 8xx series doesn't have the same lovely interface for flushing the
705 * chipset write buffers that the later chips do. According to the 865
706 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
707 * that buffer out, we just fill 1KB and clflush it out, on the assumption
708 * that it'll push whatever was in there out. It appears to work.
710 static void i830_chipset_flush(void)
712 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
714 /* Forcibly evict everything from the CPU write buffers.
715 * clflush appears to be insufficient.
717 wbinvd_on_all_cpus();
719 /* Now we've only seen documents for this magic bit on 855GM,
720 * we hope it exists for the other gen2 chipsets...
722 * Also works as advertised on my 845G.
724 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
725 intel_private.registers+I830_HIC);
727 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
728 if (time_after(jiffies, timeout))
735 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
738 u32 pte_flags = I810_PTE_VALID;
740 if (flags == AGP_USER_CACHED_MEMORY)
741 pte_flags |= I830_PTE_SYSTEM_CACHED;
743 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
746 bool intel_enable_gtt(void)
750 if (INTEL_GTT_GEN == 2) {
753 pci_read_config_word(intel_private.bridge_dev,
754 I830_GMCH_CTRL, &gmch_ctrl);
755 gmch_ctrl |= I830_GMCH_ENABLED;
756 pci_write_config_word(intel_private.bridge_dev,
757 I830_GMCH_CTRL, gmch_ctrl);
759 pci_read_config_word(intel_private.bridge_dev,
760 I830_GMCH_CTRL, &gmch_ctrl);
761 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
762 dev_err(&intel_private.pcidev->dev,
763 "failed to enable the GTT: GMCH_CTRL=%x\n",
769 /* On the resume path we may be adjusting the PGTBL value, so
770 * be paranoid and flush all chipset write buffers...
772 if (INTEL_GTT_GEN >= 3)
773 writel(0, intel_private.registers+GFX_FLSH_CNTL);
775 reg = intel_private.registers+I810_PGETBL_CTL;
776 writel(intel_private.PGETBL_save, reg);
777 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
778 dev_err(&intel_private.pcidev->dev,
779 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
780 readl(reg), intel_private.PGETBL_save);
784 if (INTEL_GTT_GEN >= 3)
785 writel(0, intel_private.registers+GFX_FLSH_CNTL);
789 EXPORT_SYMBOL(intel_enable_gtt);
791 static int i830_setup(void)
793 phys_addr_t reg_addr;
795 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
797 intel_private.registers = ioremap(reg_addr, KB(64));
798 if (!intel_private.registers)
801 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
806 #if IS_ENABLED(CONFIG_AGP_INTEL)
807 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
809 agp_bridge->gatt_table_real = NULL;
810 agp_bridge->gatt_table = NULL;
811 agp_bridge->gatt_bus_addr = 0;
816 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
821 static int intel_fake_agp_configure(void)
823 if (!intel_enable_gtt())
826 intel_private.clear_fake_agp = true;
827 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
833 static bool i830_check_flags(unsigned int flags)
837 case AGP_PHYS_MEMORY:
838 case AGP_USER_CACHED_MEMORY:
839 case AGP_USER_MEMORY:
846 void intel_gtt_insert_page(dma_addr_t addr,
850 intel_private.driver->write_entry(addr, pg, flags);
851 readl(intel_private.gtt + pg);
852 if (intel_private.driver->chipset_flush)
853 intel_private.driver->chipset_flush();
855 EXPORT_SYMBOL(intel_gtt_insert_page);
857 void intel_gtt_insert_sg_entries(struct sg_table *st,
858 unsigned int pg_start,
861 struct scatterlist *sg;
867 /* sg may merge pages, but we have to separate
868 * per-page addr for GTT */
869 for_each_sg(st->sgl, sg, st->nents, i) {
870 len = sg_dma_len(sg) >> PAGE_SHIFT;
871 for (m = 0; m < len; m++) {
872 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
873 intel_private.driver->write_entry(addr, j, flags);
877 readl(intel_private.gtt + j - 1);
878 if (intel_private.driver->chipset_flush)
879 intel_private.driver->chipset_flush();
881 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
883 #if IS_ENABLED(CONFIG_AGP_INTEL)
884 static void intel_gtt_insert_pages(unsigned int first_entry,
885 unsigned int num_entries,
891 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
892 dma_addr_t addr = page_to_phys(pages[i]);
893 intel_private.driver->write_entry(addr,
899 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
900 off_t pg_start, int type)
904 if (intel_private.clear_fake_agp) {
905 int start = intel_private.stolen_size / PAGE_SIZE;
906 int end = intel_private.gtt_mappable_entries;
907 intel_gtt_clear_range(start, end - start);
908 intel_private.clear_fake_agp = false;
911 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
912 return i810_insert_dcache_entries(mem, pg_start, type);
914 if (mem->page_count == 0)
917 if (pg_start + mem->page_count > intel_private.gtt_total_entries)
920 if (type != mem->type)
923 if (!intel_private.driver->check_flags(type))
926 if (!mem->is_flushed)
927 global_cache_flush();
929 if (intel_private.needs_dmar) {
932 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
936 intel_gtt_insert_sg_entries(&st, pg_start, type);
937 mem->sg_list = st.sgl;
938 mem->num_sg = st.nents;
940 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
946 mem->is_flushed = true;
951 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
955 for (i = first_entry; i < (first_entry + num_entries); i++) {
956 intel_private.driver->write_entry(intel_private.scratch_page_dma,
961 EXPORT_SYMBOL(intel_gtt_clear_range);
963 #if IS_ENABLED(CONFIG_AGP_INTEL)
964 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
965 off_t pg_start, int type)
967 if (mem->page_count == 0)
970 intel_gtt_clear_range(pg_start, mem->page_count);
972 if (intel_private.needs_dmar) {
973 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
981 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
984 struct agp_memory *new;
986 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
987 if (pg_count != intel_private.num_dcache_entries)
990 new = agp_create_memory(1);
994 new->type = AGP_DCACHE_MEMORY;
995 new->page_count = pg_count;
996 new->num_scratch_pages = 0;
997 agp_free_page_array(new);
1000 if (type == AGP_PHYS_MEMORY)
1001 return alloc_agpphysmem_i8xx(pg_count, type);
1002 /* always return NULL for other allocation types for now */
1007 static int intel_alloc_chipset_flush_resource(void)
1010 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1011 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1012 pcibios_align_resource, intel_private.bridge_dev);
1017 static void intel_i915_setup_chipset_flush(void)
1022 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1023 if (!(temp & 0x1)) {
1024 intel_alloc_chipset_flush_resource();
1025 intel_private.resource_valid = 1;
1026 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1030 intel_private.resource_valid = 1;
1031 intel_private.ifp_resource.start = temp;
1032 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1033 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1034 /* some BIOSes reserve this area in a pnp some don't */
1036 intel_private.resource_valid = 0;
1040 static void intel_i965_g33_setup_chipset_flush(void)
1042 u32 temp_hi, temp_lo;
1045 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1046 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1048 if (!(temp_lo & 0x1)) {
1050 intel_alloc_chipset_flush_resource();
1052 intel_private.resource_valid = 1;
1053 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1054 upper_32_bits(intel_private.ifp_resource.start));
1055 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1060 l64 = ((u64)temp_hi << 32) | temp_lo;
1062 intel_private.resource_valid = 1;
1063 intel_private.ifp_resource.start = l64;
1064 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1065 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1066 /* some BIOSes reserve this area in a pnp some don't */
1068 intel_private.resource_valid = 0;
1072 static void intel_i9xx_setup_flush(void)
1074 /* return if already configured */
1075 if (intel_private.ifp_resource.start)
1078 if (INTEL_GTT_GEN == 6)
1081 /* setup a resource for this object */
1082 intel_private.ifp_resource.name = "Intel Flush Page";
1083 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1085 /* Setup chipset flush for 915 */
1086 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1087 intel_i965_g33_setup_chipset_flush();
1089 intel_i915_setup_chipset_flush();
1092 if (intel_private.ifp_resource.start)
1093 intel_private.i9xx_flush_page = ioremap(intel_private.ifp_resource.start, PAGE_SIZE);
1094 if (!intel_private.i9xx_flush_page)
1095 dev_err(&intel_private.pcidev->dev,
1096 "can't ioremap flush page - no chipset flushing\n");
1099 static void i9xx_cleanup(void)
1101 if (intel_private.i9xx_flush_page)
1102 iounmap(intel_private.i9xx_flush_page);
1103 if (intel_private.resource_valid)
1104 release_resource(&intel_private.ifp_resource);
1105 intel_private.ifp_resource.start = 0;
1106 intel_private.resource_valid = 0;
1109 static void i9xx_chipset_flush(void)
1112 if (intel_private.i9xx_flush_page)
1113 writel(1, intel_private.i9xx_flush_page);
1116 static void i965_write_entry(dma_addr_t addr,
1122 pte_flags = I810_PTE_VALID;
1123 if (flags == AGP_USER_CACHED_MEMORY)
1124 pte_flags |= I830_PTE_SYSTEM_CACHED;
1126 /* Shift high bits down */
1127 addr |= (addr >> 28) & 0xf0;
1128 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1131 static int i9xx_setup(void)
1133 phys_addr_t reg_addr;
1136 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1138 intel_private.registers = ioremap(reg_addr, size);
1139 if (!intel_private.registers)
1142 switch (INTEL_GTT_GEN) {
1144 intel_private.gtt_phys_addr =
1145 pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1148 intel_private.gtt_phys_addr = reg_addr + MB(2);
1151 intel_private.gtt_phys_addr = reg_addr + KB(512);
1155 intel_i9xx_setup_flush();
1160 #if IS_ENABLED(CONFIG_AGP_INTEL)
1161 static const struct agp_bridge_driver intel_fake_agp_driver = {
1162 .owner = THIS_MODULE,
1163 .size_type = FIXED_APER_SIZE,
1164 .aperture_sizes = intel_fake_agp_sizes,
1165 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1166 .configure = intel_fake_agp_configure,
1167 .fetch_size = intel_fake_agp_fetch_size,
1168 .cleanup = intel_gtt_cleanup,
1169 .agp_enable = intel_fake_agp_enable,
1170 .cache_flush = global_cache_flush,
1171 .create_gatt_table = intel_fake_agp_create_gatt_table,
1172 .free_gatt_table = intel_fake_agp_free_gatt_table,
1173 .insert_memory = intel_fake_agp_insert_entries,
1174 .remove_memory = intel_fake_agp_remove_entries,
1175 .alloc_by_type = intel_fake_agp_alloc_by_type,
1176 .free_by_type = intel_i810_free_by_type,
1177 .agp_alloc_page = agp_generic_alloc_page,
1178 .agp_alloc_pages = agp_generic_alloc_pages,
1179 .agp_destroy_page = agp_generic_destroy_page,
1180 .agp_destroy_pages = agp_generic_destroy_pages,
1184 static const struct intel_gtt_driver i81x_gtt_driver = {
1186 .has_pgtbl_enable = 1,
1187 .dma_mask_size = 32,
1188 .setup = i810_setup,
1189 .cleanup = i810_cleanup,
1190 .check_flags = i830_check_flags,
1191 .write_entry = i810_write_entry,
1193 static const struct intel_gtt_driver i8xx_gtt_driver = {
1195 .has_pgtbl_enable = 1,
1196 .setup = i830_setup,
1197 .cleanup = i830_cleanup,
1198 .write_entry = i830_write_entry,
1199 .dma_mask_size = 32,
1200 .check_flags = i830_check_flags,
1201 .chipset_flush = i830_chipset_flush,
1203 static const struct intel_gtt_driver i915_gtt_driver = {
1205 .has_pgtbl_enable = 1,
1206 .setup = i9xx_setup,
1207 .cleanup = i9xx_cleanup,
1208 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1209 .write_entry = i830_write_entry,
1210 .dma_mask_size = 32,
1211 .check_flags = i830_check_flags,
1212 .chipset_flush = i9xx_chipset_flush,
1214 static const struct intel_gtt_driver g33_gtt_driver = {
1217 .setup = i9xx_setup,
1218 .cleanup = i9xx_cleanup,
1219 .write_entry = i965_write_entry,
1220 .dma_mask_size = 36,
1221 .check_flags = i830_check_flags,
1222 .chipset_flush = i9xx_chipset_flush,
1224 static const struct intel_gtt_driver pineview_gtt_driver = {
1226 .is_pineview = 1, .is_g33 = 1,
1227 .setup = i9xx_setup,
1228 .cleanup = i9xx_cleanup,
1229 .write_entry = i965_write_entry,
1230 .dma_mask_size = 36,
1231 .check_flags = i830_check_flags,
1232 .chipset_flush = i9xx_chipset_flush,
1234 static const struct intel_gtt_driver i965_gtt_driver = {
1236 .has_pgtbl_enable = 1,
1237 .setup = i9xx_setup,
1238 .cleanup = i9xx_cleanup,
1239 .write_entry = i965_write_entry,
1240 .dma_mask_size = 36,
1241 .check_flags = i830_check_flags,
1242 .chipset_flush = i9xx_chipset_flush,
1244 static const struct intel_gtt_driver g4x_gtt_driver = {
1246 .setup = i9xx_setup,
1247 .cleanup = i9xx_cleanup,
1248 .write_entry = i965_write_entry,
1249 .dma_mask_size = 36,
1250 .check_flags = i830_check_flags,
1251 .chipset_flush = i9xx_chipset_flush,
1253 static const struct intel_gtt_driver ironlake_gtt_driver = {
1256 .setup = i9xx_setup,
1257 .cleanup = i9xx_cleanup,
1258 .write_entry = i965_write_entry,
1259 .dma_mask_size = 36,
1260 .check_flags = i830_check_flags,
1261 .chipset_flush = i9xx_chipset_flush,
1264 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1265 * driver and gmch_driver must be non-null, and find_gmch will determine
1266 * which one should be used if a gmch_chip_id is present.
1268 static const struct intel_gtt_driver_description {
1269 unsigned int gmch_chip_id;
1271 const struct intel_gtt_driver *gtt_driver;
1272 } intel_gtt_chipsets[] = {
1273 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1275 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1277 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1279 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1281 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1283 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1285 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1287 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1289 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1291 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1293 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1295 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1297 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1299 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1301 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1303 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1305 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1307 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1309 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1311 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1313 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1315 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1317 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1319 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1321 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1322 &pineview_gtt_driver },
1323 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1324 &pineview_gtt_driver },
1325 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1327 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1329 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1331 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1333 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1335 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1337 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1339 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1340 "HD Graphics", &ironlake_gtt_driver },
1341 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1342 "HD Graphics", &ironlake_gtt_driver },
1346 static int find_gmch(u16 device)
1348 struct pci_dev *gmch_device;
1350 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1351 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1352 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1353 device, gmch_device);
1359 intel_private.pcidev = gmch_device;
1363 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1364 struct agp_bridge_data *bridge)
1368 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1370 if (gpu_pdev->device ==
1371 intel_gtt_chipsets[i].gmch_chip_id) {
1372 intel_private.pcidev = pci_dev_get(gpu_pdev);
1373 intel_private.driver =
1374 intel_gtt_chipsets[i].gtt_driver;
1378 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1379 intel_private.driver =
1380 intel_gtt_chipsets[i].gtt_driver;
1385 if (!intel_private.driver)
1388 #if IS_ENABLED(CONFIG_AGP_INTEL)
1390 if (INTEL_GTT_GEN > 1)
1393 bridge->driver = &intel_fake_agp_driver;
1394 bridge->dev_private_data = &intel_private;
1395 bridge->dev = bridge_pdev;
1401 * Can be called from the fake agp driver but also directly from
1402 * drm/i915.ko. Hence we need to check whether everything is set up
1405 if (intel_private.refcount++)
1408 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1410 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1413 mask = intel_private.driver->dma_mask_size;
1414 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1415 dev_err(&intel_private.pcidev->dev,
1416 "set gfx device dma mask %d-bit failed!\n",
1419 pci_set_consistent_dma_mask(intel_private.pcidev,
1420 DMA_BIT_MASK(mask));
1423 if (intel_gtt_init() != 0) {
1424 intel_gmch_remove();
1431 EXPORT_SYMBOL(intel_gmch_probe);
1433 void intel_gtt_get(u64 *gtt_total,
1434 phys_addr_t *mappable_base,
1435 resource_size_t *mappable_end)
1437 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1438 *mappable_base = intel_private.gma_bus_addr;
1439 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1441 EXPORT_SYMBOL(intel_gtt_get);
1443 void intel_gtt_chipset_flush(void)
1445 if (intel_private.driver->chipset_flush)
1446 intel_private.driver->chipset_flush();
1448 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1450 void intel_gmch_remove(void)
1452 if (--intel_private.refcount)
1455 if (intel_private.scratch_page)
1456 intel_gtt_teardown_scratch_page();
1457 if (intel_private.pcidev)
1458 pci_dev_put(intel_private.pcidev);
1459 if (intel_private.bridge_dev)
1460 pci_dev_put(intel_private.bridge_dev);
1461 intel_private.driver = NULL;
1463 EXPORT_SYMBOL(intel_gmch_remove);
1465 MODULE_AUTHOR("Dave Jones, Various @Intel");
1466 MODULE_LICENSE("GPL and additional rights");