drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pagemap.h>
  22 #include <linux/agp_backend.h>
  23 #include <linux/delay.h>
  24 #include <asm/smp.h>
  25 #include "agp.h"
  26 #include "intel-agp.h"
  27 #include <drm/intel-gtt.h>
  28
  29 /*
  30  * If we have Intel graphics, we're not going to have anything other than
  31  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  32  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
  33  * Only newer chipsets need to bother with this, of course.
  34  */
  35 #ifdef CONFIG_INTEL_IOMMU
  36 #define USE_PCI_DMA_API 1
  37 #else
  38 #define USE_PCI_DMA_API 0
  39 #endif
  40
  41 struct intel_gtt_driver {
  42         unsigned int gen : 8;
  43         unsigned int is_g33 : 1;
  44         unsigned int is_pineview : 1;
  45         unsigned int is_ironlake : 1;
  46         unsigned int has_pgtbl_enable : 1;
  47         unsigned int dma_mask_size : 8;
  48         /* Chipset specific GTT setup */
  49         int (*setup)(void);
  50         /* This should undo anything done in ->setup() save the unmapping
  51          * of the mmio register file, that's done in the generic code. */
  52         void (*cleanup)(void);
  53         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  54         /* Flags is a more or less chipset specific opaque value.
  55          * For chipsets that need to support old ums (non-gem) code, this
  56          * needs to be identical to the various supported agp memory types! */
  57         bool (*check_flags)(unsigned int flags);
  58         void (*chipset_flush)(void);
  59 };
  60
  61 static struct _intel_private {
  62         const struct intel_gtt_driver *driver;
  63         struct pci_dev *pcidev; /* device one */
  64         struct pci_dev *bridge_dev;
  65         u8 __iomem *registers;
  66         phys_addr_t gtt_phys_addr;
  67         u32 PGETBL_save;
  68         u32 __iomem *gtt;               /* I915G */
  69         bool clear_fake_agp; /* on first access via agp, fill with scratch */
  70         int num_dcache_entries;
  71         void __iomem *i9xx_flush_page;
  72         char *i81x_gtt_table;
  73         struct resource ifp_resource;
  74         int resource_valid;
  75         struct page *scratch_page;
  76         phys_addr_t scratch_page_dma;
  77         int refcount;
  78         /* Whether i915 needs to use the dmar apis or not. */
  79         unsigned int needs_dmar : 1;
  80         phys_addr_t gma_bus_addr;
  81         /*  Size of memory reserved for graphics by the BIOS */
  82         unsigned int stolen_size;
  83         /* Total number of gtt entries. */
  84         unsigned int gtt_total_entries;
  85         /* Part of the gtt that is mappable by the cpu, for those chips where
  86          * this is not the full gtt. */
  87         unsigned int gtt_mappable_entries;
  88 } intel_private;
  89
  90 #define INTEL_GTT_GEN   intel_private.driver->gen
  91 #define IS_G33          intel_private.driver->is_g33
  92 #define IS_PINEVIEW     intel_private.driver->is_pineview
  93 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  94 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  95
  96 #if IS_ENABLED(CONFIG_AGP_INTEL)
  97 static int intel_gtt_map_memory(struct page **pages,
  98                                 unsigned int num_entries,
  99                                 struct sg_table *st)
 100 {
 101         struct scatterlist *sg;
 102         int i;
 103
 104         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
 105
 106         if (sg_alloc_table(st, num_entries, GFP_KERNEL))
 107                 goto err;
 108
 109         for_each_sg(st->sgl, sg, num_entries, i)
 110                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
 111
 112         if (!pci_map_sg(intel_private.pcidev,
 113                         st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
 114                 goto err;
 115
 116         return 0;
 117
 118 err:
 119         sg_free_table(st);
 120         return -ENOMEM;
 121 }
 122
 123 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
 124 {
 125         struct sg_table st;
 126         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 127
 128         pci_unmap_sg(intel_private.pcidev, sg_list,
 129                      num_sg, PCI_DMA_BIDIRECTIONAL);
 130
 131         st.sgl = sg_list;
 132         st.orig_nents = st.nents = num_sg;
 133
 134         sg_free_table(&st);
 135 }
 136
 137 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 138 {
 139         return;
 140 }
 141
 142 /* Exists to support ARGB cursors */
 143 static struct page *i8xx_alloc_pages(void)
 144 {
 145         struct page *page;
 146
 147         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 148         if (page == NULL)
 149                 return NULL;
 150
 151         if (set_pages_uc(page, 4) < 0) {
 152                 set_pages_wb(page, 4);
 153                 __free_pages(page, 2);
 154                 return NULL;
 155         }
 156         atomic_inc(&agp_bridge->current_memory_agp);
 157         return page;
 158 }
 159
 160 static void i8xx_destroy_pages(struct page *page)
 161 {
 162         if (page == NULL)
 163                 return;
 164
 165         set_pages_wb(page, 4);
 166         __free_pages(page, 2);
 167         atomic_dec(&agp_bridge->current_memory_agp);
 168 }
 169 #endif
 170
 171 #define I810_GTT_ORDER 4
 172 static int i810_setup(void)
 173 {
 174         phys_addr_t reg_addr;
 175         char *gtt_table;
 176
 177         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 178         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 179         if (gtt_table == NULL)
 180                 return -ENOMEM;
 181         intel_private.i81x_gtt_table = gtt_table;
 182
 183         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 184
 185         intel_private.registers = ioremap(reg_addr, KB(64));
 186         if (!intel_private.registers)
 187                 return -ENOMEM;
 188
 189         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 190                intel_private.registers+I810_PGETBL_CTL);
 191
 192         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 193
 194         if ((readl(intel_private.registers+I810_DRAM_CTL)
 195                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 196                 dev_info(&intel_private.pcidev->dev,
 197                          "detected 4MB dedicated video ram\n");
 198                 intel_private.num_dcache_entries = 1024;
 199         }
 200
 201         return 0;
 202 }
 203
 204 static void i810_cleanup(void)
 205 {
 206         writel(0, intel_private.registers+I810_PGETBL_CTL);
 207         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 208 }
 209
 210 #if IS_ENABLED(CONFIG_AGP_INTEL)
 211 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 212                                       int type)
 213 {
 214         int i;
 215
 216         if ((pg_start + mem->page_count)
 217                         > intel_private.num_dcache_entries)
 218                 return -EINVAL;
 219
 220         if (!mem->is_flushed)
 221                 global_cache_flush();
 222
 223         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 224                 dma_addr_t addr = i << PAGE_SHIFT;
 225                 intel_private.driver->write_entry(addr,
 226                                                   i, type);
 227         }
 228         wmb();
 229
 230         return 0;
 231 }
 232
 233 /*
 234  * The i810/i830 requires a physical address to program its mouse
 235  * pointer into hardware.
 236  * However the Xserver still writes to it through the agp aperture.
 237  */
 238 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 239 {
 240         struct agp_memory *new;
 241         struct page *page;
 242
 243         switch (pg_count) {
 244         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 245                 break;
 246         case 4:
 247                 /* kludge to get 4 physical pages for ARGB cursor */
 248                 page = i8xx_alloc_pages();
 249                 break;
 250         default:
 251                 return NULL;
 252         }
 253
 254         if (page == NULL)
 255                 return NULL;
 256
 257         new = agp_create_memory(pg_count);
 258         if (new == NULL)
 259                 return NULL;
 260
 261         new->pages[0] = page;
 262         if (pg_count == 4) {
 263                 /* kludge to get 4 physical pages for ARGB cursor */
 264                 new->pages[1] = new->pages[0] + 1;
 265                 new->pages[2] = new->pages[1] + 1;
 266                 new->pages[3] = new->pages[2] + 1;
 267         }
 268         new->page_count = pg_count;
 269         new->num_scratch_pages = pg_count;
 270         new->type = AGP_PHYS_MEMORY;
 271         new->physical = page_to_phys(new->pages[0]);
 272         return new;
 273 }
 274
 275 static void intel_i810_free_by_type(struct agp_memory *curr)
 276 {
 277         agp_free_key(curr->key);
 278         if (curr->type == AGP_PHYS_MEMORY) {
 279                 if (curr->page_count == 4)
 280                         i8xx_destroy_pages(curr->pages[0]);
 281                 else {
 282                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 283                                                              AGP_PAGE_DESTROY_UNMAP);
 284                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 285                                                              AGP_PAGE_DESTROY_FREE);
 286                 }
 287                 agp_free_page_array(curr);
 288         }
 289         kfree(curr);
 290 }
 291 #endif
 292
 293 static int intel_gtt_setup_scratch_page(void)
 294 {
 295         struct page *page;
 296         dma_addr_t dma_addr;
 297
 298         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 299         if (page == NULL)
 300                 return -ENOMEM;
 301         set_pages_uc(page, 1);
 302
 303         if (intel_private.needs_dmar) {
 304                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 305                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 306                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) {
 307                         __free_page(page);
 308                         return -EINVAL;
 309                 }
 310
 311                 intel_private.scratch_page_dma = dma_addr;
 312         } else
 313                 intel_private.scratch_page_dma = page_to_phys(page);
 314
 315         intel_private.scratch_page = page;
 316
 317         return 0;
 318 }
 319
 320 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 321                              unsigned int flags)
 322 {
 323         u32 pte_flags = I810_PTE_VALID;
 324
 325         switch (flags) {
 326         case AGP_DCACHE_MEMORY:
 327                 pte_flags |= I810_PTE_LOCAL;
 328                 break;
 329         case AGP_USER_CACHED_MEMORY:
 330                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 331                 break;
 332         }
 333
 334         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 335 }
 336
 337 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
 338         {32, 8192, 3},
 339         {64, 16384, 4},
 340         {128, 32768, 5},
 341         {256, 65536, 6},
 342         {512, 131072, 7},
 343 };
 344
 345 static unsigned int intel_gtt_stolen_size(void)
 346 {
 347         u16 gmch_ctrl;
 348         u8 rdct;
 349         int local = 0;
 350         static const int ddt[4] = { 0, 16, 32, 64 };
 351         unsigned int stolen_size = 0;
 352
 353         if (INTEL_GTT_GEN == 1)
 354                 return 0; /* no stolen mem on i81x */
 355
 356         pci_read_config_word(intel_private.bridge_dev,
 357                              I830_GMCH_CTRL, &gmch_ctrl);
 358
 359         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 360             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 361                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 362                 case I830_GMCH_GMS_STOLEN_512:
 363                         stolen_size = KB(512);
 364                         break;
 365                 case I830_GMCH_GMS_STOLEN_1024:
 366                         stolen_size = MB(1);
 367                         break;
 368                 case I830_GMCH_GMS_STOLEN_8192:
 369                         stolen_size = MB(8);
 370                         break;
 371                 case I830_GMCH_GMS_LOCAL:
 372                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 373                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 374                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 375                         local = 1;
 376                         break;
 377                 default:
 378                         stolen_size = 0;
 379                         break;
 380                 }
 381         } else {
 382                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 383                 case I855_GMCH_GMS_STOLEN_1M:
 384                         stolen_size = MB(1);
 385                         break;
 386                 case I855_GMCH_GMS_STOLEN_4M:
 387                         stolen_size = MB(4);
 388                         break;
 389                 case I855_GMCH_GMS_STOLEN_8M:
 390                         stolen_size = MB(8);
 391                         break;
 392                 case I855_GMCH_GMS_STOLEN_16M:
 393                         stolen_size = MB(16);
 394                         break;
 395                 case I855_GMCH_GMS_STOLEN_32M:
 396                         stolen_size = MB(32);
 397                         break;
 398                 case I915_GMCH_GMS_STOLEN_48M:
 399                         stolen_size = MB(48);
 400                         break;
 401                 case I915_GMCH_GMS_STOLEN_64M:
 402                         stolen_size = MB(64);
 403                         break;
 404                 case G33_GMCH_GMS_STOLEN_128M:
 405                         stolen_size = MB(128);
 406                         break;
 407                 case G33_GMCH_GMS_STOLEN_256M:
 408                         stolen_size = MB(256);
 409                         break;
 410                 case INTEL_GMCH_GMS_STOLEN_96M:
 411                         stolen_size = MB(96);
 412                         break;
 413                 case INTEL_GMCH_GMS_STOLEN_160M:
 414                         stolen_size = MB(160);
 415                         break;
 416                 case INTEL_GMCH_GMS_STOLEN_224M:
 417                         stolen_size = MB(224);
 418                         break;
 419                 case INTEL_GMCH_GMS_STOLEN_352M:
 420                         stolen_size = MB(352);
 421                         break;
 422                 default:
 423                         stolen_size = 0;
 424                         break;
 425                 }
 426         }
 427
 428         if (stolen_size > 0) {
 429                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 430                        stolen_size / KB(1), local ? "local" : "stolen");
 431         } else {
 432                 dev_info(&intel_private.bridge_dev->dev,
 433                        "no pre-allocated video memory detected\n");
 434                 stolen_size = 0;
 435         }
 436
 437         return stolen_size;
 438 }
 439
 440 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 441 {
 442         u32 pgetbl_ctl, pgetbl_ctl2;
 443
 444         /* ensure that ppgtt is disabled */
 445         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 446         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 447         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 448
 449         /* write the new ggtt size */
 450         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 451         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 452         pgetbl_ctl |= size_flag;
 453         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 454 }
 455
 456 static unsigned int i965_gtt_total_entries(void)
 457 {
 458         int size;
 459         u32 pgetbl_ctl;
 460         u16 gmch_ctl;
 461
 462         pci_read_config_word(intel_private.bridge_dev,
 463                              I830_GMCH_CTRL, &gmch_ctl);
 464
 465         if (INTEL_GTT_GEN == 5) {
 466                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 467                 case G4x_GMCH_SIZE_1M:
 468                 case G4x_GMCH_SIZE_VT_1M:
 469                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 470                         break;
 471                 case G4x_GMCH_SIZE_VT_1_5M:
 472                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 473                         break;
 474                 case G4x_GMCH_SIZE_2M:
 475                 case G4x_GMCH_SIZE_VT_2M:
 476                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 477                         break;
 478                 }
 479         }
 480
 481         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 482
 483         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 484         case I965_PGETBL_SIZE_128KB:
 485                 size = KB(128);
 486                 break;
 487         case I965_PGETBL_SIZE_256KB:
 488                 size = KB(256);
 489                 break;
 490         case I965_PGETBL_SIZE_512KB:
 491                 size = KB(512);
 492                 break;
 493         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 494         case I965_PGETBL_SIZE_1MB:
 495                 size = KB(1024);
 496                 break;
 497         case I965_PGETBL_SIZE_2MB:
 498                 size = KB(2048);
 499                 break;
 500         case I965_PGETBL_SIZE_1_5MB:
 501                 size = KB(1024 + 512);
 502                 break;
 503         default:
 504                 dev_info(&intel_private.pcidev->dev,
 505                          "unknown page table size, assuming 512KB\n");
 506                 size = KB(512);
 507         }
 508
 509         return size/4;
 510 }
 511
 512 static unsigned int intel_gtt_total_entries(void)
 513 {
 514         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 515                 return i965_gtt_total_entries();
 516         else {
 517                 /* On previous hardware, the GTT size was just what was
 518                  * required to map the aperture.
 519                  */
 520                 return intel_private.gtt_mappable_entries;
 521         }
 522 }
 523
 524 static unsigned int intel_gtt_mappable_entries(void)
 525 {
 526         unsigned int aperture_size;
 527
 528         if (INTEL_GTT_GEN == 1) {
 529                 u32 smram_miscc;
 530
 531                 pci_read_config_dword(intel_private.bridge_dev,
 532                                       I810_SMRAM_MISCC, &smram_miscc);
 533
 534                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 535                                 == I810_GFX_MEM_WIN_32M)
 536                         aperture_size = MB(32);
 537                 else
 538                         aperture_size = MB(64);
 539         } else if (INTEL_GTT_GEN == 2) {
 540                 u16 gmch_ctrl;
 541
 542                 pci_read_config_word(intel_private.bridge_dev,
 543                                      I830_GMCH_CTRL, &gmch_ctrl);
 544
 545                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 546                         aperture_size = MB(64);
 547                 else
 548                         aperture_size = MB(128);
 549         } else {
 550                 /* 9xx supports large sizes, just look at the length */
 551                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 552         }
 553
 554         return aperture_size >> PAGE_SHIFT;
 555 }
 556
 557 static void intel_gtt_teardown_scratch_page(void)
 558 {
 559         set_pages_wb(intel_private.scratch_page, 1);
 560         pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
 561                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 562         __free_page(intel_private.scratch_page);
 563 }
 564
 565 static void intel_gtt_cleanup(void)
 566 {
 567         intel_private.driver->cleanup();
 568
 569         iounmap(intel_private.gtt);
 570         iounmap(intel_private.registers);
 571
 572         intel_gtt_teardown_scratch_page();
 573 }
 574
 575 /* Certain Gen5 chipsets require require idling the GPU before
 576  * unmapping anything from the GTT when VT-d is enabled.
 577  */
 578 static inline int needs_ilk_vtd_wa(void)
 579 {
 580 #ifdef CONFIG_INTEL_IOMMU
 581         const unsigned short gpu_devid = intel_private.pcidev->device;
 582
 583         /* Query intel_iommu to see if we need the workaround. Presumably that
 584          * was loaded first.
 585          */
 586         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||
 587              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
 588              intel_iommu_gfx_mapped)
 589                 return 1;
 590 #endif
 591         return 0;
 592 }
 593
 594 static bool intel_gtt_can_wc(void)
 595 {
 596         if (INTEL_GTT_GEN <= 2)
 597                 return false;
 598
 599         if (INTEL_GTT_GEN >= 6)
 600                 return false;
 601
 602         /* Reports of major corruption with ILK vt'd enabled */
 603         if (needs_ilk_vtd_wa())
 604                 return false;
 605
 606         return true;
 607 }
 608
 609 static int intel_gtt_init(void)
 610 {
 611         u32 gtt_map_size;
 612         int ret, bar;
 613
 614         ret = intel_private.driver->setup();
 615         if (ret != 0)
 616                 return ret;
 617
 618         intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
 619         intel_private.gtt_total_entries = intel_gtt_total_entries();
 620
 621         /* save the PGETBL reg for resume */
 622         intel_private.PGETBL_save =
 623                 readl(intel_private.registers+I810_PGETBL_CTL)
 624                         & ~I810_PGETBL_ENABLED;
 625         /* we only ever restore the register when enabling the PGTBL... */
 626         if (HAS_PGTBL_EN)
 627                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 628
 629         dev_info(&intel_private.bridge_dev->dev,
 630                         "detected gtt size: %dK total, %dK mappable\n",
 631                         intel_private.gtt_total_entries * 4,
 632                         intel_private.gtt_mappable_entries * 4);
 633
 634         gtt_map_size = intel_private.gtt_total_entries * 4;
 635
 636         intel_private.gtt = NULL;
 637         if (intel_gtt_can_wc())
 638                 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
 639                                                gtt_map_size);
 640         if (intel_private.gtt == NULL)
 641                 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
 642                                             gtt_map_size);
 643         if (intel_private.gtt == NULL) {
 644                 intel_private.driver->cleanup();
 645                 iounmap(intel_private.registers);
 646                 return -ENOMEM;
 647         }
 648
 649 #if IS_ENABLED(CONFIG_AGP_INTEL)
 650         global_cache_flush();   /* FIXME: ? */
 651 #endif
 652
 653         intel_private.stolen_size = intel_gtt_stolen_size();
 654
 655         intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
 656
 657         ret = intel_gtt_setup_scratch_page();
 658         if (ret != 0) {
 659                 intel_gtt_cleanup();
 660                 return ret;
 661         }
 662
 663         if (INTEL_GTT_GEN <= 2)
 664                 bar = I810_GMADR_BAR;
 665         else
 666                 bar = I915_GMADR_BAR;
 667
 668         intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
 669         return 0;
 670 }
 671
 672 #if IS_ENABLED(CONFIG_AGP_INTEL)
 673 static int intel_fake_agp_fetch_size(void)
 674 {
 675         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 676         unsigned int aper_size;
 677         int i;
 678
 679         aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
 680
 681         for (i = 0; i < num_sizes; i++) {
 682                 if (aper_size == intel_fake_agp_sizes[i].size) {
 683                         agp_bridge->current_size =
 684                                 (void *) (intel_fake_agp_sizes + i);
 685                         return aper_size;
 686                 }
 687         }
 688
 689         return 0;
 690 }
 691 #endif
 692
 693 static void i830_cleanup(void)
 694 {
 695 }
 696
 697 /* The chipset_flush interface needs to get data that has already been
 698  * flushed out of the CPU all the way out to main memory, because the GPU
 699  * doesn't snoop those buffers.
 700  *
 701  * The 8xx series doesn't have the same lovely interface for flushing the
 702  * chipset write buffers that the later chips do. According to the 865
 703  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 704  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 705  * that it'll push whatever was in there out.  It appears to work.
 706  */
 707 static void i830_chipset_flush(void)
 708 {
 709         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 710
 711         /* Forcibly evict everything from the CPU write buffers.
 712          * clflush appears to be insufficient.
 713          */
 714         wbinvd_on_all_cpus();
 715
 716         /* Now we've only seen documents for this magic bit on 855GM,
 717          * we hope it exists for the other gen2 chipsets...
 718          *
 719          * Also works as advertised on my 845G.
 720          */
 721         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
 722                intel_private.registers+I830_HIC);
 723
 724         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
 725                 if (time_after(jiffies, timeout))
 726                         break;
 727
 728                 udelay(50);
 729         }
 730 }
 731
 732 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 733                              unsigned int flags)
 734 {
 735         u32 pte_flags = I810_PTE_VALID;
 736
 737         if (flags ==  AGP_USER_CACHED_MEMORY)
 738                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 739
 740         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
 741 }
 742
 743 bool intel_enable_gtt(void)
 744 {
 745         u8 __iomem *reg;
 746
 747         if (INTEL_GTT_GEN == 2) {
 748                 u16 gmch_ctrl;
 749
 750                 pci_read_config_word(intel_private.bridge_dev,
 751                                      I830_GMCH_CTRL, &gmch_ctrl);
 752                 gmch_ctrl |= I830_GMCH_ENABLED;
 753                 pci_write_config_word(intel_private.bridge_dev,
 754                                       I830_GMCH_CTRL, gmch_ctrl);
 755
 756                 pci_read_config_word(intel_private.bridge_dev,
 757                                      I830_GMCH_CTRL, &gmch_ctrl);
 758                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 759                         dev_err(&intel_private.pcidev->dev,
 760                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 761                                 gmch_ctrl);
 762                         return false;
 763                 }
 764         }
 765
 766         /* On the resume path we may be adjusting the PGTBL value, so
 767          * be paranoid and flush all chipset write buffers...
 768          */
 769         if (INTEL_GTT_GEN >= 3)
 770                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 771
 772         reg = intel_private.registers+I810_PGETBL_CTL;
 773         writel(intel_private.PGETBL_save, reg);
 774         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 775                 dev_err(&intel_private.pcidev->dev,
 776                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 777                         readl(reg), intel_private.PGETBL_save);
 778                 return false;
 779         }
 780
 781         if (INTEL_GTT_GEN >= 3)
 782                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 783
 784         return true;
 785 }
 786 EXPORT_SYMBOL(intel_enable_gtt);
 787
 788 static int i830_setup(void)
 789 {
 790         phys_addr_t reg_addr;
 791
 792         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 793
 794         intel_private.registers = ioremap(reg_addr, KB(64));
 795         if (!intel_private.registers)
 796                 return -ENOMEM;
 797
 798         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 799
 800         return 0;
 801 }
 802
 803 #if IS_ENABLED(CONFIG_AGP_INTEL)
 804 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 805 {
 806         agp_bridge->gatt_table_real = NULL;
 807         agp_bridge->gatt_table = NULL;
 808         agp_bridge->gatt_bus_addr = 0;
 809
 810         return 0;
 811 }
 812
 813 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 814 {
 815         return 0;
 816 }
 817
 818 static int intel_fake_agp_configure(void)
 819 {
 820         if (!intel_enable_gtt())
 821             return -EIO;
 822
 823         intel_private.clear_fake_agp = true;
 824         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
 825
 826         return 0;
 827 }
 828 #endif
 829
 830 static bool i830_check_flags(unsigned int flags)
 831 {
 832         switch (flags) {
 833         case 0:
 834         case AGP_PHYS_MEMORY:
 835         case AGP_USER_CACHED_MEMORY:
 836         case AGP_USER_MEMORY:
 837                 return true;
 838         }
 839
 840         return false;
 841 }
 842
 843 void intel_gtt_insert_sg_entries(struct sg_table *st,
 844                                  unsigned int pg_start,
 845                                  unsigned int flags)
 846 {
 847         struct scatterlist *sg;
 848         unsigned int len, m;
 849         int i, j;
 850
 851         j = pg_start;
 852
 853         /* sg may merge pages, but we have to separate
 854          * per-page addr for GTT */
 855         for_each_sg(st->sgl, sg, st->nents, i) {
 856                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 857                 for (m = 0; m < len; m++) {
 858                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 859                         intel_private.driver->write_entry(addr, j, flags);
 860                         j++;
 861                 }
 862         }
 863         wmb();
 864         if (intel_private.driver->chipset_flush)
 865                 intel_private.driver->chipset_flush();
 866 }
 867 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 868
 869 #if IS_ENABLED(CONFIG_AGP_INTEL)
 870 static void intel_gtt_insert_pages(unsigned int first_entry,
 871                                    unsigned int num_entries,
 872                                    struct page **pages,
 873                                    unsigned int flags)
 874 {
 875         int i, j;
 876
 877         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
 878                 dma_addr_t addr = page_to_phys(pages[i]);
 879                 intel_private.driver->write_entry(addr,
 880                                                   j, flags);
 881         }
 882         wmb();
 883 }
 884
 885 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 886                                          off_t pg_start, int type)
 887 {
 888         int ret = -EINVAL;
 889
 890         if (intel_private.clear_fake_agp) {
 891                 int start = intel_private.stolen_size / PAGE_SIZE;
 892                 int end = intel_private.gtt_mappable_entries;
 893                 intel_gtt_clear_range(start, end - start);
 894                 intel_private.clear_fake_agp = false;
 895         }
 896
 897         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 898                 return i810_insert_dcache_entries(mem, pg_start, type);
 899
 900         if (mem->page_count == 0)
 901                 goto out;
 902
 903         if (pg_start + mem->page_count > intel_private.gtt_total_entries)
 904                 goto out_err;
 905
 906         if (type != mem->type)
 907                 goto out_err;
 908
 909         if (!intel_private.driver->check_flags(type))
 910                 goto out_err;
 911
 912         if (!mem->is_flushed)
 913                 global_cache_flush();
 914
 915         if (intel_private.needs_dmar) {
 916                 struct sg_table st;
 917
 918                 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
 919                 if (ret != 0)
 920                         return ret;
 921
 922                 intel_gtt_insert_sg_entries(&st, pg_start, type);
 923                 mem->sg_list = st.sgl;
 924                 mem->num_sg = st.nents;
 925         } else
 926                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
 927                                        type);
 928
 929 out:
 930         ret = 0;
 931 out_err:
 932         mem->is_flushed = true;
 933         return ret;
 934 }
 935 #endif
 936
 937 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 938 {
 939         unsigned int i;
 940
 941         for (i = first_entry; i < (first_entry + num_entries); i++) {
 942                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
 943                                                   i, 0);
 944         }
 945         wmb();
 946 }
 947 EXPORT_SYMBOL(intel_gtt_clear_range);
 948
 949 #if IS_ENABLED(CONFIG_AGP_INTEL)
 950 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
 951                                          off_t pg_start, int type)
 952 {
 953         if (mem->page_count == 0)
 954                 return 0;
 955
 956         intel_gtt_clear_range(pg_start, mem->page_count);
 957
 958         if (intel_private.needs_dmar) {
 959                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
 960                 mem->sg_list = NULL;
 961                 mem->num_sg = 0;
 962         }
 963
 964         return 0;
 965 }
 966
 967 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
 968                                                        int type)
 969 {
 970         struct agp_memory *new;
 971
 972         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
 973                 if (pg_count != intel_private.num_dcache_entries)
 974                         return NULL;
 975
 976                 new = agp_create_memory(1);
 977                 if (new == NULL)
 978                         return NULL;
 979
 980                 new->type = AGP_DCACHE_MEMORY;
 981                 new->page_count = pg_count;
 982                 new->num_scratch_pages = 0;
 983                 agp_free_page_array(new);
 984                 return new;
 985         }
 986         if (type == AGP_PHYS_MEMORY)
 987                 return alloc_agpphysmem_i8xx(pg_count, type);
 988         /* always return NULL for other allocation types for now */
 989         return NULL;
 990 }
 991 #endif
 992
 993 static int intel_alloc_chipset_flush_resource(void)
 994 {
 995         int ret;
 996         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 997                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 998                                      pcibios_align_resource, intel_private.bridge_dev);
 999
1000         return ret;
1001 }
1002
1003 static void intel_i915_setup_chipset_flush(void)
1004 {
1005         int ret;
1006         u32 temp;
1007
1008         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1009         if (!(temp & 0x1)) {
1010                 intel_alloc_chipset_flush_resource();
1011                 intel_private.resource_valid = 1;
1012                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1013         } else {
1014                 temp &= ~1;
1015
1016                 intel_private.resource_valid = 1;
1017                 intel_private.ifp_resource.start = temp;
1018                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1019                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1020                 /* some BIOSes reserve this area in a pnp some don't */
1021                 if (ret)
1022                         intel_private.resource_valid = 0;
1023         }
1024 }
1025
1026 static void intel_i965_g33_setup_chipset_flush(void)
1027 {
1028         u32 temp_hi, temp_lo;
1029         int ret;
1030
1031         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1032         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1033
1034         if (!(temp_lo & 0x1)) {
1035
1036                 intel_alloc_chipset_flush_resource();
1037
1038                 intel_private.resource_valid = 1;
1039                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1040                         upper_32_bits(intel_private.ifp_resource.start));
1041                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1042         } else {
1043                 u64 l64;
1044
1045                 temp_lo &= ~0x1;
1046                 l64 = ((u64)temp_hi << 32) | temp_lo;
1047
1048                 intel_private.resource_valid = 1;
1049                 intel_private.ifp_resource.start = l64;
1050                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1051                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1052                 /* some BIOSes reserve this area in a pnp some don't */
1053                 if (ret)
1054                         intel_private.resource_valid = 0;
1055         }
1056 }
1057
1058 static void intel_i9xx_setup_flush(void)
1059 {
1060         /* return if already configured */
1061         if (intel_private.ifp_resource.start)
1062                 return;
1063
1064         if (INTEL_GTT_GEN == 6)
1065                 return;
1066
1067         /* setup a resource for this object */
1068         intel_private.ifp_resource.name = "Intel Flush Page";
1069         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1070
1071         /* Setup chipset flush for 915 */
1072         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1073                 intel_i965_g33_setup_chipset_flush();
1074         } else {
1075                 intel_i915_setup_chipset_flush();
1076         }
1077
1078         if (intel_private.ifp_resource.start)
1079                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1080         if (!intel_private.i9xx_flush_page)
1081                 dev_err(&intel_private.pcidev->dev,
1082                         "can't ioremap flush page - no chipset flushing\n");
1083 }
1084
1085 static void i9xx_cleanup(void)
1086 {
1087         if (intel_private.i9xx_flush_page)
1088                 iounmap(intel_private.i9xx_flush_page);
1089         if (intel_private.resource_valid)
1090                 release_resource(&intel_private.ifp_resource);
1091         intel_private.ifp_resource.start = 0;
1092         intel_private.resource_valid = 0;
1093 }
1094
1095 static void i9xx_chipset_flush(void)
1096 {
1097         if (intel_private.i9xx_flush_page)
1098                 writel(1, intel_private.i9xx_flush_page);
1099 }
1100
1101 static void i965_write_entry(dma_addr_t addr,
1102                              unsigned int entry,
1103                              unsigned int flags)
1104 {
1105         u32 pte_flags;
1106
1107         pte_flags = I810_PTE_VALID;
1108         if (flags == AGP_USER_CACHED_MEMORY)
1109                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1110
1111         /* Shift high bits down */
1112         addr |= (addr >> 28) & 0xf0;
1113         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1114 }
1115
1116 static int i9xx_setup(void)
1117 {
1118         phys_addr_t reg_addr;
1119         int size = KB(512);
1120
1121         reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1122
1123         intel_private.registers = ioremap(reg_addr, size);
1124         if (!intel_private.registers)
1125                 return -ENOMEM;
1126
1127         switch (INTEL_GTT_GEN) {
1128         case 3:
1129                 intel_private.gtt_phys_addr =
1130                         pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1131                 break;
1132         case 5:
1133                 intel_private.gtt_phys_addr = reg_addr + MB(2);
1134                 break;
1135         default:
1136                 intel_private.gtt_phys_addr = reg_addr + KB(512);
1137                 break;
1138         }
1139
1140         intel_i9xx_setup_flush();
1141
1142         return 0;
1143 }
1144
1145 #if IS_ENABLED(CONFIG_AGP_INTEL)
1146 static const struct agp_bridge_driver intel_fake_agp_driver = {
1147         .owner                  = THIS_MODULE,
1148         .size_type              = FIXED_APER_SIZE,
1149         .aperture_sizes         = intel_fake_agp_sizes,
1150         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1151         .configure              = intel_fake_agp_configure,
1152         .fetch_size             = intel_fake_agp_fetch_size,
1153         .cleanup                = intel_gtt_cleanup,
1154         .agp_enable             = intel_fake_agp_enable,
1155         .cache_flush            = global_cache_flush,
1156         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1157         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1158         .insert_memory          = intel_fake_agp_insert_entries,
1159         .remove_memory          = intel_fake_agp_remove_entries,
1160         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1161         .free_by_type           = intel_i810_free_by_type,
1162         .agp_alloc_page         = agp_generic_alloc_page,
1163         .agp_alloc_pages        = agp_generic_alloc_pages,
1164         .agp_destroy_page       = agp_generic_destroy_page,
1165         .agp_destroy_pages      = agp_generic_destroy_pages,
1166 };
1167 #endif
1168
1169 static const struct intel_gtt_driver i81x_gtt_driver = {
1170         .gen = 1,
1171         .has_pgtbl_enable = 1,
1172         .dma_mask_size = 32,
1173         .setup = i810_setup,
1174         .cleanup = i810_cleanup,
1175         .check_flags = i830_check_flags,
1176         .write_entry = i810_write_entry,
1177 };
1178 static const struct intel_gtt_driver i8xx_gtt_driver = {
1179         .gen = 2,
1180         .has_pgtbl_enable = 1,
1181         .setup = i830_setup,
1182         .cleanup = i830_cleanup,
1183         .write_entry = i830_write_entry,
1184         .dma_mask_size = 32,
1185         .check_flags = i830_check_flags,
1186         .chipset_flush = i830_chipset_flush,
1187 };
1188 static const struct intel_gtt_driver i915_gtt_driver = {
1189         .gen = 3,
1190         .has_pgtbl_enable = 1,
1191         .setup = i9xx_setup,
1192         .cleanup = i9xx_cleanup,
1193         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1194         .write_entry = i830_write_entry,
1195         .dma_mask_size = 32,
1196         .check_flags = i830_check_flags,
1197         .chipset_flush = i9xx_chipset_flush,
1198 };
1199 static const struct intel_gtt_driver g33_gtt_driver = {
1200         .gen = 3,
1201         .is_g33 = 1,
1202         .setup = i9xx_setup,
1203         .cleanup = i9xx_cleanup,
1204         .write_entry = i965_write_entry,
1205         .dma_mask_size = 36,
1206         .check_flags = i830_check_flags,
1207         .chipset_flush = i9xx_chipset_flush,
1208 };
1209 static const struct intel_gtt_driver pineview_gtt_driver = {
1210         .gen = 3,
1211         .is_pineview = 1, .is_g33 = 1,
1212         .setup = i9xx_setup,
1213         .cleanup = i9xx_cleanup,
1214         .write_entry = i965_write_entry,
1215         .dma_mask_size = 36,
1216         .check_flags = i830_check_flags,
1217         .chipset_flush = i9xx_chipset_flush,
1218 };
1219 static const struct intel_gtt_driver i965_gtt_driver = {
1220         .gen = 4,
1221         .has_pgtbl_enable = 1,
1222         .setup = i9xx_setup,
1223         .cleanup = i9xx_cleanup,
1224         .write_entry = i965_write_entry,
1225         .dma_mask_size = 36,
1226         .check_flags = i830_check_flags,
1227         .chipset_flush = i9xx_chipset_flush,
1228 };
1229 static const struct intel_gtt_driver g4x_gtt_driver = {
1230         .gen = 5,
1231         .setup = i9xx_setup,
1232         .cleanup = i9xx_cleanup,
1233         .write_entry = i965_write_entry,
1234         .dma_mask_size = 36,
1235         .check_flags = i830_check_flags,
1236         .chipset_flush = i9xx_chipset_flush,
1237 };
1238 static const struct intel_gtt_driver ironlake_gtt_driver = {
1239         .gen = 5,
1240         .is_ironlake = 1,
1241         .setup = i9xx_setup,
1242         .cleanup = i9xx_cleanup,
1243         .write_entry = i965_write_entry,
1244         .dma_mask_size = 36,
1245         .check_flags = i830_check_flags,
1246         .chipset_flush = i9xx_chipset_flush,
1247 };
1248
1249 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1250  * driver and gmch_driver must be non-null, and find_gmch will determine
1251  * which one should be used if a gmch_chip_id is present.
1252  */
1253 static const struct intel_gtt_driver_description {
1254         unsigned int gmch_chip_id;
1255         char *name;
1256         const struct intel_gtt_driver *gtt_driver;
1257 } intel_gtt_chipsets[] = {
1258         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1259                 &i81x_gtt_driver},
1260         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1261                 &i81x_gtt_driver},
1262         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1263                 &i81x_gtt_driver},
1264         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1265                 &i81x_gtt_driver},
1266         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1267                 &i8xx_gtt_driver},
1268         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1269                 &i8xx_gtt_driver},
1270         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1271                 &i8xx_gtt_driver},
1272         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1273                 &i8xx_gtt_driver},
1274         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1275                 &i8xx_gtt_driver},
1276         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1277                 &i915_gtt_driver },
1278         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1279                 &i915_gtt_driver },
1280         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1281                 &i915_gtt_driver },
1282         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1283                 &i915_gtt_driver },
1284         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1285                 &i915_gtt_driver },
1286         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1287                 &i915_gtt_driver },
1288         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1289                 &i965_gtt_driver },
1290         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1291                 &i965_gtt_driver },
1292         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1293                 &i965_gtt_driver },
1294         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1295                 &i965_gtt_driver },
1296         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1297                 &i965_gtt_driver },
1298         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1299                 &i965_gtt_driver },
1300         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1301                 &g33_gtt_driver },
1302         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1303                 &g33_gtt_driver },
1304         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1305                 &g33_gtt_driver },
1306         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1307                 &pineview_gtt_driver },
1308         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1309                 &pineview_gtt_driver },
1310         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1311                 &g4x_gtt_driver },
1312         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1313                 &g4x_gtt_driver },
1314         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1315                 &g4x_gtt_driver },
1316         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1317                 &g4x_gtt_driver },
1318         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1319                 &g4x_gtt_driver },
1320         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1321                 &g4x_gtt_driver },
1322         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1323                 &g4x_gtt_driver },
1324         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1325             "HD Graphics", &ironlake_gtt_driver },
1326         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1327             "HD Graphics", &ironlake_gtt_driver },
1328         { 0, NULL, NULL }
1329 };
1330
1331 static int find_gmch(u16 device)
1332 {
1333         struct pci_dev *gmch_device;
1334
1335         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1336         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1337                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1338                                              device, gmch_device);
1339         }
1340
1341         if (!gmch_device)
1342                 return 0;
1343
1344         intel_private.pcidev = gmch_device;
1345         return 1;
1346 }
1347
1348 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1349                      struct agp_bridge_data *bridge)
1350 {
1351         int i, mask;
1352
1353         /*
1354          * Can be called from the fake agp driver but also directly from
1355          * drm/i915.ko. Hence we need to check whether everything is set up
1356          * already.
1357          */
1358         if (intel_private.driver) {
1359                 intel_private.refcount++;
1360                 return 1;
1361         }
1362
1363         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1364                 if (gpu_pdev) {
1365                         if (gpu_pdev->device ==
1366                             intel_gtt_chipsets[i].gmch_chip_id) {
1367                                 intel_private.pcidev = pci_dev_get(gpu_pdev);
1368                                 intel_private.driver =
1369                                         intel_gtt_chipsets[i].gtt_driver;
1370
1371                                 break;
1372                         }
1373                 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1374                         intel_private.driver =
1375                                 intel_gtt_chipsets[i].gtt_driver;
1376                         break;
1377                 }
1378         }
1379
1380         if (!intel_private.driver)
1381                 return 0;
1382
1383         intel_private.refcount++;
1384
1385 #if IS_ENABLED(CONFIG_AGP_INTEL)
1386         if (bridge) {
1387                 bridge->driver = &intel_fake_agp_driver;
1388                 bridge->dev_private_data = &intel_private;
1389                 bridge->dev = bridge_pdev;
1390         }
1391 #endif
1392
1393         intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1394
1395         dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1396
1397         mask = intel_private.driver->dma_mask_size;
1398         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1399                 dev_err(&intel_private.pcidev->dev,
1400                         "set gfx device dma mask %d-bit failed!\n", mask);
1401         else
1402                 pci_set_consistent_dma_mask(intel_private.pcidev,
1403                                             DMA_BIT_MASK(mask));
1404
1405         if (intel_gtt_init() != 0) {
1406                 intel_gmch_remove();
1407
1408                 return 0;
1409         }
1410
1411         return 1;
1412 }
1413 EXPORT_SYMBOL(intel_gmch_probe);
1414
1415 void intel_gtt_get(u64 *gtt_total, size_t *stolen_size,
1416                    phys_addr_t *mappable_base, u64 *mappable_end)
1417 {
1418         *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1419         *stolen_size = intel_private.stolen_size;
1420         *mappable_base = intel_private.gma_bus_addr;
1421         *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1422 }
1423 EXPORT_SYMBOL(intel_gtt_get);
1424
1425 void intel_gtt_chipset_flush(void)
1426 {
1427         if (intel_private.driver->chipset_flush)
1428                 intel_private.driver->chipset_flush();
1429 }
1430 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1431
1432 void intel_gmch_remove(void)
1433 {
1434         if (--intel_private.refcount)
1435                 return;
1436
1437         if (intel_private.pcidev)
1438                 pci_dev_put(intel_private.pcidev);
1439         if (intel_private.bridge_dev)
1440                 pci_dev_put(intel_private.bridge_dev);
1441         intel_private.driver = NULL;
1442 }
1443 EXPORT_SYMBOL(intel_gmch_remove);
1444
1445 MODULE_AUTHOR("Dave Jones, Various @Intel");
1446 MODULE_LICENSE("GPL and additional rights");