1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_domain.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/slab.h>
18 #include <linux/iopoll.h>
20 #include <linux/platform_data/ti-sysc.h>
22 #include <dt-bindings/bus/ti-sysc.h>
24 #define MAX_MODULE_SOFTRESET_WAIT 10000
26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
47 #define SYSC_IDLEMODE_MASK 3
48 #define SYSC_CLOCKACTIVITY_MASK 3
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
57 * @mdata: ti-sysc to hwmod translation data for a module
58 * @clocks: clocks used by the interconnect target module
59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
61 * @rsts: resets used by the interconnect target module
62 * @legacy_mode: configured for legacy mode if set
63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
65 * @cookie: data used by legacy platform callbacks
66 * @name: name if available
67 * @revision: interconnect target module revision
68 * @enabled: sysc runtime enabled status
69 * @needs_resume: runtime resume needed on resume from suspend
70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
73 * @pre_reset_quirk: module specific pre-reset quirk
74 * @post_reset_quirk: module specific post-reset quirk
75 * @reset_done_quirk: module specific reset done quirk
76 * @module_enable_quirk: module specific enable quirk
77 * @module_disable_quirk: module specific disable quirk
78 * @module_unlock_quirk: module specific sysconfig unlock quirk
79 * @module_lock_quirk: module specific sysconfig lock quirk
85 void __iomem *module_va;
86 int offsets[SYSC_MAX_REGS];
87 struct ti_sysc_module_data *mdata;
89 const char **clock_roles;
91 struct reset_control *rsts;
92 const char *legacy_mode;
93 const struct sysc_capabilities *cap;
94 struct sysc_config cfg;
95 struct ti_sysc_cookie cookie;
98 unsigned int enabled:1;
99 unsigned int needs_resume:1;
100 unsigned int child_needs_resume:1;
101 struct delayed_work idle_work;
102 void (*pre_reset_quirk)(struct sysc *sysc);
103 void (*post_reset_quirk)(struct sysc *sysc);
104 void (*reset_done_quirk)(struct sysc *sysc);
105 void (*module_enable_quirk)(struct sysc *sysc);
106 void (*module_disable_quirk)(struct sysc *sysc);
107 void (*module_unlock_quirk)(struct sysc *sysc);
108 void (*module_lock_quirk)(struct sysc *sysc);
111 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
114 static void sysc_write(struct sysc *ddata, int offset, u32 value)
116 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
117 writew_relaxed(value & 0xffff, ddata->module_va + offset);
119 /* Only i2c revision has LO and HI register with stride of 4 */
120 if (ddata->offsets[SYSC_REVISION] >= 0 &&
121 offset == ddata->offsets[SYSC_REVISION]) {
122 u16 hi = value >> 16;
124 writew_relaxed(hi, ddata->module_va + offset + 4);
130 writel_relaxed(value, ddata->module_va + offset);
133 static u32 sysc_read(struct sysc *ddata, int offset)
135 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
138 val = readw_relaxed(ddata->module_va + offset);
140 /* Only i2c revision has LO and HI register with stride of 4 */
141 if (ddata->offsets[SYSC_REVISION] >= 0 &&
142 offset == ddata->offsets[SYSC_REVISION]) {
143 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
151 return readl_relaxed(ddata->module_va + offset);
154 static bool sysc_opt_clks_needed(struct sysc *ddata)
156 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
159 static u32 sysc_read_revision(struct sysc *ddata)
161 int offset = ddata->offsets[SYSC_REVISION];
166 return sysc_read(ddata, offset);
169 static u32 sysc_read_sysconfig(struct sysc *ddata)
171 int offset = ddata->offsets[SYSC_SYSCONFIG];
176 return sysc_read(ddata, offset);
179 static u32 sysc_read_sysstatus(struct sysc *ddata)
181 int offset = ddata->offsets[SYSC_SYSSTATUS];
186 return sysc_read(ddata, offset);
189 /* Poll on reset status */
190 static int sysc_wait_softreset(struct sysc *ddata)
192 u32 sysc_mask, syss_done, rstval;
193 int syss_offset, error = 0;
195 if (ddata->cap->regbits->srst_shift < 0)
198 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
199 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
201 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
204 syss_done = ddata->cfg.syss_mask;
206 if (syss_offset >= 0) {
207 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
208 rstval, (rstval & ddata->cfg.syss_mask) ==
209 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
211 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
212 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
213 rstval, !(rstval & sysc_mask),
214 100, MAX_MODULE_SOFTRESET_WAIT);
220 static int sysc_add_named_clock_from_child(struct sysc *ddata,
222 const char *optfck_name)
224 struct device_node *np = ddata->dev->of_node;
225 struct device_node *child;
226 struct clk_lookup *cl;
235 /* Does the clock alias already exist? */
236 clock = of_clk_get_by_name(np, n);
237 if (!IS_ERR(clock)) {
243 child = of_get_next_available_child(np, NULL);
247 clock = devm_get_clk_from_child(ddata->dev, child, name);
249 return PTR_ERR(clock);
252 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
253 * limit for clk_get(). If cl ever needs to be freed, it should be done
254 * with clkdev_drop().
256 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
261 cl->dev_id = dev_name(ddata->dev);
270 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
272 const char *optfck_name;
275 if (ddata->nr_clocks < SYSC_OPTFCK0)
276 index = SYSC_OPTFCK0;
278 index = ddata->nr_clocks;
283 optfck_name = clock_names[index];
285 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
289 ddata->clock_roles[index] = optfck_name;
295 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
297 int error, i, index = -ENODEV;
299 if (!strncmp(clock_names[SYSC_FCK], name, 3))
301 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
305 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
306 if (!ddata->clocks[i]) {
314 dev_err(ddata->dev, "clock %s not added\n", name);
318 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
319 if (IS_ERR(ddata->clocks[index])) {
320 dev_err(ddata->dev, "clock get error for %s: %li\n",
321 name, PTR_ERR(ddata->clocks[index]));
323 return PTR_ERR(ddata->clocks[index]);
326 error = clk_prepare(ddata->clocks[index]);
328 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
337 static int sysc_get_clocks(struct sysc *ddata)
339 struct device_node *np = ddata->dev->of_node;
340 struct property *prop;
342 int nr_fck = 0, nr_ick = 0, i, error = 0;
344 ddata->clock_roles = devm_kcalloc(ddata->dev,
346 sizeof(*ddata->clock_roles),
348 if (!ddata->clock_roles)
351 of_property_for_each_string(np, "clock-names", prop, name) {
352 if (!strncmp(clock_names[SYSC_FCK], name, 3))
354 if (!strncmp(clock_names[SYSC_ICK], name, 3))
356 ddata->clock_roles[ddata->nr_clocks] = name;
360 if (ddata->nr_clocks < 1)
363 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
364 error = sysc_init_ext_opt_clock(ddata, NULL);
369 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
370 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
375 if (nr_fck > 1 || nr_ick > 1) {
376 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
381 /* Always add a slot for main clocks fck and ick even if unused */
387 ddata->clocks = devm_kcalloc(ddata->dev,
388 ddata->nr_clocks, sizeof(*ddata->clocks),
393 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
394 const char *name = ddata->clock_roles[i];
399 error = sysc_get_one_clock(ddata, name);
407 static int sysc_enable_main_clocks(struct sysc *ddata)
415 for (i = 0; i < SYSC_OPTFCK0; i++) {
416 clock = ddata->clocks[i];
418 /* Main clocks may not have ick */
419 if (IS_ERR_OR_NULL(clock))
422 error = clk_enable(clock);
430 for (i--; i >= 0; i--) {
431 clock = ddata->clocks[i];
433 /* Main clocks may not have ick */
434 if (IS_ERR_OR_NULL(clock))
443 static void sysc_disable_main_clocks(struct sysc *ddata)
451 for (i = 0; i < SYSC_OPTFCK0; i++) {
452 clock = ddata->clocks[i];
453 if (IS_ERR_OR_NULL(clock))
460 static int sysc_enable_opt_clocks(struct sysc *ddata)
465 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
468 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
469 clock = ddata->clocks[i];
471 /* Assume no holes for opt clocks */
472 if (IS_ERR_OR_NULL(clock))
475 error = clk_enable(clock);
483 for (i--; i >= 0; i--) {
484 clock = ddata->clocks[i];
485 if (IS_ERR_OR_NULL(clock))
494 static void sysc_disable_opt_clocks(struct sysc *ddata)
499 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
502 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
503 clock = ddata->clocks[i];
505 /* Assume no holes for opt clocks */
506 if (IS_ERR_OR_NULL(clock))
513 static void sysc_clkdm_deny_idle(struct sysc *ddata)
515 struct ti_sysc_platform_data *pdata;
517 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
520 pdata = dev_get_platdata(ddata->dev);
521 if (pdata && pdata->clkdm_deny_idle)
522 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
525 static void sysc_clkdm_allow_idle(struct sysc *ddata)
527 struct ti_sysc_platform_data *pdata;
529 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
532 pdata = dev_get_platdata(ddata->dev);
533 if (pdata && pdata->clkdm_allow_idle)
534 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
538 * sysc_init_resets - init rstctrl reset line if configured
539 * @ddata: device driver data
541 * See sysc_rstctrl_reset_deassert().
543 static int sysc_init_resets(struct sysc *ddata)
546 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
547 if (IS_ERR(ddata->rsts))
548 return PTR_ERR(ddata->rsts);
554 * sysc_parse_and_check_child_range - parses module IO region from ranges
555 * @ddata: device driver data
557 * In general we only need rev, syss, and sysc registers and not the whole
558 * module range. But we do want the offsets for these registers from the
559 * module base. This allows us to check them against the legacy hwmod
560 * platform data. Let's also check the ranges are configured properly.
562 static int sysc_parse_and_check_child_range(struct sysc *ddata)
564 struct device_node *np = ddata->dev->of_node;
565 const __be32 *ranges;
566 u32 nr_addr, nr_size;
569 ranges = of_get_property(np, "ranges", &len);
571 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
576 len /= sizeof(*ranges);
579 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
584 error = of_property_read_u32(np, "#address-cells", &nr_addr);
588 error = of_property_read_u32(np, "#size-cells", &nr_size);
592 if (nr_addr != 1 || nr_size != 1) {
593 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
599 ddata->module_pa = of_translate_address(np, ranges++);
600 ddata->module_size = be32_to_cpup(ranges);
605 /* Interconnect instances to probe before l4_per instances */
606 static struct resource early_bus_ranges[] = {
608 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
609 /* omap4/5 and dra7 l4_cfg */
610 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
612 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
613 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
614 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
617 static atomic_t sysc_defer = ATOMIC_INIT(10);
620 * sysc_defer_non_critical - defer non_critical interconnect probing
621 * @ddata: device driver data
623 * We want to probe l4_cfg and l4_wkup interconnect instances before any
624 * l4_per instances as l4_per instances depend on resources on l4_cfg and
625 * l4_wkup interconnects.
627 static int sysc_defer_non_critical(struct sysc *ddata)
629 struct resource *res;
632 if (!atomic_read(&sysc_defer))
635 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
636 res = &early_bus_ranges[i];
637 if (ddata->module_pa >= res->start &&
638 ddata->module_pa <= res->end) {
639 atomic_set(&sysc_defer, 0);
645 atomic_dec_if_positive(&sysc_defer);
647 return -EPROBE_DEFER;
650 static struct device_node *stdout_path;
652 static void sysc_init_stdout_path(struct sysc *ddata)
654 struct device_node *np = NULL;
657 if (IS_ERR(stdout_path))
663 np = of_find_node_by_path("/chosen");
667 uart = of_get_property(np, "stdout-path", NULL);
671 np = of_find_node_by_path(uart);
680 stdout_path = ERR_PTR(-ENODEV);
683 static void sysc_check_quirk_stdout(struct sysc *ddata,
684 struct device_node *np)
686 sysc_init_stdout_path(ddata);
687 if (np != stdout_path)
690 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
691 SYSC_QUIRK_NO_RESET_ON_INIT;
695 * sysc_check_one_child - check child configuration
696 * @ddata: device driver data
697 * @np: child device node
699 * Let's avoid messy situations where we have new interconnect target
700 * node but children have "ti,hwmods". These belong to the interconnect
701 * target node and are managed by this driver.
703 static void sysc_check_one_child(struct sysc *ddata,
704 struct device_node *np)
708 name = of_get_property(np, "ti,hwmods", NULL);
710 dev_warn(ddata->dev, "really a child ti,hwmods property?");
712 sysc_check_quirk_stdout(ddata, np);
713 sysc_parse_dts_quirks(ddata, np, true);
716 static void sysc_check_children(struct sysc *ddata)
718 struct device_node *child;
720 for_each_child_of_node(ddata->dev->of_node, child)
721 sysc_check_one_child(ddata, child);
725 * So far only I2C uses 16-bit read access with clockactivity with revision
726 * in two registers with stride of 4. We can detect this based on the rev
727 * register size to configure things far enough to be able to properly read
728 * the revision register.
730 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
732 if (resource_size(res) == 8)
733 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
737 * sysc_parse_one - parses the interconnect target module registers
738 * @ddata: device driver data
739 * @reg: register to parse
741 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
743 struct resource *res;
750 name = reg_names[reg];
756 res = platform_get_resource_byname(to_platform_device(ddata->dev),
757 IORESOURCE_MEM, name);
759 ddata->offsets[reg] = -ENODEV;
764 ddata->offsets[reg] = res->start - ddata->module_pa;
765 if (reg == SYSC_REVISION)
766 sysc_check_quirk_16bit(ddata, res);
771 static int sysc_parse_registers(struct sysc *ddata)
775 for (i = 0; i < SYSC_MAX_REGS; i++) {
776 error = sysc_parse_one(ddata, i);
785 * sysc_check_registers - check for misconfigured register overlaps
786 * @ddata: device driver data
788 static int sysc_check_registers(struct sysc *ddata)
790 int i, j, nr_regs = 0, nr_matches = 0;
792 for (i = 0; i < SYSC_MAX_REGS; i++) {
793 if (ddata->offsets[i] < 0)
796 if (ddata->offsets[i] > (ddata->module_size - 4)) {
797 dev_err(ddata->dev, "register outside module range");
802 for (j = 0; j < SYSC_MAX_REGS; j++) {
803 if (ddata->offsets[j] < 0)
806 if (ddata->offsets[i] == ddata->offsets[j])
812 if (nr_matches > nr_regs) {
813 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
814 nr_regs, nr_matches);
823 * syc_ioremap - ioremap register space for the interconnect target module
824 * @ddata: device driver data
826 * Note that the interconnect target module registers can be anywhere
827 * within the interconnect target module range. For example, SGX has
828 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
829 * has them at offset 0x1200 in the CPSW_WR child. Usually the
830 * the interconnect target module registers are at the beginning of
831 * the module range though.
833 static int sysc_ioremap(struct sysc *ddata)
837 if (ddata->offsets[SYSC_REVISION] < 0 &&
838 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
839 ddata->offsets[SYSC_SYSSTATUS] < 0) {
840 size = ddata->module_size;
842 size = max3(ddata->offsets[SYSC_REVISION],
843 ddata->offsets[SYSC_SYSCONFIG],
844 ddata->offsets[SYSC_SYSSTATUS]);
849 if ((size + sizeof(u32)) > ddata->module_size)
850 size = ddata->module_size;
853 ddata->module_va = devm_ioremap(ddata->dev,
856 if (!ddata->module_va)
863 * sysc_map_and_check_registers - ioremap and check device registers
864 * @ddata: device driver data
866 static int sysc_map_and_check_registers(struct sysc *ddata)
870 error = sysc_parse_and_check_child_range(ddata);
874 error = sysc_defer_non_critical(ddata);
878 sysc_check_children(ddata);
880 error = sysc_parse_registers(ddata);
884 error = sysc_ioremap(ddata);
888 error = sysc_check_registers(ddata);
896 * sysc_show_rev - read and show interconnect target module revision
897 * @bufp: buffer to print the information to
898 * @ddata: device driver data
900 static int sysc_show_rev(char *bufp, struct sysc *ddata)
904 if (ddata->offsets[SYSC_REVISION] < 0)
905 return sprintf(bufp, ":NA");
907 len = sprintf(bufp, ":%08x", ddata->revision);
912 static int sysc_show_reg(struct sysc *ddata,
913 char *bufp, enum sysc_registers reg)
915 if (ddata->offsets[reg] < 0)
916 return sprintf(bufp, ":NA");
918 return sprintf(bufp, ":%x", ddata->offsets[reg]);
921 static int sysc_show_name(char *bufp, struct sysc *ddata)
926 return sprintf(bufp, ":%s", ddata->name);
930 * sysc_show_registers - show information about interconnect target module
931 * @ddata: device driver data
933 static void sysc_show_registers(struct sysc *ddata)
939 for (i = 0; i < SYSC_MAX_REGS; i++)
940 bufp += sysc_show_reg(ddata, bufp, i);
942 bufp += sysc_show_rev(bufp, ddata);
943 bufp += sysc_show_name(bufp, ddata);
945 dev_dbg(ddata->dev, "%llx:%x%s\n",
946 ddata->module_pa, ddata->module_size,
951 * sysc_write_sysconfig - handle sysconfig quirks for register write
952 * @ddata: device driver data
953 * @value: register value
955 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
957 if (ddata->module_unlock_quirk)
958 ddata->module_unlock_quirk(ddata);
960 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
962 if (ddata->module_lock_quirk)
963 ddata->module_lock_quirk(ddata);
966 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
967 #define SYSC_CLOCACT_ICK 2
969 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
970 static int sysc_enable_module(struct device *dev)
973 const struct sysc_regbits *regbits;
974 u32 reg, idlemodes, best_mode;
977 ddata = dev_get_drvdata(dev);
980 * Some modules like DSS reset automatically on idle. Enable optional
981 * reset clocks and wait for OCP softreset to complete.
983 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
984 error = sysc_enable_opt_clocks(ddata);
987 "Optional clocks failed for enable: %i\n",
992 error = sysc_wait_softreset(ddata);
994 dev_warn(ddata->dev, "OCP softreset timed out\n");
995 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
996 sysc_disable_opt_clocks(ddata);
999 * Some subsystem private interconnects, like DSS top level module,
1000 * need only the automatic OCP softreset handling with no sysconfig
1001 * register bits to configure.
1003 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1006 regbits = ddata->cap->regbits;
1007 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1010 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1011 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1012 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1014 if (regbits->clkact_shift >= 0 &&
1015 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1016 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1018 /* Set SIDLE mode */
1019 idlemodes = ddata->cfg.sidlemodes;
1020 if (!idlemodes || regbits->sidle_shift < 0)
1023 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1024 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1025 best_mode = SYSC_IDLE_NO;
1027 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1028 if (best_mode > SYSC_IDLE_MASK) {
1029 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1034 if (regbits->enwkup_shift >= 0 &&
1035 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1036 reg |= BIT(regbits->enwkup_shift);
1039 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1040 reg |= best_mode << regbits->sidle_shift;
1041 sysc_write_sysconfig(ddata, reg);
1044 /* Set MIDLE mode */
1045 idlemodes = ddata->cfg.midlemodes;
1046 if (!idlemodes || regbits->midle_shift < 0)
1049 best_mode = fls(ddata->cfg.midlemodes) - 1;
1050 if (best_mode > SYSC_IDLE_MASK) {
1051 dev_err(dev, "%s: invalid midlemode\n", __func__);
1055 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1056 best_mode = SYSC_IDLE_NO;
1058 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1059 reg |= best_mode << regbits->midle_shift;
1060 sysc_write_sysconfig(ddata, reg);
1063 /* Autoidle bit must enabled separately if available */
1064 if (regbits->autoidle_shift >= 0 &&
1065 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1066 reg |= 1 << regbits->autoidle_shift;
1067 sysc_write_sysconfig(ddata, reg);
1070 /* Flush posted write */
1071 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1073 if (ddata->module_enable_quirk)
1074 ddata->module_enable_quirk(ddata);
1079 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1081 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1082 *best_mode = SYSC_IDLE_SMART_WKUP;
1083 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1084 *best_mode = SYSC_IDLE_SMART;
1085 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1086 *best_mode = SYSC_IDLE_FORCE;
1093 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1094 static int sysc_disable_module(struct device *dev)
1097 const struct sysc_regbits *regbits;
1098 u32 reg, idlemodes, best_mode;
1101 ddata = dev_get_drvdata(dev);
1102 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1105 if (ddata->module_disable_quirk)
1106 ddata->module_disable_quirk(ddata);
1108 regbits = ddata->cap->regbits;
1109 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1111 /* Set MIDLE mode */
1112 idlemodes = ddata->cfg.midlemodes;
1113 if (!idlemodes || regbits->midle_shift < 0)
1116 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1118 dev_err(dev, "%s: invalid midlemode\n", __func__);
1122 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1123 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1124 best_mode = SYSC_IDLE_FORCE;
1126 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1127 reg |= best_mode << regbits->midle_shift;
1128 sysc_write_sysconfig(ddata, reg);
1131 /* Set SIDLE mode */
1132 idlemodes = ddata->cfg.sidlemodes;
1133 if (!idlemodes || regbits->sidle_shift < 0)
1136 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1137 best_mode = SYSC_IDLE_FORCE;
1139 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1141 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1146 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1147 reg |= best_mode << regbits->sidle_shift;
1148 if (regbits->autoidle_shift >= 0 &&
1149 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1150 reg |= 1 << regbits->autoidle_shift;
1151 sysc_write_sysconfig(ddata, reg);
1153 /* Flush posted write */
1154 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1159 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1162 struct ti_sysc_platform_data *pdata;
1165 pdata = dev_get_platdata(ddata->dev);
1169 if (!pdata->idle_module)
1172 error = pdata->idle_module(dev, &ddata->cookie);
1174 dev_err(dev, "%s: could not idle: %i\n",
1177 reset_control_assert(ddata->rsts);
1182 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1185 struct ti_sysc_platform_data *pdata;
1188 reset_control_deassert(ddata->rsts);
1190 pdata = dev_get_platdata(ddata->dev);
1194 if (!pdata->enable_module)
1197 error = pdata->enable_module(dev, &ddata->cookie);
1199 dev_err(dev, "%s: could not enable: %i\n",
1205 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1210 ddata = dev_get_drvdata(dev);
1212 if (!ddata->enabled)
1215 sysc_clkdm_deny_idle(ddata);
1217 if (ddata->legacy_mode) {
1218 error = sysc_runtime_suspend_legacy(dev, ddata);
1220 goto err_allow_idle;
1222 error = sysc_disable_module(dev);
1224 goto err_allow_idle;
1227 sysc_disable_main_clocks(ddata);
1229 if (sysc_opt_clks_needed(ddata))
1230 sysc_disable_opt_clocks(ddata);
1232 ddata->enabled = false;
1235 reset_control_assert(ddata->rsts);
1237 sysc_clkdm_allow_idle(ddata);
1242 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1247 ddata = dev_get_drvdata(dev);
1253 sysc_clkdm_deny_idle(ddata);
1255 reset_control_deassert(ddata->rsts);
1257 if (sysc_opt_clks_needed(ddata)) {
1258 error = sysc_enable_opt_clocks(ddata);
1260 goto err_allow_idle;
1263 error = sysc_enable_main_clocks(ddata);
1265 goto err_opt_clocks;
1267 if (ddata->legacy_mode) {
1268 error = sysc_runtime_resume_legacy(dev, ddata);
1270 goto err_main_clocks;
1272 error = sysc_enable_module(dev);
1274 goto err_main_clocks;
1277 ddata->enabled = true;
1279 sysc_clkdm_allow_idle(ddata);
1284 sysc_disable_main_clocks(ddata);
1286 if (sysc_opt_clks_needed(ddata))
1287 sysc_disable_opt_clocks(ddata);
1289 sysc_clkdm_allow_idle(ddata);
1294 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1298 ddata = dev_get_drvdata(dev);
1300 if (ddata->cfg.quirks &
1301 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1304 return pm_runtime_force_suspend(dev);
1307 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1311 ddata = dev_get_drvdata(dev);
1313 if (ddata->cfg.quirks &
1314 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1317 return pm_runtime_force_resume(dev);
1320 static const struct dev_pm_ops sysc_pm_ops = {
1321 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1322 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1323 sysc_runtime_resume,
1327 /* Module revision register based quirks */
1328 struct sysc_revision_quirk {
1339 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1340 optrev_val, optrevmask, optquirkmask) \
1342 .name = (optname), \
1343 .base = (optbase), \
1344 .rev_offset = (optrev), \
1345 .sysc_offset = (optsysc), \
1346 .syss_offset = (optsyss), \
1347 .revision = (optrev_val), \
1348 .revision_mask = (optrevmask), \
1349 .quirks = (optquirkmask), \
1352 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1353 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1354 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1355 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1356 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1357 SYSC_QUIRK_LEGACY_IDLE),
1358 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1359 SYSC_QUIRK_LEGACY_IDLE),
1360 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1361 SYSC_QUIRK_LEGACY_IDLE),
1362 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
1363 SYSC_QUIRK_LEGACY_IDLE),
1364 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
1365 SYSC_QUIRK_LEGACY_IDLE),
1366 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1368 /* Some timers on omap4 and later */
1369 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff,
1371 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff,
1373 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1374 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1375 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1376 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1377 /* Uarts on omap4 and later */
1378 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1379 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1380 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1381 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1383 /* Quirks that need to be set based on the module address */
1384 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1385 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1386 SYSC_QUIRK_SWSUP_SIDLE),
1388 /* Quirks that need to be set based on detected module */
1389 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1390 SYSC_MODULE_QUIRK_AESS),
1391 /* Errata i893 handling for dra7 dcan1 and 2 */
1392 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1393 SYSC_QUIRK_CLKDM_NOAUTO),
1394 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1395 SYSC_QUIRK_CLKDM_NOAUTO),
1396 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1397 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1398 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1399 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1400 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1401 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1402 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1403 SYSC_QUIRK_CLKDM_NOAUTO),
1404 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1405 SYSC_QUIRK_CLKDM_NOAUTO),
1406 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1407 SYSC_QUIRK_OPT_CLKS_NEEDED),
1408 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1409 SYSC_MODULE_QUIRK_HDQ1W),
1410 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1411 SYSC_MODULE_QUIRK_HDQ1W),
1412 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1413 SYSC_MODULE_QUIRK_I2C),
1414 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1415 SYSC_MODULE_QUIRK_I2C),
1416 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1417 SYSC_MODULE_QUIRK_I2C),
1418 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1419 SYSC_MODULE_QUIRK_I2C),
1420 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1421 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1422 SYSC_MODULE_QUIRK_SGX),
1423 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1424 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1425 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1426 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1427 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1428 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1429 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1430 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1431 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1432 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1433 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1434 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1435 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1436 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1437 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1438 SYSC_MODULE_QUIRK_WDT),
1439 /* Watchdog on am3 and am4 */
1440 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1441 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1444 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1445 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1446 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1447 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1448 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1450 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1451 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1452 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1453 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1454 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1455 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1456 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1457 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1458 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1459 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1460 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1461 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1462 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1463 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1464 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1465 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1466 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1467 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1468 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1469 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 0),
1470 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1471 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1472 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1473 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1474 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1475 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1476 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1477 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1478 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1479 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1480 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1481 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1482 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1483 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1484 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1485 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1486 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1487 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1488 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1489 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1490 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1491 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1492 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1493 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1494 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1495 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1496 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1497 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1498 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1499 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1500 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1501 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1502 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1503 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1508 * Early quirks based on module base and register offsets only that are
1509 * needed before the module revision can be read
1511 static void sysc_init_early_quirks(struct sysc *ddata)
1513 const struct sysc_revision_quirk *q;
1516 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1517 q = &sysc_revision_quirks[i];
1522 if (q->base != ddata->module_pa)
1525 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1528 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1531 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1534 ddata->name = q->name;
1535 ddata->cfg.quirks |= q->quirks;
1539 /* Quirks that also consider the revision register value */
1540 static void sysc_init_revision_quirks(struct sysc *ddata)
1542 const struct sysc_revision_quirk *q;
1545 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1546 q = &sysc_revision_quirks[i];
1548 if (q->base && q->base != ddata->module_pa)
1551 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1554 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1557 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1560 if (q->revision == ddata->revision ||
1561 (q->revision & q->revision_mask) ==
1562 (ddata->revision & q->revision_mask)) {
1563 ddata->name = q->name;
1564 ddata->cfg.quirks |= q->quirks;
1569 /* 1-wire needs module's internal clocks enabled for reset */
1570 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1572 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1575 val = sysc_read(ddata, offset);
1577 sysc_write(ddata, offset, val);
1580 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1581 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1583 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1585 sysc_write(ddata, offset, 1);
1588 /* I2C needs to be disabled for reset */
1589 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1594 /* I2C_CON, omap2/3 is different from omap4 and later */
1595 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1601 val = sysc_read(ddata, offset);
1606 sysc_write(ddata, offset, val);
1609 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1611 sysc_clk_quirk_i2c(ddata, false);
1614 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1616 sysc_clk_quirk_i2c(ddata, true);
1619 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1620 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1622 u32 val, kick0_val = 0, kick1_val = 0;
1623 unsigned long flags;
1627 kick0_val = 0x83e70b13;
1628 kick1_val = 0x95a4f1e0;
1631 local_irq_save(flags);
1632 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1633 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1634 !(val & BIT(0)), 100, 50);
1636 dev_warn(ddata->dev, "rtc busy timeout\n");
1637 /* Now we have ~15 microseconds to read/write various registers */
1638 sysc_write(ddata, 0x6c, kick0_val);
1639 sysc_write(ddata, 0x70, kick1_val);
1640 local_irq_restore(flags);
1643 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1645 sysc_quirk_rtc(ddata, false);
1648 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1650 sysc_quirk_rtc(ddata, true);
1653 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1654 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1656 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1657 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1659 sysc_write(ddata, offset, val);
1662 /* Watchdog timer needs a disable sequence after reset */
1663 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1665 int wps, spr, error;
1671 sysc_write(ddata, spr, 0xaaaa);
1672 error = readl_poll_timeout(ddata->module_va + wps, val,
1674 MAX_MODULE_SOFTRESET_WAIT);
1676 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1678 sysc_write(ddata, spr, 0x5555);
1679 error = readl_poll_timeout(ddata->module_va + wps, val,
1681 MAX_MODULE_SOFTRESET_WAIT);
1683 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1686 static void sysc_init_module_quirks(struct sysc *ddata)
1688 if (ddata->legacy_mode || !ddata->name)
1691 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1692 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1697 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1698 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1699 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
1704 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1705 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1707 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1708 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1709 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1714 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1715 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1717 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1718 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1719 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1723 static int sysc_clockdomain_init(struct sysc *ddata)
1725 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1726 struct clk *fck = NULL, *ick = NULL;
1729 if (!pdata || !pdata->init_clockdomain)
1732 switch (ddata->nr_clocks) {
1734 ick = ddata->clocks[SYSC_ICK];
1737 fck = ddata->clocks[SYSC_FCK];
1743 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1744 if (!error || error == -ENODEV)
1751 * Note that pdata->init_module() typically does a reset first. After
1752 * pdata->init_module() is done, PM runtime can be used for the interconnect
1755 static int sysc_legacy_init(struct sysc *ddata)
1757 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1760 if (!pdata || !pdata->init_module)
1763 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1764 if (error == -EEXIST)
1771 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1772 * @ddata: device driver data
1773 * @reset: reset before deassert
1775 * A module can have both OCP softreset control and external rstctrl.
1776 * If more complicated rstctrl resets are needed, please handle these
1777 * directly from the child device driver and map only the module reset
1778 * for the parent interconnect target module device.
1780 * Automatic reset of the module on init can be skipped with the
1781 * "ti,no-reset-on-init" device tree property.
1783 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1791 error = reset_control_assert(ddata->rsts);
1796 reset_control_deassert(ddata->rsts);
1802 * Note that the caller must ensure the interconnect target module is enabled
1803 * before calling reset. Otherwise reset will not complete.
1805 static int sysc_reset(struct sysc *ddata)
1807 int sysc_offset, sysc_val, error;
1810 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1812 if (ddata->legacy_mode || sysc_offset < 0 ||
1813 ddata->cap->regbits->srst_shift < 0 ||
1814 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1817 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1819 if (ddata->pre_reset_quirk)
1820 ddata->pre_reset_quirk(ddata);
1822 sysc_val = sysc_read_sysconfig(ddata);
1823 sysc_val |= sysc_mask;
1824 sysc_write(ddata, sysc_offset, sysc_val);
1826 if (ddata->cfg.srst_udelay)
1827 usleep_range(ddata->cfg.srst_udelay,
1828 ddata->cfg.srst_udelay * 2);
1830 if (ddata->post_reset_quirk)
1831 ddata->post_reset_quirk(ddata);
1833 error = sysc_wait_softreset(ddata);
1835 dev_warn(ddata->dev, "OCP softreset timed out\n");
1837 if (ddata->reset_done_quirk)
1838 ddata->reset_done_quirk(ddata);
1844 * At this point the module is configured enough to read the revision but
1845 * module may not be completely configured yet to use PM runtime. Enable
1846 * all clocks directly during init to configure the quirks needed for PM
1847 * runtime based on the revision register.
1849 static int sysc_init_module(struct sysc *ddata)
1852 bool manage_clocks = true;
1854 error = sysc_rstctrl_reset_deassert(ddata, false);
1858 if (ddata->cfg.quirks &
1859 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1860 manage_clocks = false;
1862 error = sysc_clockdomain_init(ddata);
1866 sysc_clkdm_deny_idle(ddata);
1869 * Always enable clocks. The bootloader may or may not have enabled
1870 * the related clocks.
1872 error = sysc_enable_opt_clocks(ddata);
1876 error = sysc_enable_main_clocks(ddata);
1878 goto err_opt_clocks;
1880 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1881 error = sysc_rstctrl_reset_deassert(ddata, true);
1883 goto err_main_clocks;
1886 ddata->revision = sysc_read_revision(ddata);
1887 sysc_init_revision_quirks(ddata);
1888 sysc_init_module_quirks(ddata);
1890 if (ddata->legacy_mode) {
1891 error = sysc_legacy_init(ddata);
1893 goto err_main_clocks;
1896 if (!ddata->legacy_mode) {
1897 error = sysc_enable_module(ddata->dev);
1899 goto err_main_clocks;
1902 error = sysc_reset(ddata);
1904 dev_err(ddata->dev, "Reset failed with %d\n", error);
1906 if (!ddata->legacy_mode && manage_clocks)
1907 sysc_disable_module(ddata->dev);
1911 sysc_disable_main_clocks(ddata);
1913 /* No re-enable of clockdomain autoidle to prevent module autoidle */
1914 if (manage_clocks) {
1915 sysc_disable_opt_clocks(ddata);
1916 sysc_clkdm_allow_idle(ddata);
1922 static int sysc_init_sysc_mask(struct sysc *ddata)
1924 struct device_node *np = ddata->dev->of_node;
1928 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1932 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1937 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1940 struct device_node *np = ddata->dev->of_node;
1941 struct property *prop;
1945 of_property_for_each_u32(np, name, prop, p, val) {
1946 if (val >= SYSC_NR_IDLEMODES) {
1947 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1950 *idlemodes |= (1 << val);
1956 static int sysc_init_idlemodes(struct sysc *ddata)
1960 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1965 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1974 * Only some devices on omap4 and later have SYSCONFIG reset done
1975 * bit. We can detect this if there is no SYSSTATUS at all, or the
1976 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1977 * have multiple bits for the child devices like OHCI and EHCI.
1978 * Depends on SYSC being parsed first.
1980 static int sysc_init_syss_mask(struct sysc *ddata)
1982 struct device_node *np = ddata->dev->of_node;
1986 error = of_property_read_u32(np, "ti,syss-mask", &val);
1988 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1989 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1990 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1991 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1996 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1997 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1999 ddata->cfg.syss_mask = val;
2005 * Many child device drivers need to have fck and opt clocks available
2006 * to get the clock rate for device internal configuration etc.
2008 static int sysc_child_add_named_clock(struct sysc *ddata,
2009 struct device *child,
2013 struct clk_lookup *l;
2019 clk = clk_get(child, name);
2026 clk = clk_get(ddata->dev, name);
2030 l = clkdev_create(clk, name, dev_name(child));
2039 static int sysc_child_add_clocks(struct sysc *ddata,
2040 struct device *child)
2044 for (i = 0; i < ddata->nr_clocks; i++) {
2045 error = sysc_child_add_named_clock(ddata,
2047 ddata->clock_roles[i]);
2048 if (error && error != -EEXIST) {
2049 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2050 ddata->clock_roles[i], error);
2059 static struct device_type sysc_device_type = {
2062 static struct sysc *sysc_child_to_parent(struct device *dev)
2064 struct device *parent = dev->parent;
2066 if (!parent || parent->type != &sysc_device_type)
2069 return dev_get_drvdata(parent);
2072 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2077 ddata = sysc_child_to_parent(dev);
2079 error = pm_generic_runtime_suspend(dev);
2083 if (!ddata->enabled)
2086 return sysc_runtime_suspend(ddata->dev);
2089 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2094 ddata = sysc_child_to_parent(dev);
2096 if (!ddata->enabled) {
2097 error = sysc_runtime_resume(ddata->dev);
2100 "%s error: %i\n", __func__, error);
2103 return pm_generic_runtime_resume(dev);
2106 #ifdef CONFIG_PM_SLEEP
2107 static int sysc_child_suspend_noirq(struct device *dev)
2112 ddata = sysc_child_to_parent(dev);
2114 dev_dbg(ddata->dev, "%s %s\n", __func__,
2115 ddata->name ? ddata->name : "");
2117 error = pm_generic_suspend_noirq(dev);
2119 dev_err(dev, "%s error at %i: %i\n",
2120 __func__, __LINE__, error);
2125 if (!pm_runtime_status_suspended(dev)) {
2126 error = pm_generic_runtime_suspend(dev);
2128 dev_dbg(dev, "%s busy at %i: %i\n",
2129 __func__, __LINE__, error);
2134 error = sysc_runtime_suspend(ddata->dev);
2136 dev_err(dev, "%s error at %i: %i\n",
2137 __func__, __LINE__, error);
2142 ddata->child_needs_resume = true;
2148 static int sysc_child_resume_noirq(struct device *dev)
2153 ddata = sysc_child_to_parent(dev);
2155 dev_dbg(ddata->dev, "%s %s\n", __func__,
2156 ddata->name ? ddata->name : "");
2158 if (ddata->child_needs_resume) {
2159 ddata->child_needs_resume = false;
2161 error = sysc_runtime_resume(ddata->dev);
2164 "%s runtime resume error: %i\n",
2167 error = pm_generic_runtime_resume(dev);
2170 "%s generic runtime resume: %i\n",
2174 return pm_generic_resume_noirq(dev);
2178 static struct dev_pm_domain sysc_child_pm_domain = {
2180 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2181 sysc_child_runtime_resume,
2183 USE_PLATFORM_PM_SLEEP_OPS
2184 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2185 sysc_child_resume_noirq)
2190 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2191 * @ddata: device driver data
2192 * @child: child device driver
2194 * Allow idle for child devices as done with _od_runtime_suspend().
2195 * Otherwise many child devices will not idle because of the permanent
2196 * parent usecount set in pm_runtime_irq_safe().
2198 * Note that the long term solution is to just modify the child device
2199 * drivers to not set pm_runtime_irq_safe() and then this can be just
2202 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2204 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2205 dev_pm_domain_set(child, &sysc_child_pm_domain);
2208 static int sysc_notifier_call(struct notifier_block *nb,
2209 unsigned long event, void *device)
2211 struct device *dev = device;
2215 ddata = sysc_child_to_parent(dev);
2220 case BUS_NOTIFY_ADD_DEVICE:
2221 error = sysc_child_add_clocks(ddata, dev);
2224 sysc_legacy_idle_quirk(ddata, dev);
2233 static struct notifier_block sysc_nb = {
2234 .notifier_call = sysc_notifier_call,
2237 /* Device tree configured quirks */
2238 struct sysc_dts_quirk {
2243 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2244 { .name = "ti,no-idle-on-init",
2245 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2246 { .name = "ti,no-reset-on-init",
2247 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2248 { .name = "ti,no-idle",
2249 .mask = SYSC_QUIRK_NO_IDLE, },
2252 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2255 const struct property *prop;
2258 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2259 const char *name = sysc_dts_quirks[i].name;
2261 prop = of_get_property(np, name, &len);
2265 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2267 dev_warn(ddata->dev,
2268 "dts flag should be at module level for %s\n",
2274 static int sysc_init_dts_quirks(struct sysc *ddata)
2276 struct device_node *np = ddata->dev->of_node;
2280 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2282 sysc_parse_dts_quirks(ddata, np, false);
2283 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2286 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2290 ddata->cfg.srst_udelay = (u8)val;
2296 static void sysc_unprepare(struct sysc *ddata)
2303 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2304 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2305 clk_unprepare(ddata->clocks[i]);
2310 * Common sysc register bits found on omap2, also known as type1
2312 static const struct sysc_regbits sysc_regbits_omap2 = {
2313 .dmadisable_shift = -ENODEV,
2320 .autoidle_shift = 0,
2323 static const struct sysc_capabilities sysc_omap2 = {
2324 .type = TI_SYSC_OMAP2,
2325 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2326 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2327 SYSC_OMAP2_AUTOIDLE,
2328 .regbits = &sysc_regbits_omap2,
2331 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2332 static const struct sysc_capabilities sysc_omap2_timer = {
2333 .type = TI_SYSC_OMAP2_TIMER,
2334 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2335 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2336 SYSC_OMAP2_AUTOIDLE,
2337 .regbits = &sysc_regbits_omap2,
2338 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2342 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2343 * with different sidle position
2345 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2346 .dmadisable_shift = -ENODEV,
2347 .midle_shift = -ENODEV,
2349 .clkact_shift = -ENODEV,
2350 .enwkup_shift = -ENODEV,
2352 .autoidle_shift = 0,
2353 .emufree_shift = -ENODEV,
2356 static const struct sysc_capabilities sysc_omap3_sham = {
2357 .type = TI_SYSC_OMAP3_SHAM,
2358 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2359 .regbits = &sysc_regbits_omap3_sham,
2363 * AES register bits found on omap3 and later, a variant of
2364 * sysc_regbits_omap2 with different sidle position
2366 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2367 .dmadisable_shift = -ENODEV,
2368 .midle_shift = -ENODEV,
2370 .clkact_shift = -ENODEV,
2371 .enwkup_shift = -ENODEV,
2373 .autoidle_shift = 0,
2374 .emufree_shift = -ENODEV,
2377 static const struct sysc_capabilities sysc_omap3_aes = {
2378 .type = TI_SYSC_OMAP3_AES,
2379 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2380 .regbits = &sysc_regbits_omap3_aes,
2384 * Common sysc register bits found on omap4, also known as type2
2386 static const struct sysc_regbits sysc_regbits_omap4 = {
2387 .dmadisable_shift = 16,
2390 .clkact_shift = -ENODEV,
2391 .enwkup_shift = -ENODEV,
2394 .autoidle_shift = -ENODEV,
2397 static const struct sysc_capabilities sysc_omap4 = {
2398 .type = TI_SYSC_OMAP4,
2399 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2400 SYSC_OMAP4_SOFTRESET,
2401 .regbits = &sysc_regbits_omap4,
2404 static const struct sysc_capabilities sysc_omap4_timer = {
2405 .type = TI_SYSC_OMAP4_TIMER,
2406 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2407 SYSC_OMAP4_SOFTRESET,
2408 .regbits = &sysc_regbits_omap4,
2412 * Common sysc register bits found on omap4, also known as type3
2414 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2415 .dmadisable_shift = -ENODEV,
2418 .clkact_shift = -ENODEV,
2419 .enwkup_shift = -ENODEV,
2420 .srst_shift = -ENODEV,
2421 .emufree_shift = -ENODEV,
2422 .autoidle_shift = -ENODEV,
2425 static const struct sysc_capabilities sysc_omap4_simple = {
2426 .type = TI_SYSC_OMAP4_SIMPLE,
2427 .regbits = &sysc_regbits_omap4_simple,
2431 * SmartReflex sysc found on omap34xx
2433 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2434 .dmadisable_shift = -ENODEV,
2435 .midle_shift = -ENODEV,
2436 .sidle_shift = -ENODEV,
2438 .enwkup_shift = -ENODEV,
2439 .srst_shift = -ENODEV,
2440 .emufree_shift = -ENODEV,
2441 .autoidle_shift = -ENODEV,
2444 static const struct sysc_capabilities sysc_34xx_sr = {
2445 .type = TI_SYSC_OMAP34XX_SR,
2446 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2447 .regbits = &sysc_regbits_omap34xx_sr,
2448 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2449 SYSC_QUIRK_LEGACY_IDLE,
2453 * SmartReflex sysc found on omap36xx and later
2455 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2456 .dmadisable_shift = -ENODEV,
2457 .midle_shift = -ENODEV,
2459 .clkact_shift = -ENODEV,
2461 .srst_shift = -ENODEV,
2462 .emufree_shift = -ENODEV,
2463 .autoidle_shift = -ENODEV,
2466 static const struct sysc_capabilities sysc_36xx_sr = {
2467 .type = TI_SYSC_OMAP36XX_SR,
2468 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2469 .regbits = &sysc_regbits_omap36xx_sr,
2470 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2473 static const struct sysc_capabilities sysc_omap4_sr = {
2474 .type = TI_SYSC_OMAP4_SR,
2475 .regbits = &sysc_regbits_omap36xx_sr,
2476 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2480 * McASP register bits found on omap4 and later
2482 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2483 .dmadisable_shift = -ENODEV,
2484 .midle_shift = -ENODEV,
2486 .clkact_shift = -ENODEV,
2487 .enwkup_shift = -ENODEV,
2488 .srst_shift = -ENODEV,
2489 .emufree_shift = -ENODEV,
2490 .autoidle_shift = -ENODEV,
2493 static const struct sysc_capabilities sysc_omap4_mcasp = {
2494 .type = TI_SYSC_OMAP4_MCASP,
2495 .regbits = &sysc_regbits_omap4_mcasp,
2496 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2500 * McASP found on dra7 and later
2502 static const struct sysc_capabilities sysc_dra7_mcasp = {
2503 .type = TI_SYSC_OMAP4_SIMPLE,
2504 .regbits = &sysc_regbits_omap4_simple,
2505 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2509 * FS USB host found on omap4 and later
2511 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2512 .dmadisable_shift = -ENODEV,
2513 .midle_shift = -ENODEV,
2515 .clkact_shift = -ENODEV,
2517 .srst_shift = -ENODEV,
2518 .emufree_shift = -ENODEV,
2519 .autoidle_shift = -ENODEV,
2522 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2523 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2524 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2525 .regbits = &sysc_regbits_omap4_usb_host_fs,
2528 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2529 .dmadisable_shift = -ENODEV,
2530 .midle_shift = -ENODEV,
2531 .sidle_shift = -ENODEV,
2532 .clkact_shift = -ENODEV,
2535 .emufree_shift = -ENODEV,
2536 .autoidle_shift = -ENODEV,
2539 static const struct sysc_capabilities sysc_dra7_mcan = {
2540 .type = TI_SYSC_DRA7_MCAN,
2541 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2542 .regbits = &sysc_regbits_dra7_mcan,
2543 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2546 static int sysc_init_pdata(struct sysc *ddata)
2548 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2549 struct ti_sysc_module_data *mdata;
2554 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2558 if (ddata->legacy_mode) {
2559 mdata->name = ddata->legacy_mode;
2560 mdata->module_pa = ddata->module_pa;
2561 mdata->module_size = ddata->module_size;
2562 mdata->offsets = ddata->offsets;
2563 mdata->nr_offsets = SYSC_MAX_REGS;
2564 mdata->cap = ddata->cap;
2565 mdata->cfg = &ddata->cfg;
2568 ddata->mdata = mdata;
2573 static int sysc_init_match(struct sysc *ddata)
2575 const struct sysc_capabilities *cap;
2577 cap = of_device_get_match_data(ddata->dev);
2583 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2588 static void ti_sysc_idle(struct work_struct *work)
2592 ddata = container_of(work, struct sysc, idle_work.work);
2595 * One time decrement of clock usage counts if left on from init.
2596 * Note that we disable opt clocks unconditionally in this case
2597 * as they are enabled unconditionally during init without
2598 * considering sysc_opt_clks_needed() at that point.
2600 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2601 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2602 sysc_disable_main_clocks(ddata);
2603 sysc_disable_opt_clocks(ddata);
2604 sysc_clkdm_allow_idle(ddata);
2607 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2608 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2612 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2613 * and SYSC_QUIRK_NO_RESET_ON_INIT
2615 if (pm_runtime_active(ddata->dev))
2616 pm_runtime_put_sync(ddata->dev);
2619 static const struct of_device_id sysc_match_table[] = {
2620 { .compatible = "simple-bus", },
2624 static int sysc_probe(struct platform_device *pdev)
2626 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2630 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2634 ddata->dev = &pdev->dev;
2635 platform_set_drvdata(pdev, ddata);
2637 error = sysc_init_match(ddata);
2641 error = sysc_init_dts_quirks(ddata);
2645 error = sysc_map_and_check_registers(ddata);
2649 error = sysc_init_sysc_mask(ddata);
2653 error = sysc_init_idlemodes(ddata);
2657 error = sysc_init_syss_mask(ddata);
2661 error = sysc_init_pdata(ddata);
2665 sysc_init_early_quirks(ddata);
2667 error = sysc_get_clocks(ddata);
2671 error = sysc_init_resets(ddata);
2675 error = sysc_init_module(ddata);
2679 pm_runtime_enable(ddata->dev);
2680 error = pm_runtime_get_sync(ddata->dev);
2682 pm_runtime_put_noidle(ddata->dev);
2683 pm_runtime_disable(ddata->dev);
2687 /* Balance reset counts */
2689 reset_control_assert(ddata->rsts);
2691 sysc_show_registers(ddata);
2693 ddata->dev->type = &sysc_device_type;
2694 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2695 pdata ? pdata->auxdata : NULL,
2700 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2702 /* At least earlycon won't survive without deferred idle */
2703 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2704 SYSC_QUIRK_NO_IDLE_ON_INIT |
2705 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2706 schedule_delayed_work(&ddata->idle_work, 3000);
2708 pm_runtime_put(&pdev->dev);
2714 pm_runtime_put_sync(&pdev->dev);
2715 pm_runtime_disable(&pdev->dev);
2717 sysc_unprepare(ddata);
2722 static int sysc_remove(struct platform_device *pdev)
2724 struct sysc *ddata = platform_get_drvdata(pdev);
2727 /* Device can still be enabled, see deferred idle quirk in probe */
2728 if (cancel_delayed_work_sync(&ddata->idle_work))
2729 ti_sysc_idle(&ddata->idle_work.work);
2731 error = pm_runtime_get_sync(ddata->dev);
2733 pm_runtime_put_noidle(ddata->dev);
2734 pm_runtime_disable(ddata->dev);
2738 of_platform_depopulate(&pdev->dev);
2740 pm_runtime_put_sync(&pdev->dev);
2741 pm_runtime_disable(&pdev->dev);
2743 if (!reset_control_status(ddata->rsts))
2744 reset_control_assert(ddata->rsts);
2747 sysc_unprepare(ddata);
2752 static const struct of_device_id sysc_match[] = {
2753 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2754 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2755 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2756 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2757 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2758 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2759 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2760 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2761 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2762 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2763 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2764 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2765 { .compatible = "ti,sysc-usb-host-fs",
2766 .data = &sysc_omap4_usb_host_fs, },
2767 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2770 MODULE_DEVICE_TABLE(of, sysc_match);
2772 static struct platform_driver sysc_driver = {
2773 .probe = sysc_probe,
2774 .remove = sysc_remove,
2777 .of_match_table = sysc_match,
2782 static int __init sysc_init(void)
2784 bus_register_notifier(&platform_bus_type, &sysc_nb);
2786 return platform_driver_register(&sysc_driver);
2788 module_init(sysc_init);
2790 static void __exit sysc_exit(void)
2792 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2793 platform_driver_unregister(&sysc_driver);
2795 module_exit(sysc_exit);
2797 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2798 MODULE_LICENSE("GPL v2");