2 * Register cache access API
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/bsearch.h>
14 #include <linux/device.h>
15 #include <linux/export.h>
16 #include <linux/slab.h>
17 #include <linux/sort.h>
22 static const struct regcache_ops *cache_types[] = {
24 #if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED)
30 static int regcache_hw_init(struct regmap *map)
35 unsigned int reg, val;
38 if (!map->num_reg_defaults_raw)
41 /* calculate the size of reg_defaults */
42 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
43 if (regmap_readable(map, i * map->reg_stride) &&
44 !regmap_volatile(map, i * map->reg_stride))
47 /* all registers are unreadable or volatile, so just bypass */
49 map->cache_bypass = true;
53 map->num_reg_defaults = count;
54 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
56 if (!map->reg_defaults)
59 if (!map->reg_defaults_raw) {
60 bool cache_bypass = map->cache_bypass;
61 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
63 /* Bypass the cache access till data read from HW */
64 map->cache_bypass = true;
65 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
70 ret = regmap_raw_read(map, 0, tmp_buf,
72 map->cache_bypass = cache_bypass;
74 map->reg_defaults_raw = tmp_buf;
81 /* fill the reg_defaults */
82 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
83 reg = i * map->reg_stride;
85 if (!regmap_readable(map, reg))
88 if (regmap_volatile(map, reg))
91 if (map->reg_defaults_raw) {
92 val = regcache_get_val(map, map->reg_defaults_raw, i);
94 bool cache_bypass = map->cache_bypass;
96 map->cache_bypass = true;
97 ret = regmap_read(map, reg, &val);
98 map->cache_bypass = cache_bypass;
100 dev_err(map->dev, "Failed to read %d: %d\n",
106 map->reg_defaults[j].reg = reg;
107 map->reg_defaults[j].def = val;
114 kfree(map->reg_defaults);
119 int regcache_init(struct regmap *map, const struct regmap_config *config)
125 if (map->cache_type == REGCACHE_NONE) {
126 if (config->reg_defaults || config->num_reg_defaults_raw)
128 "No cache used with register defaults set!\n");
130 map->cache_bypass = true;
134 if (config->reg_defaults && !config->num_reg_defaults) {
136 "Register defaults are set without the number!\n");
140 for (i = 0; i < config->num_reg_defaults; i++)
141 if (config->reg_defaults[i].reg % map->reg_stride)
144 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
145 if (cache_types[i]->type == map->cache_type)
148 if (i == ARRAY_SIZE(cache_types)) {
149 dev_err(map->dev, "Could not match compress type: %d\n",
154 map->num_reg_defaults = config->num_reg_defaults;
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156 map->reg_defaults_raw = config->reg_defaults_raw;
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
161 map->cache_ops = cache_types[i];
163 if (!map->cache_ops->read ||
164 !map->cache_ops->write ||
165 !map->cache_ops->name)
168 /* We still need to ensure that the reg_defaults
169 * won't vanish from under us. We'll need to make
172 if (config->reg_defaults) {
173 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
174 sizeof(struct reg_default), GFP_KERNEL);
177 map->reg_defaults = tmp_buf;
178 } else if (map->num_reg_defaults_raw) {
179 /* Some devices such as PMICs don't have cache defaults,
180 * we cope with this by reading back the HW registers and
181 * crafting the cache defaults by hand.
183 ret = regcache_hw_init(map);
186 if (map->cache_bypass)
190 if (!map->max_register)
191 map->max_register = map->num_reg_defaults_raw;
193 if (map->cache_ops->init) {
194 dev_dbg(map->dev, "Initializing %s cache\n",
195 map->cache_ops->name);
196 ret = map->cache_ops->init(map);
203 kfree(map->reg_defaults);
205 kfree(map->reg_defaults_raw);
210 void regcache_exit(struct regmap *map)
212 if (map->cache_type == REGCACHE_NONE)
215 BUG_ON(!map->cache_ops);
217 kfree(map->reg_defaults);
219 kfree(map->reg_defaults_raw);
221 if (map->cache_ops->exit) {
222 dev_dbg(map->dev, "Destroying %s cache\n",
223 map->cache_ops->name);
224 map->cache_ops->exit(map);
229 * regcache_read - Fetch the value of a given register from the cache.
231 * @map: map to configure.
232 * @reg: The register index.
233 * @value: The value to be returned.
235 * Return a negative value on failure, 0 on success.
237 int regcache_read(struct regmap *map,
238 unsigned int reg, unsigned int *value)
242 if (map->cache_type == REGCACHE_NONE)
245 BUG_ON(!map->cache_ops);
247 if (!regmap_volatile(map, reg)) {
248 ret = map->cache_ops->read(map, reg, value);
251 trace_regmap_reg_read_cache(map, reg, *value);
260 * regcache_write - Set the value of a given register in the cache.
262 * @map: map to configure.
263 * @reg: The register index.
264 * @value: The new register value.
266 * Return a negative value on failure, 0 on success.
268 int regcache_write(struct regmap *map,
269 unsigned int reg, unsigned int value)
271 if (map->cache_type == REGCACHE_NONE)
274 BUG_ON(!map->cache_ops);
276 if (!regmap_volatile(map, reg))
277 return map->cache_ops->write(map, reg, value);
282 static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
287 /* If we don't know the chip just got reset, then sync everything. */
288 if (!map->no_sync_defaults)
291 /* Is this the hardware default? If so skip. */
292 ret = regcache_lookup_reg(map, reg);
293 if (ret >= 0 && val == map->reg_defaults[ret].def)
298 static int regcache_default_sync(struct regmap *map, unsigned int min,
303 for (reg = min; reg <= max; reg += map->reg_stride) {
307 if (regmap_volatile(map, reg) ||
308 !regmap_writeable(map, reg))
311 ret = regcache_read(map, reg, &val);
315 if (!regcache_reg_needs_sync(map, reg, val))
318 map->cache_bypass = true;
319 ret = _regmap_write(map, reg, val);
320 map->cache_bypass = false;
322 dev_err(map->dev, "Unable to sync register %#x. %d\n",
326 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
333 * regcache_sync - Sync the register cache with the hardware.
335 * @map: map to configure.
337 * Any registers that should not be synced should be marked as
338 * volatile. In general drivers can choose not to use the provided
339 * syncing functionality if they so require.
341 * Return a negative value on failure, 0 on success.
343 int regcache_sync(struct regmap *map)
350 if (WARN_ON(map->cache_type == REGCACHE_NONE))
353 BUG_ON(!map->cache_ops);
355 map->lock(map->lock_arg);
356 /* Remember the initial bypass state */
357 bypass = map->cache_bypass;
358 dev_dbg(map->dev, "Syncing %s cache\n",
359 map->cache_ops->name);
360 name = map->cache_ops->name;
361 trace_regcache_sync(map, name, "start");
363 if (!map->cache_dirty)
368 /* Apply any patch first */
369 map->cache_bypass = true;
370 for (i = 0; i < map->patch_regs; i++) {
371 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
373 dev_err(map->dev, "Failed to write %x = %x: %d\n",
374 map->patch[i].reg, map->patch[i].def, ret);
378 map->cache_bypass = false;
380 if (map->cache_ops->sync)
381 ret = map->cache_ops->sync(map, 0, map->max_register);
383 ret = regcache_default_sync(map, 0, map->max_register);
386 map->cache_dirty = false;
389 /* Restore the bypass state */
391 map->cache_bypass = bypass;
392 map->no_sync_defaults = false;
393 map->unlock(map->lock_arg);
395 regmap_async_complete(map);
397 trace_regcache_sync(map, name, "stop");
401 EXPORT_SYMBOL_GPL(regcache_sync);
404 * regcache_sync_region - Sync part of the register cache with the hardware.
407 * @min: first register to sync
408 * @max: last register to sync
410 * Write all non-default register values in the specified region to
413 * Return a negative value on failure, 0 on success.
415 int regcache_sync_region(struct regmap *map, unsigned int min,
422 if (WARN_ON(map->cache_type == REGCACHE_NONE))
425 BUG_ON(!map->cache_ops);
427 map->lock(map->lock_arg);
429 /* Remember the initial bypass state */
430 bypass = map->cache_bypass;
432 name = map->cache_ops->name;
433 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
435 trace_regcache_sync(map, name, "start region");
437 if (!map->cache_dirty)
442 if (map->cache_ops->sync)
443 ret = map->cache_ops->sync(map, min, max);
445 ret = regcache_default_sync(map, min, max);
448 /* Restore the bypass state */
449 map->cache_bypass = bypass;
451 map->no_sync_defaults = false;
452 map->unlock(map->lock_arg);
454 regmap_async_complete(map);
456 trace_regcache_sync(map, name, "stop region");
460 EXPORT_SYMBOL_GPL(regcache_sync_region);
463 * regcache_drop_region - Discard part of the register cache
465 * @map: map to operate on
466 * @min: first register to discard
467 * @max: last register to discard
469 * Discard part of the register cache.
471 * Return a negative value on failure, 0 on success.
473 int regcache_drop_region(struct regmap *map, unsigned int min,
478 if (!map->cache_ops || !map->cache_ops->drop)
481 map->lock(map->lock_arg);
483 trace_regcache_drop_region(map, min, max);
485 ret = map->cache_ops->drop(map, min, max);
487 map->unlock(map->lock_arg);
491 EXPORT_SYMBOL_GPL(regcache_drop_region);
494 * regcache_cache_only - Put a register map into cache only mode
496 * @map: map to configure
497 * @enable: flag if changes should be written to the hardware
499 * When a register map is marked as cache only writes to the register
500 * map API will only update the register cache, they will not cause
501 * any hardware changes. This is useful for allowing portions of
502 * drivers to act as though the device were functioning as normal when
503 * it is disabled for power saving reasons.
505 void regcache_cache_only(struct regmap *map, bool enable)
507 map->lock(map->lock_arg);
508 WARN_ON(map->cache_bypass && enable);
509 map->cache_only = enable;
510 trace_regmap_cache_only(map, enable);
511 map->unlock(map->lock_arg);
513 EXPORT_SYMBOL_GPL(regcache_cache_only);
516 * regcache_mark_dirty - Indicate that HW registers were reset to default values
520 * Inform regcache that the device has been powered down or reset, so that
521 * on resume, regcache_sync() knows to write out all non-default values
522 * stored in the cache.
524 * If this function is not called, regcache_sync() will assume that
525 * the hardware state still matches the cache state, modulo any writes that
526 * happened when cache_only was true.
528 void regcache_mark_dirty(struct regmap *map)
530 map->lock(map->lock_arg);
531 map->cache_dirty = true;
532 map->no_sync_defaults = true;
533 map->unlock(map->lock_arg);
535 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
538 * regcache_cache_bypass - Put a register map into cache bypass mode
540 * @map: map to configure
541 * @enable: flag if changes should not be written to the cache
543 * When a register map is marked with the cache bypass option, writes
544 * to the register map API will only update the hardware and not the
545 * the cache directly. This is useful when syncing the cache back to
548 void regcache_cache_bypass(struct regmap *map, bool enable)
550 map->lock(map->lock_arg);
551 WARN_ON(map->cache_only && enable);
552 map->cache_bypass = enable;
553 trace_regmap_cache_bypass(map, enable);
554 map->unlock(map->lock_arg);
556 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
558 bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
561 if (regcache_get_val(map, base, idx) == val)
564 /* Use device native format if possible */
565 if (map->format.format_val) {
566 map->format.format_val(base + (map->cache_word_size * idx),
571 switch (map->cache_word_size) {
604 unsigned int regcache_get_val(struct regmap *map, const void *base,
610 /* Use device native format if possible */
611 if (map->format.parse_val)
612 return map->format.parse_val(regcache_get_val_addr(map, base,
615 switch (map->cache_word_size) {
617 const u8 *cache = base;
622 const u16 *cache = base;
627 const u32 *cache = base;
633 const u64 *cache = base;
645 static int regcache_default_cmp(const void *a, const void *b)
647 const struct reg_default *_a = a;
648 const struct reg_default *_b = b;
650 return _a->reg - _b->reg;
653 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
655 struct reg_default key;
656 struct reg_default *r;
661 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
662 sizeof(struct reg_default), regcache_default_cmp);
665 return r - map->reg_defaults;
670 static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
675 return test_bit(idx, cache_present);
678 static int regcache_sync_block_single(struct regmap *map, void *block,
679 unsigned long *cache_present,
680 unsigned int block_base,
681 unsigned int start, unsigned int end)
683 unsigned int i, regtmp, val;
686 for (i = start; i < end; i++) {
687 regtmp = block_base + (i * map->reg_stride);
689 if (!regcache_reg_present(cache_present, i) ||
690 !regmap_writeable(map, regtmp))
693 val = regcache_get_val(map, block, i);
694 if (!regcache_reg_needs_sync(map, regtmp, val))
697 map->cache_bypass = true;
699 ret = _regmap_write(map, regtmp, val);
701 map->cache_bypass = false;
703 dev_err(map->dev, "Unable to sync register %#x. %d\n",
707 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
714 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
715 unsigned int base, unsigned int cur)
717 size_t val_bytes = map->format.val_bytes;
723 count = (cur - base) / map->reg_stride;
725 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
726 count * val_bytes, count, base, cur - map->reg_stride);
728 map->cache_bypass = true;
730 ret = _regmap_raw_write(map, base, *data, count * val_bytes);
732 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
733 base, cur - map->reg_stride, ret);
735 map->cache_bypass = false;
742 static int regcache_sync_block_raw(struct regmap *map, void *block,
743 unsigned long *cache_present,
744 unsigned int block_base, unsigned int start,
748 unsigned int regtmp = 0;
749 unsigned int base = 0;
750 const void *data = NULL;
753 for (i = start; i < end; i++) {
754 regtmp = block_base + (i * map->reg_stride);
756 if (!regcache_reg_present(cache_present, i) ||
757 !regmap_writeable(map, regtmp)) {
758 ret = regcache_sync_block_raw_flush(map, &data,
765 val = regcache_get_val(map, block, i);
766 if (!regcache_reg_needs_sync(map, regtmp, val)) {
767 ret = regcache_sync_block_raw_flush(map, &data,
775 data = regcache_get_val_addr(map, block, i);
780 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
784 int regcache_sync_block(struct regmap *map, void *block,
785 unsigned long *cache_present,
786 unsigned int block_base, unsigned int start,
789 if (regmap_can_raw_write(map) && !map->use_single_write)
790 return regcache_sync_block_raw(map, block, cache_present,
791 block_base, start, end);
793 return regcache_sync_block_single(map, block, cache_present,
794 block_base, start, end);