1 // SPDX-License-Identifier: GPL-2.0
3 // Register cache access API
5 // Copyright 2011 Wolfson Microelectronics plc
7 // Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
9 #include <linux/bsearch.h>
10 #include <linux/device.h>
11 #include <linux/export.h>
12 #include <linux/slab.h>
13 #include <linux/sort.h>
18 static const struct regcache_ops *cache_types[] = {
20 #if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED)
26 static int regcache_hw_init(struct regmap *map)
31 unsigned int reg, val;
34 if (!map->num_reg_defaults_raw)
37 /* calculate the size of reg_defaults */
38 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
39 if (regmap_readable(map, i * map->reg_stride) &&
40 !regmap_volatile(map, i * map->reg_stride))
43 /* all registers are unreadable or volatile, so just bypass */
45 map->cache_bypass = true;
49 map->num_reg_defaults = count;
50 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
52 if (!map->reg_defaults)
55 if (!map->reg_defaults_raw) {
56 bool cache_bypass = map->cache_bypass;
57 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
59 /* Bypass the cache access till data read from HW */
60 map->cache_bypass = true;
61 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
66 ret = regmap_raw_read(map, 0, tmp_buf,
68 map->cache_bypass = cache_bypass;
70 map->reg_defaults_raw = tmp_buf;
77 /* fill the reg_defaults */
78 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
79 reg = i * map->reg_stride;
81 if (!regmap_readable(map, reg))
84 if (regmap_volatile(map, reg))
87 if (map->reg_defaults_raw) {
88 val = regcache_get_val(map, map->reg_defaults_raw, i);
90 bool cache_bypass = map->cache_bypass;
92 map->cache_bypass = true;
93 ret = regmap_read(map, reg, &val);
94 map->cache_bypass = cache_bypass;
96 dev_err(map->dev, "Failed to read %d: %d\n",
102 map->reg_defaults[j].reg = reg;
103 map->reg_defaults[j].def = val;
110 kfree(map->reg_defaults);
115 int regcache_init(struct regmap *map, const struct regmap_config *config)
121 if (map->cache_type == REGCACHE_NONE) {
122 if (config->reg_defaults || config->num_reg_defaults_raw)
124 "No cache used with register defaults set!\n");
126 map->cache_bypass = true;
130 if (config->reg_defaults && !config->num_reg_defaults) {
132 "Register defaults are set without the number!\n");
136 for (i = 0; i < config->num_reg_defaults; i++)
137 if (config->reg_defaults[i].reg % map->reg_stride)
140 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
141 if (cache_types[i]->type == map->cache_type)
144 if (i == ARRAY_SIZE(cache_types)) {
145 dev_err(map->dev, "Could not match compress type: %d\n",
150 map->num_reg_defaults = config->num_reg_defaults;
151 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
152 map->reg_defaults_raw = config->reg_defaults_raw;
153 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
154 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
157 map->cache_ops = cache_types[i];
159 if (!map->cache_ops->read ||
160 !map->cache_ops->write ||
161 !map->cache_ops->name)
164 /* We still need to ensure that the reg_defaults
165 * won't vanish from under us. We'll need to make
168 if (config->reg_defaults) {
169 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
170 sizeof(struct reg_default), GFP_KERNEL);
173 map->reg_defaults = tmp_buf;
174 } else if (map->num_reg_defaults_raw) {
175 /* Some devices such as PMICs don't have cache defaults,
176 * we cope with this by reading back the HW registers and
177 * crafting the cache defaults by hand.
179 ret = regcache_hw_init(map);
182 if (map->cache_bypass)
186 if (!map->max_register)
187 map->max_register = map->num_reg_defaults_raw;
189 if (map->cache_ops->init) {
190 dev_dbg(map->dev, "Initializing %s cache\n",
191 map->cache_ops->name);
192 ret = map->cache_ops->init(map);
199 kfree(map->reg_defaults);
201 kfree(map->reg_defaults_raw);
206 void regcache_exit(struct regmap *map)
208 if (map->cache_type == REGCACHE_NONE)
211 BUG_ON(!map->cache_ops);
213 kfree(map->reg_defaults);
215 kfree(map->reg_defaults_raw);
217 if (map->cache_ops->exit) {
218 dev_dbg(map->dev, "Destroying %s cache\n",
219 map->cache_ops->name);
220 map->cache_ops->exit(map);
225 * regcache_read - Fetch the value of a given register from the cache.
227 * @map: map to configure.
228 * @reg: The register index.
229 * @value: The value to be returned.
231 * Return a negative value on failure, 0 on success.
233 int regcache_read(struct regmap *map,
234 unsigned int reg, unsigned int *value)
238 if (map->cache_type == REGCACHE_NONE)
241 BUG_ON(!map->cache_ops);
243 if (!regmap_volatile(map, reg)) {
244 ret = map->cache_ops->read(map, reg, value);
247 trace_regmap_reg_read_cache(map, reg, *value);
256 * regcache_write - Set the value of a given register in the cache.
258 * @map: map to configure.
259 * @reg: The register index.
260 * @value: The new register value.
262 * Return a negative value on failure, 0 on success.
264 int regcache_write(struct regmap *map,
265 unsigned int reg, unsigned int value)
267 if (map->cache_type == REGCACHE_NONE)
270 BUG_ON(!map->cache_ops);
272 if (!regmap_volatile(map, reg))
273 return map->cache_ops->write(map, reg, value);
278 static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
283 /* If we don't know the chip just got reset, then sync everything. */
284 if (!map->no_sync_defaults)
287 /* Is this the hardware default? If so skip. */
288 ret = regcache_lookup_reg(map, reg);
289 if (ret >= 0 && val == map->reg_defaults[ret].def)
294 static int regcache_default_sync(struct regmap *map, unsigned int min,
299 for (reg = min; reg <= max; reg += map->reg_stride) {
303 if (regmap_volatile(map, reg) ||
304 !regmap_writeable(map, reg))
307 ret = regcache_read(map, reg, &val);
311 if (!regcache_reg_needs_sync(map, reg, val))
314 map->cache_bypass = true;
315 ret = _regmap_write(map, reg, val);
316 map->cache_bypass = false;
318 dev_err(map->dev, "Unable to sync register %#x. %d\n",
322 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
329 * regcache_sync - Sync the register cache with the hardware.
331 * @map: map to configure.
333 * Any registers that should not be synced should be marked as
334 * volatile. In general drivers can choose not to use the provided
335 * syncing functionality if they so require.
337 * Return a negative value on failure, 0 on success.
339 int regcache_sync(struct regmap *map)
346 if (WARN_ON(map->cache_type == REGCACHE_NONE))
349 BUG_ON(!map->cache_ops);
351 map->lock(map->lock_arg);
352 /* Remember the initial bypass state */
353 bypass = map->cache_bypass;
354 dev_dbg(map->dev, "Syncing %s cache\n",
355 map->cache_ops->name);
356 name = map->cache_ops->name;
357 trace_regcache_sync(map, name, "start");
359 if (!map->cache_dirty)
364 /* Apply any patch first */
365 map->cache_bypass = true;
366 for (i = 0; i < map->patch_regs; i++) {
367 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
369 dev_err(map->dev, "Failed to write %x = %x: %d\n",
370 map->patch[i].reg, map->patch[i].def, ret);
374 map->cache_bypass = false;
376 if (map->cache_ops->sync)
377 ret = map->cache_ops->sync(map, 0, map->max_register);
379 ret = regcache_default_sync(map, 0, map->max_register);
382 map->cache_dirty = false;
385 /* Restore the bypass state */
387 map->cache_bypass = bypass;
388 map->no_sync_defaults = false;
389 map->unlock(map->lock_arg);
391 regmap_async_complete(map);
393 trace_regcache_sync(map, name, "stop");
397 EXPORT_SYMBOL_GPL(regcache_sync);
400 * regcache_sync_region - Sync part of the register cache with the hardware.
403 * @min: first register to sync
404 * @max: last register to sync
406 * Write all non-default register values in the specified region to
409 * Return a negative value on failure, 0 on success.
411 int regcache_sync_region(struct regmap *map, unsigned int min,
418 if (WARN_ON(map->cache_type == REGCACHE_NONE))
421 BUG_ON(!map->cache_ops);
423 map->lock(map->lock_arg);
425 /* Remember the initial bypass state */
426 bypass = map->cache_bypass;
428 name = map->cache_ops->name;
429 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
431 trace_regcache_sync(map, name, "start region");
433 if (!map->cache_dirty)
438 if (map->cache_ops->sync)
439 ret = map->cache_ops->sync(map, min, max);
441 ret = regcache_default_sync(map, min, max);
444 /* Restore the bypass state */
445 map->cache_bypass = bypass;
447 map->no_sync_defaults = false;
448 map->unlock(map->lock_arg);
450 regmap_async_complete(map);
452 trace_regcache_sync(map, name, "stop region");
456 EXPORT_SYMBOL_GPL(regcache_sync_region);
459 * regcache_drop_region - Discard part of the register cache
461 * @map: map to operate on
462 * @min: first register to discard
463 * @max: last register to discard
465 * Discard part of the register cache.
467 * Return a negative value on failure, 0 on success.
469 int regcache_drop_region(struct regmap *map, unsigned int min,
474 if (!map->cache_ops || !map->cache_ops->drop)
477 map->lock(map->lock_arg);
479 trace_regcache_drop_region(map, min, max);
481 ret = map->cache_ops->drop(map, min, max);
483 map->unlock(map->lock_arg);
487 EXPORT_SYMBOL_GPL(regcache_drop_region);
490 * regcache_cache_only - Put a register map into cache only mode
492 * @map: map to configure
493 * @enable: flag if changes should be written to the hardware
495 * When a register map is marked as cache only writes to the register
496 * map API will only update the register cache, they will not cause
497 * any hardware changes. This is useful for allowing portions of
498 * drivers to act as though the device were functioning as normal when
499 * it is disabled for power saving reasons.
501 void regcache_cache_only(struct regmap *map, bool enable)
503 map->lock(map->lock_arg);
504 WARN_ON(map->cache_bypass && enable);
505 map->cache_only = enable;
506 trace_regmap_cache_only(map, enable);
507 map->unlock(map->lock_arg);
509 EXPORT_SYMBOL_GPL(regcache_cache_only);
512 * regcache_mark_dirty - Indicate that HW registers were reset to default values
516 * Inform regcache that the device has been powered down or reset, so that
517 * on resume, regcache_sync() knows to write out all non-default values
518 * stored in the cache.
520 * If this function is not called, regcache_sync() will assume that
521 * the hardware state still matches the cache state, modulo any writes that
522 * happened when cache_only was true.
524 void regcache_mark_dirty(struct regmap *map)
526 map->lock(map->lock_arg);
527 map->cache_dirty = true;
528 map->no_sync_defaults = true;
529 map->unlock(map->lock_arg);
531 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
534 * regcache_cache_bypass - Put a register map into cache bypass mode
536 * @map: map to configure
537 * @enable: flag if changes should not be written to the cache
539 * When a register map is marked with the cache bypass option, writes
540 * to the register map API will only update the hardware and not the
541 * the cache directly. This is useful when syncing the cache back to
544 void regcache_cache_bypass(struct regmap *map, bool enable)
546 map->lock(map->lock_arg);
547 WARN_ON(map->cache_only && enable);
548 map->cache_bypass = enable;
549 trace_regmap_cache_bypass(map, enable);
550 map->unlock(map->lock_arg);
552 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
554 bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
557 if (regcache_get_val(map, base, idx) == val)
560 /* Use device native format if possible */
561 if (map->format.format_val) {
562 map->format.format_val(base + (map->cache_word_size * idx),
567 switch (map->cache_word_size) {
600 unsigned int regcache_get_val(struct regmap *map, const void *base,
606 /* Use device native format if possible */
607 if (map->format.parse_val)
608 return map->format.parse_val(regcache_get_val_addr(map, base,
611 switch (map->cache_word_size) {
613 const u8 *cache = base;
618 const u16 *cache = base;
623 const u32 *cache = base;
629 const u64 *cache = base;
641 static int regcache_default_cmp(const void *a, const void *b)
643 const struct reg_default *_a = a;
644 const struct reg_default *_b = b;
646 return _a->reg - _b->reg;
649 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
651 struct reg_default key;
652 struct reg_default *r;
657 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
658 sizeof(struct reg_default), regcache_default_cmp);
661 return r - map->reg_defaults;
666 static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
671 return test_bit(idx, cache_present);
674 static int regcache_sync_block_single(struct regmap *map, void *block,
675 unsigned long *cache_present,
676 unsigned int block_base,
677 unsigned int start, unsigned int end)
679 unsigned int i, regtmp, val;
682 for (i = start; i < end; i++) {
683 regtmp = block_base + (i * map->reg_stride);
685 if (!regcache_reg_present(cache_present, i) ||
686 !regmap_writeable(map, regtmp))
689 val = regcache_get_val(map, block, i);
690 if (!regcache_reg_needs_sync(map, regtmp, val))
693 map->cache_bypass = true;
695 ret = _regmap_write(map, regtmp, val);
697 map->cache_bypass = false;
699 dev_err(map->dev, "Unable to sync register %#x. %d\n",
703 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
710 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
711 unsigned int base, unsigned int cur)
713 size_t val_bytes = map->format.val_bytes;
719 count = (cur - base) / map->reg_stride;
721 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
722 count * val_bytes, count, base, cur - map->reg_stride);
724 map->cache_bypass = true;
726 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
728 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
729 base, cur - map->reg_stride, ret);
731 map->cache_bypass = false;
738 static int regcache_sync_block_raw(struct regmap *map, void *block,
739 unsigned long *cache_present,
740 unsigned int block_base, unsigned int start,
744 unsigned int regtmp = 0;
745 unsigned int base = 0;
746 const void *data = NULL;
749 for (i = start; i < end; i++) {
750 regtmp = block_base + (i * map->reg_stride);
752 if (!regcache_reg_present(cache_present, i) ||
753 !regmap_writeable(map, regtmp)) {
754 ret = regcache_sync_block_raw_flush(map, &data,
761 val = regcache_get_val(map, block, i);
762 if (!regcache_reg_needs_sync(map, regtmp, val)) {
763 ret = regcache_sync_block_raw_flush(map, &data,
771 data = regcache_get_val_addr(map, block, i);
776 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
780 int regcache_sync_block(struct regmap *map, void *block,
781 unsigned long *cache_present,
782 unsigned int block_base, unsigned int start,
785 if (regmap_can_raw_write(map) && !map->use_single_write)
786 return regcache_sync_block_raw(map, block, cache_present,
787 block_base, start, end);
789 return regcache_sync_block_single(map, block, cache_present,
790 block_base, start, end);