2 * Renesas R-Car SATA driver
4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013-2015 Cogent Embedded, Inc.
6 * Copyright (C) 2013-2015 Renesas Solutions Corp.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/ata.h>
17 #include <linux/libata.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/err.h>
23 #define DRV_NAME "sata_rcar"
25 /* SH-Navi2G/ATAPI-ATA compatible task registers */
26 #define DATA_REG 0x100
27 #define SDEVCON_REG 0x138
29 /* SH-Navi2G/ATAPI module compatible control registers */
30 #define ATAPI_CONTROL1_REG 0x180
31 #define ATAPI_STATUS_REG 0x184
32 #define ATAPI_INT_ENABLE_REG 0x188
33 #define ATAPI_DTB_ADR_REG 0x198
34 #define ATAPI_DMA_START_ADR_REG 0x19C
35 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0
36 #define ATAPI_CONTROL2_REG 0x1A4
37 #define ATAPI_SIG_ST_REG 0x1B0
38 #define ATAPI_BYTE_SWAP_REG 0x1BC
40 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */
41 #define ATAPI_CONTROL1_ISM BIT(16)
42 #define ATAPI_CONTROL1_DTA32M BIT(11)
43 #define ATAPI_CONTROL1_RESET BIT(7)
44 #define ATAPI_CONTROL1_DESE BIT(3)
45 #define ATAPI_CONTROL1_RW BIT(2)
46 #define ATAPI_CONTROL1_STOP BIT(1)
47 #define ATAPI_CONTROL1_START BIT(0)
49 /* ATAPI status register (ATAPI_STATUS) bits */
50 #define ATAPI_STATUS_SATAINT BIT(11)
51 #define ATAPI_STATUS_DNEND BIT(6)
52 #define ATAPI_STATUS_DEVTRM BIT(5)
53 #define ATAPI_STATUS_DEVINT BIT(4)
54 #define ATAPI_STATUS_ERR BIT(2)
55 #define ATAPI_STATUS_NEND BIT(1)
56 #define ATAPI_STATUS_ACT BIT(0)
58 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */
59 #define ATAPI_INT_ENABLE_SATAINT BIT(11)
60 #define ATAPI_INT_ENABLE_DNEND BIT(6)
61 #define ATAPI_INT_ENABLE_DEVTRM BIT(5)
62 #define ATAPI_INT_ENABLE_DEVINT BIT(4)
63 #define ATAPI_INT_ENABLE_ERR BIT(2)
64 #define ATAPI_INT_ENABLE_NEND BIT(1)
65 #define ATAPI_INT_ENABLE_ACT BIT(0)
67 /* Access control registers for physical layer control register */
68 #define SATAPHYADDR_REG 0x200
69 #define SATAPHYWDATA_REG 0x204
70 #define SATAPHYACCEN_REG 0x208
71 #define SATAPHYRESET_REG 0x20C
72 #define SATAPHYRDATA_REG 0x210
73 #define SATAPHYACK_REG 0x214
75 /* Physical layer control address command register (SATAPHYADDR) bits */
76 #define SATAPHYADDR_PHYRATEMODE BIT(10)
77 #define SATAPHYADDR_PHYCMD_READ BIT(9)
78 #define SATAPHYADDR_PHYCMD_WRITE BIT(8)
80 /* Physical layer control enable register (SATAPHYACCEN) bits */
81 #define SATAPHYACCEN_PHYLANE BIT(0)
83 /* Physical layer control reset register (SATAPHYRESET) bits */
84 #define SATAPHYRESET_PHYRST BIT(1)
85 #define SATAPHYRESET_PHYSRES BIT(0)
87 /* Physical layer control acknowledge register (SATAPHYACK) bits */
88 #define SATAPHYACK_PHYACK BIT(0)
90 /* Serial-ATA HOST control registers */
91 #define BISTCONF_REG 0x102C
92 #define SDATA_REG 0x1100
93 #define SSDEVCON_REG 0x1204
95 #define SCRSSTS_REG 0x1400
96 #define SCRSERR_REG 0x1404
97 #define SCRSCON_REG 0x1408
98 #define SCRSACT_REG 0x140C
100 #define SATAINTSTAT_REG 0x1508
101 #define SATAINTMASK_REG 0x150C
103 /* SATA INT status register (SATAINTSTAT) bits */
104 #define SATAINTSTAT_SERR BIT(3)
105 #define SATAINTSTAT_ATA BIT(0)
107 /* SATA INT mask register (SATAINTSTAT) bits */
108 #define SATAINTMASK_SERRMSK BIT(3)
109 #define SATAINTMASK_ERRMSK BIT(2)
110 #define SATAINTMASK_ERRCRTMSK BIT(1)
111 #define SATAINTMASK_ATAMSK BIT(0)
112 #define SATAINTMASK_ALL_GEN1 0x7ff
113 #define SATAINTMASK_ALL_GEN2 0xfff
115 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
118 /* Physical Layer Control Registers */
119 #define SATAPCTLR1_REG 0x43
120 #define SATAPCTLR2_REG 0x52
121 #define SATAPCTLR3_REG 0x5A
122 #define SATAPCTLR4_REG 0x60
124 /* Descriptor table word 0 bit (when DTA32M = 1) */
125 #define SATA_RCAR_DTEND BIT(0)
127 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL
129 /* Gen2 Physical Layer Control Registers */
130 #define RCAR_GEN2_PHY_CTL1_REG 0x1704
131 #define RCAR_GEN2_PHY_CTL1 0x34180002
132 #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */
134 #define RCAR_GEN2_PHY_CTL2_REG 0x170C
135 #define RCAR_GEN2_PHY_CTL2 0x00002303
137 #define RCAR_GEN2_PHY_CTL3_REG 0x171C
138 #define RCAR_GEN2_PHY_CTL3 0x000B0194
140 #define RCAR_GEN2_PHY_CTL4_REG 0x1724
141 #define RCAR_GEN2_PHY_CTL4 0x00030994
143 #define RCAR_GEN2_PHY_CTL5_REG 0x1740
144 #define RCAR_GEN2_PHY_CTL5 0x03004001
145 #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */
146 #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */
148 enum sata_rcar_type {
152 RCAR_R8A7790_ES1_SATA,
155 struct sata_rcar_priv {
158 enum sata_rcar_type type;
161 static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
163 void __iomem *base = priv->base;
166 iowrite32(0, base + SATAPHYADDR_REG);
168 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
171 iowrite32(0, base + SATAPHYRESET_REG);
174 static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
177 void __iomem *base = priv->base;
181 iowrite32(0, base + SATAPHYRESET_REG);
183 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
184 /* write phy register value */
185 iowrite32(val, base + SATAPHYWDATA_REG);
186 /* set register group */
188 reg |= SATAPHYADDR_PHYRATEMODE;
190 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
192 for (timeout = 0; timeout < 100; timeout++) {
193 val = ioread32(base + SATAPHYACK_REG);
194 if (val & SATAPHYACK_PHYACK)
198 pr_err("%s timeout\n", __func__);
200 iowrite32(0, base + SATAPHYADDR_REG);
203 static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
205 sata_rcar_gen1_phy_preinit(priv);
206 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
207 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
208 sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
209 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
210 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
211 sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
214 static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
216 void __iomem *base = priv->base;
218 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
219 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
220 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
221 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
222 iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC |
223 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
226 static void sata_rcar_freeze(struct ata_port *ap)
228 struct sata_rcar_priv *priv = ap->host->private_data;
231 iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG);
236 static void sata_rcar_thaw(struct ata_port *ap)
238 struct sata_rcar_priv *priv = ap->host->private_data;
239 void __iomem *base = priv->base;
242 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
247 iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
250 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
255 u16 data = ioread32(reg);
261 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
263 const u16 *ptr = buffer;
266 iowrite32(*ptr++, reg);
269 static u8 sata_rcar_check_status(struct ata_port *ap)
271 return ioread32(ap->ioaddr.status_addr);
274 static u8 sata_rcar_check_altstatus(struct ata_port *ap)
276 return ioread32(ap->ioaddr.altstatus_addr);
279 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
281 iowrite32(ctl, ap->ioaddr.ctl_addr);
284 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
286 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
287 ata_sff_pause(ap); /* needed; also flushes, for mmio */
290 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
293 struct ata_ioports *ioaddr = &ap->ioaddr;
296 sata_rcar_dev_select(ap, device);
298 iowrite32(0x55, ioaddr->nsect_addr);
299 iowrite32(0xaa, ioaddr->lbal_addr);
301 iowrite32(0xaa, ioaddr->nsect_addr);
302 iowrite32(0x55, ioaddr->lbal_addr);
304 iowrite32(0x55, ioaddr->nsect_addr);
305 iowrite32(0xaa, ioaddr->lbal_addr);
307 nsect = ioread32(ioaddr->nsect_addr);
308 lbal = ioread32(ioaddr->lbal_addr);
310 if (nsect == 0x55 && lbal == 0xaa)
311 return 1; /* found a device */
313 return 0; /* nothing found */
316 static int sata_rcar_wait_after_reset(struct ata_link *link,
317 unsigned long deadline)
319 struct ata_port *ap = link->ap;
321 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
323 return ata_sff_wait_ready(link, deadline);
326 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
328 struct ata_ioports *ioaddr = &ap->ioaddr;
330 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
332 /* software reset. causes dev0 to be selected */
333 iowrite32(ap->ctl, ioaddr->ctl_addr);
335 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
337 iowrite32(ap->ctl, ioaddr->ctl_addr);
338 ap->last_ctl = ap->ctl;
340 /* wait the port to become ready */
341 return sata_rcar_wait_after_reset(&ap->link, deadline);
344 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
345 unsigned long deadline)
347 struct ata_port *ap = link->ap;
348 unsigned int devmask = 0;
352 /* determine if device 0 is present */
353 if (sata_rcar_ata_devchk(ap, 0))
356 /* issue bus reset */
357 DPRINTK("about to softreset, devmask=%x\n", devmask);
358 rc = sata_rcar_bus_softreset(ap, deadline);
359 /* if link is occupied, -ENODEV too is an error */
360 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
361 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
365 /* determine by signature whether we have ATA or ATAPI devices */
366 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
368 DPRINTK("classes[0]=%u\n", classes[0]);
372 static void sata_rcar_tf_load(struct ata_port *ap,
373 const struct ata_taskfile *tf)
375 struct ata_ioports *ioaddr = &ap->ioaddr;
376 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
378 if (tf->ctl != ap->last_ctl) {
379 iowrite32(tf->ctl, ioaddr->ctl_addr);
380 ap->last_ctl = tf->ctl;
384 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
385 iowrite32(tf->hob_feature, ioaddr->feature_addr);
386 iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
387 iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
388 iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
389 iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
390 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
399 iowrite32(tf->feature, ioaddr->feature_addr);
400 iowrite32(tf->nsect, ioaddr->nsect_addr);
401 iowrite32(tf->lbal, ioaddr->lbal_addr);
402 iowrite32(tf->lbam, ioaddr->lbam_addr);
403 iowrite32(tf->lbah, ioaddr->lbah_addr);
404 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
412 if (tf->flags & ATA_TFLAG_DEVICE) {
413 iowrite32(tf->device, ioaddr->device_addr);
414 VPRINTK("device 0x%X\n", tf->device);
420 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
422 struct ata_ioports *ioaddr = &ap->ioaddr;
424 tf->command = sata_rcar_check_status(ap);
425 tf->feature = ioread32(ioaddr->error_addr);
426 tf->nsect = ioread32(ioaddr->nsect_addr);
427 tf->lbal = ioread32(ioaddr->lbal_addr);
428 tf->lbam = ioread32(ioaddr->lbam_addr);
429 tf->lbah = ioread32(ioaddr->lbah_addr);
430 tf->device = ioread32(ioaddr->device_addr);
432 if (tf->flags & ATA_TFLAG_LBA48) {
433 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
434 tf->hob_feature = ioread32(ioaddr->error_addr);
435 tf->hob_nsect = ioread32(ioaddr->nsect_addr);
436 tf->hob_lbal = ioread32(ioaddr->lbal_addr);
437 tf->hob_lbam = ioread32(ioaddr->lbam_addr);
438 tf->hob_lbah = ioread32(ioaddr->lbah_addr);
439 iowrite32(tf->ctl, ioaddr->ctl_addr);
440 ap->last_ctl = tf->ctl;
444 static void sata_rcar_exec_command(struct ata_port *ap,
445 const struct ata_taskfile *tf)
447 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
449 iowrite32(tf->command, ap->ioaddr.command_addr);
453 static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc,
455 unsigned int buflen, int rw)
457 struct ata_port *ap = qc->dev->link->ap;
458 void __iomem *data_addr = ap->ioaddr.data_addr;
459 unsigned int words = buflen >> 1;
461 /* Transfer multiple of 2 bytes */
463 sata_rcar_ioread16_rep(data_addr, buf, words);
465 sata_rcar_iowrite16_rep(data_addr, buf, words);
467 /* Transfer trailing byte, if any. */
468 if (unlikely(buflen & 0x01)) {
469 unsigned char pad[2] = { };
471 /* Point buf to the tail of buffer */
475 * Use io*16_rep() accessors here as well to avoid pointlessly
476 * swapping bytes to and from on the big endian machines...
479 sata_rcar_ioread16_rep(data_addr, pad, 1);
483 sata_rcar_iowrite16_rep(data_addr, pad, 1);
491 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
496 /* We only need to flush incoming data when a command was running */
497 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
501 /* Drain up to 64K of data before we give up this recovery method */
502 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
503 count < 65536; count += 2)
504 ioread32(ap->ioaddr.data_addr);
506 /* Can become DEBUG later */
508 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
511 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
514 if (sc_reg > SCR_ACTIVE)
517 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
521 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
524 if (sc_reg > SCR_ACTIVE)
527 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
531 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
533 struct ata_port *ap = qc->ap;
534 struct ata_bmdma_prd *prd = ap->bmdma_prd;
535 struct scatterlist *sg;
538 for_each_sg(qc->sg, sg, qc->n_elem, si) {
542 * Note: h/w doesn't support 64-bit, so we unconditionally
543 * truncate dma_addr_t to u32.
545 addr = (u32)sg_dma_address(sg);
546 sg_len = sg_dma_len(sg);
548 prd[si].addr = cpu_to_le32(addr);
549 prd[si].flags_len = cpu_to_le32(sg_len);
550 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
553 /* end-of-table flag */
554 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
557 static enum ata_completion_errors sata_rcar_qc_prep(struct ata_queued_cmd *qc)
559 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
562 sata_rcar_bmdma_fill_sg(qc);
567 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
569 struct ata_port *ap = qc->ap;
570 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
571 struct sata_rcar_priv *priv = ap->host->private_data;
572 void __iomem *base = priv->base;
575 /* load PRD table addr. */
576 mb(); /* make sure PRD table writes are visible to controller */
577 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
579 /* specify data direction, triple-check start bit is clear */
580 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
581 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
582 if (dmactl & ATAPI_CONTROL1_START) {
583 dmactl &= ~ATAPI_CONTROL1_START;
584 dmactl |= ATAPI_CONTROL1_STOP;
587 dmactl |= ATAPI_CONTROL1_RW;
588 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
590 /* issue r/w command */
591 ap->ops->sff_exec_command(ap, &qc->tf);
594 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
596 struct ata_port *ap = qc->ap;
597 struct sata_rcar_priv *priv = ap->host->private_data;
598 void __iomem *base = priv->base;
601 /* start host DMA transaction */
602 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
603 dmactl &= ~ATAPI_CONTROL1_STOP;
604 dmactl |= ATAPI_CONTROL1_START;
605 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
608 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
610 struct ata_port *ap = qc->ap;
611 struct sata_rcar_priv *priv = ap->host->private_data;
612 void __iomem *base = priv->base;
615 /* force termination of DMA transfer if active */
616 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
617 if (dmactl & ATAPI_CONTROL1_START) {
618 dmactl &= ~ATAPI_CONTROL1_START;
619 dmactl |= ATAPI_CONTROL1_STOP;
620 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
623 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
624 ata_sff_dma_pause(ap);
627 static u8 sata_rcar_bmdma_status(struct ata_port *ap)
629 struct sata_rcar_priv *priv = ap->host->private_data;
633 status = ioread32(priv->base + ATAPI_STATUS_REG);
634 if (status & ATAPI_STATUS_DEVINT)
635 host_stat |= ATA_DMA_INTR;
636 if (status & ATAPI_STATUS_ACT)
637 host_stat |= ATA_DMA_ACTIVE;
642 static struct scsi_host_template sata_rcar_sht = {
643 ATA_BASE_SHT(DRV_NAME),
645 * This controller allows transfer chunks up to 512MB which cross 64KB
646 * boundaries, therefore the DMA limits are more relaxed than standard
649 .sg_tablesize = ATA_MAX_PRD,
650 .dma_boundary = SATA_RCAR_DMA_BOUNDARY,
653 static struct ata_port_operations sata_rcar_port_ops = {
654 .inherits = &ata_bmdma_port_ops,
656 .freeze = sata_rcar_freeze,
657 .thaw = sata_rcar_thaw,
658 .softreset = sata_rcar_softreset,
660 .scr_read = sata_rcar_scr_read,
661 .scr_write = sata_rcar_scr_write,
663 .sff_dev_select = sata_rcar_dev_select,
664 .sff_set_devctl = sata_rcar_set_devctl,
665 .sff_check_status = sata_rcar_check_status,
666 .sff_check_altstatus = sata_rcar_check_altstatus,
667 .sff_tf_load = sata_rcar_tf_load,
668 .sff_tf_read = sata_rcar_tf_read,
669 .sff_exec_command = sata_rcar_exec_command,
670 .sff_data_xfer = sata_rcar_data_xfer,
671 .sff_drain_fifo = sata_rcar_drain_fifo,
673 .qc_prep = sata_rcar_qc_prep,
675 .bmdma_setup = sata_rcar_bmdma_setup,
676 .bmdma_start = sata_rcar_bmdma_start,
677 .bmdma_stop = sata_rcar_bmdma_stop,
678 .bmdma_status = sata_rcar_bmdma_status,
681 static void sata_rcar_serr_interrupt(struct ata_port *ap)
683 struct sata_rcar_priv *priv = ap->host->private_data;
684 struct ata_eh_info *ehi = &ap->link.eh_info;
688 serror = ioread32(priv->base + SCRSERR_REG);
692 DPRINTK("SError @host_intr: 0x%x\n", serror);
694 /* first, analyze and record host port events */
695 ata_ehi_clear_desc(ehi);
697 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
698 /* Setup a soft-reset EH action */
699 ata_ehi_hotplugged(ehi);
700 ata_ehi_push_desc(ehi, "%s", "hotplug");
702 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
705 /* freeze or abort */
712 static void sata_rcar_ata_interrupt(struct ata_port *ap)
714 struct ata_queued_cmd *qc;
717 qc = ata_qc_from_tag(ap, ap->link.active_tag);
719 handled |= ata_bmdma_port_intr(ap, qc);
721 /* be sure to clear ATA interrupt */
723 sata_rcar_check_status(ap);
726 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
728 struct ata_host *host = dev_instance;
729 struct sata_rcar_priv *priv = host->private_data;
730 void __iomem *base = priv->base;
731 unsigned int handled = 0;
736 spin_lock_irqsave(&host->lock, flags);
738 sataintstat = ioread32(base + SATAINTSTAT_REG);
739 sataintstat &= SATA_RCAR_INT_MASK;
743 iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG);
747 if (sataintstat & SATAINTSTAT_ATA)
748 sata_rcar_ata_interrupt(ap);
750 if (sataintstat & SATAINTSTAT_SERR)
751 sata_rcar_serr_interrupt(ap);
755 spin_unlock_irqrestore(&host->lock, flags);
757 return IRQ_RETVAL(handled);
760 static void sata_rcar_setup_port(struct ata_host *host)
762 struct ata_port *ap = host->ports[0];
763 struct ata_ioports *ioaddr = &ap->ioaddr;
764 struct sata_rcar_priv *priv = host->private_data;
765 void __iomem *base = priv->base;
767 ap->ops = &sata_rcar_port_ops;
768 ap->pio_mask = ATA_PIO4;
769 ap->udma_mask = ATA_UDMA6;
770 ap->flags |= ATA_FLAG_SATA;
772 if (priv->type == RCAR_R8A7790_ES1_SATA)
773 ap->flags |= ATA_FLAG_NO_DIPM;
775 ioaddr->cmd_addr = base + SDATA_REG;
776 ioaddr->ctl_addr = base + SSDEVCON_REG;
777 ioaddr->scr_addr = base + SCRSSTS_REG;
778 ioaddr->altstatus_addr = ioaddr->ctl_addr;
780 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
781 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
782 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
783 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
784 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
785 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
786 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
787 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
788 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
789 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
792 static void sata_rcar_init_module(struct sata_rcar_priv *priv)
794 void __iomem *base = priv->base;
797 /* SATA-IP reset state */
798 val = ioread32(base + ATAPI_CONTROL1_REG);
799 val |= ATAPI_CONTROL1_RESET;
800 iowrite32(val, base + ATAPI_CONTROL1_REG);
802 /* ISM mode, PRD mode, DTEND flag at bit 0 */
803 val = ioread32(base + ATAPI_CONTROL1_REG);
804 val |= ATAPI_CONTROL1_ISM;
805 val |= ATAPI_CONTROL1_DESE;
806 val |= ATAPI_CONTROL1_DTA32M;
807 iowrite32(val, base + ATAPI_CONTROL1_REG);
809 /* Release the SATA-IP from the reset state */
810 val = ioread32(base + ATAPI_CONTROL1_REG);
811 val &= ~ATAPI_CONTROL1_RESET;
812 iowrite32(val, base + ATAPI_CONTROL1_REG);
815 iowrite32(0, base + SATAINTSTAT_REG);
816 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
818 /* enable interrupts */
819 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
822 static void sata_rcar_init_controller(struct ata_host *host)
824 struct sata_rcar_priv *priv = host->private_data;
826 priv->sataint_mask = SATAINTMASK_ALL_GEN2;
828 /* reset and setup phy */
829 switch (priv->type) {
831 priv->sataint_mask = SATAINTMASK_ALL_GEN1;
832 sata_rcar_gen1_phy_init(priv);
835 case RCAR_R8A7790_ES1_SATA:
836 sata_rcar_gen2_phy_init(priv);
841 dev_warn(host->dev, "SATA phy is not initialized\n");
845 sata_rcar_init_module(priv);
848 static const struct of_device_id sata_rcar_match[] = {
850 /* Deprecated by "renesas,sata-r8a7779" */
851 .compatible = "renesas,rcar-sata",
852 .data = (void *)RCAR_GEN1_SATA,
855 .compatible = "renesas,sata-r8a7779",
856 .data = (void *)RCAR_GEN1_SATA,
859 .compatible = "renesas,sata-r8a7790",
860 .data = (void *)RCAR_GEN2_SATA
863 .compatible = "renesas,sata-r8a7790-es1",
864 .data = (void *)RCAR_R8A7790_ES1_SATA
867 .compatible = "renesas,sata-r8a7791",
868 .data = (void *)RCAR_GEN2_SATA
871 .compatible = "renesas,sata-r8a7793",
872 .data = (void *)RCAR_GEN2_SATA
875 .compatible = "renesas,sata-r8a7795",
876 .data = (void *)RCAR_GEN3_SATA
879 .compatible = "renesas,rcar-gen2-sata",
880 .data = (void *)RCAR_GEN2_SATA
883 .compatible = "renesas,rcar-gen3-sata",
884 .data = (void *)RCAR_GEN3_SATA
888 MODULE_DEVICE_TABLE(of, sata_rcar_match);
890 static int sata_rcar_probe(struct platform_device *pdev)
892 struct device *dev = &pdev->dev;
893 struct ata_host *host;
894 struct sata_rcar_priv *priv;
895 struct resource *mem;
899 irq = platform_get_irq(pdev, 0);
905 priv = devm_kzalloc(dev, sizeof(struct sata_rcar_priv), GFP_KERNEL);
909 priv->type = (enum sata_rcar_type)of_device_get_match_data(dev);
911 pm_runtime_enable(dev);
912 ret = pm_runtime_get_sync(dev);
916 host = ata_host_alloc(dev, 1);
918 dev_err(dev, "ata_host_alloc failed\n");
923 host->private_data = priv;
925 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
926 priv->base = devm_ioremap_resource(dev, mem);
927 if (IS_ERR(priv->base)) {
928 ret = PTR_ERR(priv->base);
933 sata_rcar_setup_port(host);
935 /* initialize host controller */
936 sata_rcar_init_controller(host);
938 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
945 pm_runtime_disable(dev);
949 static int sata_rcar_remove(struct platform_device *pdev)
951 struct ata_host *host = platform_get_drvdata(pdev);
952 struct sata_rcar_priv *priv = host->private_data;
953 void __iomem *base = priv->base;
955 ata_host_detach(host);
957 /* disable interrupts */
958 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
960 iowrite32(0, base + SATAINTSTAT_REG);
961 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
963 pm_runtime_put(&pdev->dev);
964 pm_runtime_disable(&pdev->dev);
969 #ifdef CONFIG_PM_SLEEP
970 static int sata_rcar_suspend(struct device *dev)
972 struct ata_host *host = dev_get_drvdata(dev);
973 struct sata_rcar_priv *priv = host->private_data;
974 void __iomem *base = priv->base;
977 ret = ata_host_suspend(host, PMSG_SUSPEND);
979 /* disable interrupts */
980 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
982 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
990 static int sata_rcar_resume(struct device *dev)
992 struct ata_host *host = dev_get_drvdata(dev);
993 struct sata_rcar_priv *priv = host->private_data;
994 void __iomem *base = priv->base;
997 ret = pm_runtime_get_sync(dev);
1003 if (priv->type == RCAR_GEN3_SATA) {
1004 sata_rcar_init_module(priv);
1007 iowrite32(0, base + SATAINTSTAT_REG);
1008 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
1010 /* enable interrupts */
1011 iowrite32(ATAPI_INT_ENABLE_SATAINT,
1012 base + ATAPI_INT_ENABLE_REG);
1015 ata_host_resume(host);
1020 static int sata_rcar_restore(struct device *dev)
1022 struct ata_host *host = dev_get_drvdata(dev);
1025 ret = pm_runtime_get_sync(dev);
1027 pm_runtime_put(dev);
1031 sata_rcar_setup_port(host);
1033 /* initialize host controller */
1034 sata_rcar_init_controller(host);
1036 ata_host_resume(host);
1041 static const struct dev_pm_ops sata_rcar_pm_ops = {
1042 .suspend = sata_rcar_suspend,
1043 .resume = sata_rcar_resume,
1044 .freeze = sata_rcar_suspend,
1045 .thaw = sata_rcar_resume,
1046 .poweroff = sata_rcar_suspend,
1047 .restore = sata_rcar_restore,
1051 static struct platform_driver sata_rcar_driver = {
1052 .probe = sata_rcar_probe,
1053 .remove = sata_rcar_remove,
1056 .of_match_table = sata_rcar_match,
1057 #ifdef CONFIG_PM_SLEEP
1058 .pm = &sata_rcar_pm_ops,
1063 module_platform_driver(sata_rcar_driver);
1065 MODULE_LICENSE("GPL");
1066 MODULE_AUTHOR("Vladimir Barinov");
1067 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");