1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/ata/sata_dwc_460ex.c
5 * Synopsys DesignWare Cores (DWC) SATA host driver
7 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
9 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
10 * Copyright 2008 DENX Software Engineering
12 * Based on versions provided by AMCC and Synopsys which are:
13 * Copyright 2006 Applied Micro Circuits Corporation
14 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
17 #ifdef CONFIG_SATA_DWC_DEBUG
21 #ifdef CONFIG_SATA_DWC_VDEBUG
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/dmaengine.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/phy/phy.h>
35 #include <linux/libata.h>
36 #include <linux/slab.h>
40 #include <scsi/scsi_host.h>
41 #include <scsi/scsi_cmnd.h>
43 /* These two are defined in "libata.h" */
47 #define DRV_NAME "sata-dwc"
48 #define DRV_VERSION "1.3"
50 #define sata_dwc_writel(a, v) writel_relaxed(v, a)
51 #define sata_dwc_readl(a) readl_relaxed(a)
57 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
60 SATA_DWC_MAX_PORTS = 1,
62 SATA_DWC_SCR_OFFSET = 0x24,
63 SATA_DWC_REG_OFFSET = 0x64,
66 /* DWC SATA Registers */
67 struct sata_dwc_regs {
68 u32 fptagr; /* 1st party DMA tag */
69 u32 fpbor; /* 1st party DMA buffer offset */
70 u32 fptcr; /* 1st party DMA Xfr count */
71 u32 dmacr; /* DMA Control */
72 u32 dbtsr; /* DMA Burst Transac size */
73 u32 intpr; /* Interrupt Pending */
74 u32 intmr; /* Interrupt Mask */
75 u32 errmr; /* Error Mask */
76 u32 llcr; /* Link Layer Control */
77 u32 phycr; /* PHY Control */
78 u32 physr; /* PHY Status */
79 u32 rxbistpd; /* Recvd BIST pattern def register */
80 u32 rxbistpd1; /* Recvd BIST data dword1 */
81 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
82 u32 txbistpd; /* Trans BIST pattern def register */
83 u32 txbistpd1; /* Trans BIST data dword1 */
84 u32 txbistpd2; /* Trans BIST data dword2 */
85 u32 bistcr; /* BIST Control Register */
86 u32 bistfctr; /* BIST FIS Count Register */
87 u32 bistsr; /* BIST Status Register */
88 u32 bistdecr; /* BIST Dword Error count register */
89 u32 res[15]; /* Reserved locations */
90 u32 testr; /* Test Register */
91 u32 versionr; /* Version Register */
92 u32 idr; /* ID Register */
93 u32 unimpl[192]; /* Unimplemented */
94 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
98 SCR_SCONTROL_DET_ENABLE = 0x00000001,
99 SCR_SSTATUS_DET_PRESENT = 0x00000001,
100 SCR_SERROR_DIAG_X = 0x04000000,
101 /* DWC SATA Register Operations */
102 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
103 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
104 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
105 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
106 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
107 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
108 SATA_DWC_INTPR_DMAT = 0x00000001,
109 SATA_DWC_INTPR_NEWFP = 0x00000002,
110 SATA_DWC_INTPR_PMABRT = 0x00000004,
111 SATA_DWC_INTPR_ERR = 0x00000008,
112 SATA_DWC_INTPR_NEWBIST = 0x00000010,
113 SATA_DWC_INTPR_IPF = 0x10000000,
114 SATA_DWC_INTMR_DMATM = 0x00000001,
115 SATA_DWC_INTMR_NEWFPM = 0x00000002,
116 SATA_DWC_INTMR_PMABRTM = 0x00000004,
117 SATA_DWC_INTMR_ERRM = 0x00000008,
118 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
119 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
120 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
121 SATA_DWC_LLCR_RPDEN = 0x00000004,
122 /* This is all error bits, zero's are reserved fields. */
123 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
126 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
127 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
128 SATA_DWC_DMACR_TMOD_TXCHEN)
129 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
130 SATA_DWC_DMACR_TMOD_TXCHEN)
131 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
132 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
134 struct sata_dwc_device {
135 struct device *dev; /* generic device struct */
136 struct ata_probe_ent *pe; /* ptr to probe-ent */
137 struct ata_host *host;
138 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
143 #ifdef CONFIG_SATA_DWC_OLD_DMA
144 struct dw_dma_chip *dma;
149 * Allow one extra special slot for commands and DMA management
150 * to account for libata internal commands.
152 #define SATA_DWC_QCMD_MAX (ATA_MAX_QUEUE + 1)
154 struct sata_dwc_device_port {
155 struct sata_dwc_device *hsdev;
156 int cmd_issued[SATA_DWC_QCMD_MAX];
157 int dma_pending[SATA_DWC_QCMD_MAX];
160 struct dma_chan *chan;
161 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
162 u32 dma_interrupt_count;
166 * Commonly used DWC SATA driver macros
168 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
169 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
170 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
171 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
175 SATA_DWC_CMD_ISSUED_NOT = 0,
176 SATA_DWC_CMD_ISSUED_PEND = 1,
177 SATA_DWC_CMD_ISSUED_EXEC = 2,
178 SATA_DWC_CMD_ISSUED_NODATA = 3,
180 SATA_DWC_DMA_PENDING_NONE = 0,
181 SATA_DWC_DMA_PENDING_TX = 1,
182 SATA_DWC_DMA_PENDING_RX = 2,
188 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
189 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
191 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
192 static void sata_dwc_port_stop(struct ata_port *ap);
193 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
195 #ifdef CONFIG_SATA_DWC_OLD_DMA
197 #include <linux/platform_data/dma-dw.h>
198 #include <linux/dma/dw.h>
200 static struct dw_dma_slave sata_dwc_dma_dws = {
207 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
209 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
211 if (dws->dma_dev != chan->device->dev)
218 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
220 struct sata_dwc_device *hsdev = hsdevp->hsdev;
221 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
224 dws->dma_dev = hsdev->dev;
227 dma_cap_set(DMA_SLAVE, mask);
229 /* Acquire DMA channel */
230 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
232 dev_err(hsdev->dev, "%s: dma channel unavailable\n",
240 static int sata_dwc_dma_init_old(struct platform_device *pdev,
241 struct sata_dwc_device *hsdev)
243 struct device_node *np = pdev->dev.of_node;
244 struct resource *res;
246 hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
250 hsdev->dma->dev = &pdev->dev;
251 hsdev->dma->id = pdev->id;
253 /* Get SATA DMA interrupt number */
254 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
255 if (hsdev->dma->irq == NO_IRQ) {
256 dev_err(&pdev->dev, "no SATA DMA irq\n");
260 /* Get physical SATA DMA register base address */
261 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
262 hsdev->dma->regs = devm_ioremap_resource(&pdev->dev, res);
263 if (IS_ERR(hsdev->dma->regs))
264 return PTR_ERR(hsdev->dma->regs);
266 /* Initialize AHB DMAC */
267 return dw_dma_probe(hsdev->dma);
270 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
275 dw_dma_remove(hsdev->dma);
280 static const char *get_prot_descript(u8 protocol)
283 case ATA_PROT_NODATA:
284 return "ATA no data";
291 case ATA_PROT_NCQ_NODATA:
292 return "ATA NCQ no data";
293 case ATAPI_PROT_NODATA:
294 return "ATAPI no data";
304 static const char *get_dma_dir_descript(int dma_dir)
306 switch ((enum dma_data_direction)dma_dir) {
307 case DMA_BIDIRECTIONAL:
308 return "bidirectional";
311 case DMA_FROM_DEVICE:
312 return "from device";
318 static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
321 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
322 tf->command, get_prot_descript(tf->protocol), tf->flags,
325 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
326 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
328 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
329 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
333 static void dma_dwc_xfer_done(void *hsdev_instance)
336 struct sata_dwc_device *hsdev = hsdev_instance;
337 struct ata_host *host = (struct ata_host *)hsdev->host;
339 struct sata_dwc_device_port *hsdevp;
341 unsigned int port = 0;
343 spin_lock_irqsave(&host->lock, flags);
344 ap = host->ports[port];
345 hsdevp = HSDEVP_FROM_AP(ap);
346 tag = ap->link.active_tag;
349 * Each DMA command produces 2 interrupts. Only
350 * complete the command after both interrupts have been
351 * seen. (See sata_dwc_isr())
353 hsdevp->dma_interrupt_count++;
354 sata_dwc_clear_dmacr(hsdevp, tag);
356 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
357 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
358 tag, hsdevp->dma_pending[tag]);
361 if ((hsdevp->dma_interrupt_count % 2) == 0)
362 sata_dwc_dma_xfer_complete(ap, 1);
364 spin_unlock_irqrestore(&host->lock, flags);
367 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
369 struct ata_port *ap = qc->ap;
370 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
371 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
372 struct dma_slave_config sconf;
373 struct dma_async_tx_descriptor *desc;
375 if (qc->dma_dir == DMA_DEV_TO_MEM) {
376 sconf.src_addr = hsdev->dmadr;
377 sconf.device_fc = false;
378 } else { /* DMA_MEM_TO_DEV */
379 sconf.dst_addr = hsdev->dmadr;
380 sconf.device_fc = false;
383 sconf.direction = qc->dma_dir;
384 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
385 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
386 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
387 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
389 dmaengine_slave_config(hsdevp->chan, &sconf);
391 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
392 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
394 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
399 desc->callback = dma_dwc_xfer_done;
400 desc->callback_param = hsdev;
402 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
403 qc->sg, qc->n_elem, &hsdev->dmadr);
408 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
410 if (scr > SCR_NOTIFICATION) {
411 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
416 *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
417 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
418 link->ap->print_id, scr, *val);
423 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
425 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
426 link->ap->print_id, scr, val);
427 if (scr > SCR_NOTIFICATION) {
428 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
432 sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
437 static void clear_serror(struct ata_port *ap)
440 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
441 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
444 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
446 sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
447 sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
450 static u32 qcmd_tag_to_mask(u8 tag)
452 return 0x00000001 << (tag & 0x1f);
456 static void sata_dwc_error_intr(struct ata_port *ap,
457 struct sata_dwc_device *hsdev, uint intpr)
459 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
460 struct ata_eh_info *ehi = &ap->link.eh_info;
461 unsigned int err_mask = 0, action = 0;
462 struct ata_queued_cmd *qc;
466 ata_ehi_clear_desc(ehi);
468 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
469 status = ap->ops->sff_check_status(ap);
471 tag = ap->link.active_tag;
474 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
475 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
476 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
478 /* Clear error register and interrupt bit */
480 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
482 /* This is the only error happening now. TODO check for exact error */
484 err_mask |= AC_ERR_HOST_BUS;
485 action |= ATA_EH_RESET;
487 /* Pass this on to EH */
488 ehi->serror |= serror;
489 ehi->action |= action;
491 qc = ata_qc_from_tag(ap, tag);
493 qc->err_mask |= err_mask;
495 ehi->err_mask |= err_mask;
501 * Function : sata_dwc_isr
502 * arguments : irq, void *dev_instance, struct pt_regs *regs
503 * Return value : irqreturn_t - status of IRQ
504 * This Interrupt handler called via port ops registered function.
505 * .irq_handler = sata_dwc_isr
507 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
509 struct ata_host *host = (struct ata_host *)dev_instance;
510 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
512 struct ata_queued_cmd *qc;
515 int handled, num_processed, port = 0;
516 uint intpr, sactive, sactive2, tag_mask;
517 struct sata_dwc_device_port *hsdevp;
518 hsdev->sactive_issued = 0;
520 spin_lock_irqsave(&host->lock, flags);
522 /* Read the interrupt register */
523 intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
525 ap = host->ports[port];
526 hsdevp = HSDEVP_FROM_AP(ap);
528 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
529 ap->link.active_tag);
531 /* Check for error interrupt */
532 if (intpr & SATA_DWC_INTPR_ERR) {
533 sata_dwc_error_intr(ap, hsdev, intpr);
538 /* Check for DMA SETUP FIS (FP DMA) interrupt */
539 if (intpr & SATA_DWC_INTPR_NEWFP) {
540 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
542 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
543 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
544 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
545 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
547 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
549 qc = ata_qc_from_tag(ap, tag);
551 dev_err(ap->dev, "failed to get qc");
556 * Start FP DMA for NCQ command. At this point the tag is the
557 * active tag. It is the tag that matches the command about to
560 qc->ap->link.active_tag = tag;
561 sata_dwc_bmdma_start_by_tag(qc, tag);
566 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
567 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
569 /* If no sactive issued and tag_mask is zero then this is not NCQ */
570 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
571 if (ap->link.active_tag == ATA_TAG_POISON)
574 tag = ap->link.active_tag;
575 qc = ata_qc_from_tag(ap, tag);
577 /* DEV interrupt w/ no active qc? */
578 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
580 "%s interrupt with no active qc qc=%p\n",
582 ap->ops->sff_check_status(ap);
586 status = ap->ops->sff_check_status(ap);
588 qc->ap->link.active_tag = tag;
589 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
591 if (status & ATA_ERR) {
592 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
593 sata_dwc_qc_complete(ap, qc, 1);
598 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
599 __func__, get_prot_descript(qc->tf.protocol));
601 if (ata_is_dma(qc->tf.protocol)) {
603 * Each DMA transaction produces 2 interrupts. The DMAC
604 * transfer complete interrupt and the SATA controller
605 * operation done interrupt. The command should be
606 * completed only after both interrupts are seen.
608 hsdevp->dma_interrupt_count++;
609 if (hsdevp->dma_pending[tag] == \
610 SATA_DWC_DMA_PENDING_NONE) {
612 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
613 __func__, intpr, status,
614 hsdevp->dma_pending[tag]);
617 if ((hsdevp->dma_interrupt_count % 2) == 0)
618 sata_dwc_dma_xfer_complete(ap, 1);
619 } else if (ata_is_pio(qc->tf.protocol)) {
620 ata_sff_hsm_move(ap, qc, status, 0);
624 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
633 * This is a NCQ command. At this point we need to figure out for which
634 * tags we have gotten a completion interrupt. One interrupt may serve
635 * as completion for more than one operation when commands are queued
636 * (NCQ). We need to process each completed command.
639 /* process completed commands */
640 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
641 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
643 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
645 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
646 __func__, sactive, hsdev->sactive_issued, tag_mask);
649 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
651 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
652 sactive, hsdev->sactive_issued, tag_mask);
655 /* read just to clear ... not bad if currently still busy */
656 status = ap->ops->sff_check_status(ap);
657 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
663 while (!(tag_mask & 0x00000001)) {
668 tag_mask &= (~0x00000001);
669 qc = ata_qc_from_tag(ap, tag);
671 dev_err(ap->dev, "failed to get qc");
676 /* To be picked up by completion functions */
677 qc->ap->link.active_tag = tag;
678 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
680 /* Let libata/scsi layers handle error */
681 if (status & ATA_ERR) {
682 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
684 sata_dwc_qc_complete(ap, qc, 1);
689 /* Process completed command */
690 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
691 get_prot_descript(qc->tf.protocol));
692 if (ata_is_dma(qc->tf.protocol)) {
693 hsdevp->dma_interrupt_count++;
694 if (hsdevp->dma_pending[tag] == \
695 SATA_DWC_DMA_PENDING_NONE)
696 dev_warn(ap->dev, "%s: DMA not pending?\n",
698 if ((hsdevp->dma_interrupt_count % 2) == 0)
699 sata_dwc_dma_xfer_complete(ap, 1);
701 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
707 ap->stats.idle_irq++;
708 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
710 } /* while tag_mask */
713 * Check to see if any commands completed while we were processing our
714 * initial set of completed commands (read status clears interrupts,
715 * so we might miss a completed command interrupt if one came in while
716 * we were processing --we read status as part of processing a completed
719 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
720 if (sactive2 != sactive) {
722 "More completed - sactive=0x%x sactive2=0x%x\n",
728 spin_unlock_irqrestore(&host->lock, flags);
729 return IRQ_RETVAL(handled);
732 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
734 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
735 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
737 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
738 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
739 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
740 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
741 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
742 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
745 * This should not happen, it indicates the driver is out of
746 * sync. If it does happen, clear dmacr anyway.
749 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
750 __func__, tag, hsdevp->dma_pending[tag], dmacr);
751 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
752 SATA_DWC_DMACR_TXRXCH_CLEAR);
756 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
758 struct ata_queued_cmd *qc;
759 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
760 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
763 tag = ap->link.active_tag;
764 qc = ata_qc_from_tag(ap, tag);
766 dev_err(ap->dev, "failed to get qc");
773 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
774 __func__, qc->hw_tag, qc->tf.command,
775 get_dma_dir_descript(qc->dma_dir),
776 get_prot_descript(qc->tf.protocol),
777 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
781 if (ata_is_dma(qc->tf.protocol)) {
782 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
784 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
786 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
789 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
790 sata_dwc_qc_complete(ap, qc, check_status);
791 ap->link.active_tag = ATA_TAG_POISON;
793 sata_dwc_qc_complete(ap, qc, check_status);
797 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
803 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
804 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
805 hsdev->sactive_queued = 0;
806 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
808 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
809 dev_err(ap->dev, "TX DMA PENDING\n");
810 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
811 dev_err(ap->dev, "RX DMA PENDING\n");
813 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
814 qc->tf.command, status, ap->print_id, qc->tf.protocol);
816 /* clear active bit */
817 mask = (~(qcmd_tag_to_mask(tag)));
818 hsdev->sactive_queued = hsdev->sactive_queued & mask;
819 hsdev->sactive_issued = hsdev->sactive_issued & mask;
824 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
826 /* Enable selective interrupts by setting the interrupt maskregister*/
827 sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
828 SATA_DWC_INTMR_ERRM |
829 SATA_DWC_INTMR_NEWFPM |
830 SATA_DWC_INTMR_PMABRTM |
831 SATA_DWC_INTMR_DMATM);
833 * Unmask the error bits that should trigger an error interrupt by
834 * setting the error mask register.
836 sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
838 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
839 __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
840 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
843 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
845 port->cmd_addr = base + 0x00;
846 port->data_addr = base + 0x00;
848 port->error_addr = base + 0x04;
849 port->feature_addr = base + 0x04;
851 port->nsect_addr = base + 0x08;
853 port->lbal_addr = base + 0x0c;
854 port->lbam_addr = base + 0x10;
855 port->lbah_addr = base + 0x14;
857 port->device_addr = base + 0x18;
858 port->command_addr = base + 0x1c;
859 port->status_addr = base + 0x1c;
861 port->altstatus_addr = base + 0x20;
862 port->ctl_addr = base + 0x20;
865 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
867 struct sata_dwc_device *hsdev = hsdevp->hsdev;
868 struct device *dev = hsdev->dev;
870 #ifdef CONFIG_SATA_DWC_OLD_DMA
871 if (!of_find_property(dev->of_node, "dmas", NULL))
872 return sata_dwc_dma_get_channel_old(hsdevp);
875 hsdevp->chan = dma_request_chan(dev, "sata-dma");
876 if (IS_ERR(hsdevp->chan)) {
877 dev_err(dev, "failed to allocate dma channel: %ld\n",
878 PTR_ERR(hsdevp->chan));
879 return PTR_ERR(hsdevp->chan);
886 * Function : sata_dwc_port_start
887 * arguments : struct ata_ioports *port
888 * Return value : returns 0 if success, error code otherwise
889 * This function allocates the scatter gather LLI table for AHB DMA
891 static int sata_dwc_port_start(struct ata_port *ap)
894 struct sata_dwc_device *hsdev;
895 struct sata_dwc_device_port *hsdevp = NULL;
899 hsdev = HSDEV_FROM_AP(ap);
901 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
903 hsdev->host = ap->host;
904 pdev = ap->host->dev;
906 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
911 /* Allocate Port Struct */
912 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
917 hsdevp->hsdev = hsdev;
919 err = sata_dwc_dma_get_channel(hsdevp);
923 err = phy_power_on(hsdev->phy);
927 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
928 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
930 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
931 ap->bmdma_prd_dma = 0;
933 if (ap->port_no == 0) {
934 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
936 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
937 SATA_DWC_DMACR_TXRXCH_CLEAR);
939 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
941 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
942 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
943 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
946 /* Clear any error bits before libata starts issuing commands */
948 ap->private_data = hsdevp;
949 dev_dbg(ap->dev, "%s: done\n", __func__);
955 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
959 static void sata_dwc_port_stop(struct ata_port *ap)
961 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
962 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
964 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
966 dmaengine_terminate_sync(hsdevp->chan);
967 dma_release_channel(hsdevp->chan);
968 phy_power_off(hsdev->phy);
971 ap->private_data = NULL;
975 * Function : sata_dwc_exec_command_by_tag
976 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
977 * Return value : None
978 * This function keeps track of individual command tag ids and calls
979 * ata_exec_command in libata
981 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
982 struct ata_taskfile *tf,
983 u8 tag, u32 cmd_issued)
985 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
987 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
988 ata_get_cmd_descript(tf->command), tag);
990 hsdevp->cmd_issued[tag] = cmd_issued;
993 * Clear SError before executing a new command.
994 * sata_dwc_scr_write and read can not be used here. Clearing the PM
995 * managed SError register for the disk needs to be done before the
996 * task file is loaded.
999 ata_sff_exec_command(ap, tf);
1002 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1004 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1005 SATA_DWC_CMD_ISSUED_PEND);
1008 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1010 u8 tag = qc->hw_tag;
1012 if (ata_is_ncq(qc->tf.protocol)) {
1013 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1014 __func__, qc->ap->link.sactive, tag);
1018 sata_dwc_bmdma_setup_by_tag(qc, tag);
1021 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1025 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1026 struct ata_port *ap = qc->ap;
1027 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1028 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
1029 int dir = qc->dma_dir;
1031 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1033 if (dir == DMA_TO_DEVICE)
1034 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1036 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1039 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1040 __func__, hsdevp->cmd_issued[tag], tag);
1045 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1046 __func__, qc, tag, qc->tf.command,
1047 get_dma_dir_descript(qc->dma_dir), start_dma);
1048 sata_dwc_tf_dump(ap, &qc->tf);
1051 sata_dwc_scr_read(&ap->link, SCR_ERROR, ®);
1052 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1053 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1057 if (dir == DMA_TO_DEVICE)
1058 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1059 SATA_DWC_DMACR_TXCHEN);
1061 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1062 SATA_DWC_DMACR_RXCHEN);
1064 /* Enable AHB DMA transfer on the specified channel */
1065 dmaengine_submit(desc);
1066 dma_async_issue_pending(hsdevp->chan);
1070 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1072 u8 tag = qc->hw_tag;
1074 if (ata_is_ncq(qc->tf.protocol)) {
1075 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1076 __func__, qc->ap->link.sactive, tag);
1080 dev_dbg(qc->ap->dev, "%s\n", __func__);
1081 sata_dwc_bmdma_start_by_tag(qc, tag);
1084 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1087 u8 tag = qc->hw_tag;
1088 struct ata_port *ap = qc->ap;
1089 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1092 if (qc->hw_tag > 0 || ap->link.sactive > 1)
1094 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1095 __func__, ap->print_id, qc->tf.command,
1096 ata_get_cmd_descript(qc->tf.command),
1097 qc->hw_tag, get_prot_descript(qc->tf.protocol),
1098 ap->link.active_tag, ap->link.sactive);
1101 if (!ata_is_ncq(qc->tf.protocol))
1104 if (ata_is_dma(qc->tf.protocol)) {
1105 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1106 if (!hsdevp->desc[tag])
1107 return AC_ERR_SYSTEM;
1109 hsdevp->desc[tag] = NULL;
1112 if (ata_is_ncq(qc->tf.protocol)) {
1113 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1114 sactive |= (0x00000001 << tag);
1115 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1117 dev_dbg(qc->ap->dev,
1118 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1119 __func__, tag, qc->ap->link.sactive, sactive);
1121 ap->ops->sff_tf_load(ap, &qc->tf);
1122 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1123 SATA_DWC_CMD_ISSUED_PEND);
1125 return ata_bmdma_qc_issue(qc);
1130 static void sata_dwc_error_handler(struct ata_port *ap)
1132 ata_sff_error_handler(ap);
1135 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1136 unsigned long deadline)
1138 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1141 ret = sata_sff_hardreset(link, class, deadline);
1143 sata_dwc_enable_interrupts(hsdev);
1145 /* Reconfigure the DMA control register */
1146 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1147 SATA_DWC_DMACR_TXRXCH_CLEAR);
1149 /* Reconfigure the DMA Burst Transaction Size register */
1150 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1151 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1152 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1157 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1159 /* SATA DWC is master only */
1163 * scsi mid-layer and libata interface structures
1165 static struct scsi_host_template sata_dwc_sht = {
1166 ATA_NCQ_SHT(DRV_NAME),
1168 * test-only: Currently this driver doesn't handle NCQ
1169 * correctly. We enable NCQ but set the queue depth to a
1170 * max of 1. This will get fixed in in a future release.
1172 .sg_tablesize = LIBATA_MAX_PRD,
1173 /* .can_queue = ATA_MAX_QUEUE, */
1175 * Make sure a LLI block is not created that will span 8K max FIS
1176 * boundary. If the block spans such a FIS boundary, there is a chance
1177 * that a DMA burst will cross that boundary -- this results in an
1178 * error in the host controller.
1180 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
1183 static struct ata_port_operations sata_dwc_ops = {
1184 .inherits = &ata_sff_port_ops,
1186 .error_handler = sata_dwc_error_handler,
1187 .hardreset = sata_dwc_hardreset,
1189 .qc_issue = sata_dwc_qc_issue,
1191 .scr_read = sata_dwc_scr_read,
1192 .scr_write = sata_dwc_scr_write,
1194 .port_start = sata_dwc_port_start,
1195 .port_stop = sata_dwc_port_stop,
1197 .sff_dev_select = sata_dwc_dev_select,
1199 .bmdma_setup = sata_dwc_bmdma_setup,
1200 .bmdma_start = sata_dwc_bmdma_start,
1203 static const struct ata_port_info sata_dwc_port_info[] = {
1205 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1206 .pio_mask = ATA_PIO4,
1207 .udma_mask = ATA_UDMA6,
1208 .port_ops = &sata_dwc_ops,
1212 static int sata_dwc_probe(struct platform_device *ofdev)
1214 struct sata_dwc_device *hsdev;
1216 char *ver = (char *)&versionr;
1220 struct ata_host *host;
1221 struct ata_port_info pi = sata_dwc_port_info[0];
1222 const struct ata_port_info *ppi[] = { &pi, NULL };
1223 struct device_node *np = ofdev->dev.of_node;
1224 struct resource *res;
1226 /* Allocate DWC SATA device */
1227 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1228 hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1229 if (!host || !hsdev)
1232 host->private_data = hsdev;
1234 /* Ioremap SATA registers */
1235 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1236 base = devm_ioremap_resource(&ofdev->dev, res);
1238 return PTR_ERR(base);
1239 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1241 /* Synopsys DWC SATA specific Registers */
1242 hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1243 hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
1246 host->ports[0]->ioaddr.cmd_addr = base;
1247 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1248 sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1250 /* Read the ID and Version Registers */
1251 idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1252 versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1253 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1254 idr, ver[0], ver[1], ver[2]);
1256 /* Save dev for later use in dev_xxx() routines */
1257 hsdev->dev = &ofdev->dev;
1259 /* Enable SATA Interrupts */
1260 sata_dwc_enable_interrupts(hsdev);
1262 /* Get SATA interrupt number */
1263 irq = irq_of_parse_and_map(np, 0);
1264 if (irq == NO_IRQ) {
1265 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1269 #ifdef CONFIG_SATA_DWC_OLD_DMA
1270 if (!of_find_property(np, "dmas", NULL)) {
1271 err = sata_dwc_dma_init_old(ofdev, hsdev);
1277 hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1278 if (IS_ERR(hsdev->phy))
1279 return PTR_ERR(hsdev->phy);
1281 err = phy_init(hsdev->phy);
1286 * Now, register with libATA core, this will also initiate the
1287 * device discovery process, invoking our port_start() handler &
1288 * error_handler() to execute a dummy Softreset EH session
1290 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1292 dev_err(&ofdev->dev, "failed to activate host");
1297 phy_exit(hsdev->phy);
1301 static int sata_dwc_remove(struct platform_device *ofdev)
1303 struct device *dev = &ofdev->dev;
1304 struct ata_host *host = dev_get_drvdata(dev);
1305 struct sata_dwc_device *hsdev = host->private_data;
1307 ata_host_detach(host);
1309 phy_exit(hsdev->phy);
1311 #ifdef CONFIG_SATA_DWC_OLD_DMA
1312 /* Free SATA DMA resources */
1313 sata_dwc_dma_exit_old(hsdev);
1316 dev_dbg(&ofdev->dev, "done\n");
1320 static const struct of_device_id sata_dwc_match[] = {
1321 { .compatible = "amcc,sata-460ex", },
1324 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1326 static struct platform_driver sata_dwc_driver = {
1329 .of_match_table = sata_dwc_match,
1331 .probe = sata_dwc_probe,
1332 .remove = sata_dwc_remove,
1335 module_platform_driver(sata_dwc_driver);
1337 MODULE_LICENSE("GPL");
1338 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1339 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1340 MODULE_VERSION(DRV_VERSION);