2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat, all rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 * An ATA driver for the legacy ATA ports.
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
29 * http://www.ryston.cz/petr/vlb/qd6500.html
30 * http://www.ryston.cz/petr/vlb/qd6580.html
32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
34 * Samuel Thibault <samuel.thibault@ens-lyon.org>
36 * Unsupported but docs exist:
37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
40 * on PC class systems. There are three hybrid devices that are exceptions
41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
47 * Support for the Winbond 83759A when operating in advanced mode.
48 * Multichip mode is not currently supported.
50 * Use the autospeed and pio_mask options with:
51 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
54 * Winbond W83759A, Promise PDC20230-B
56 * For now use autospeed and pio_mask as above with the W83759A. This may
61 #include <linux/async.h>
62 #include <linux/kernel.h>
63 #include <linux/module.h>
64 #include <linux/pci.h>
65 #include <linux/init.h>
66 #include <linux/blkdev.h>
67 #include <linux/delay.h>
68 #include <scsi/scsi_host.h>
69 #include <linux/ata.h>
70 #include <linux/libata.h>
71 #include <linux/platform_device.h>
73 #define DRV_NAME "pata_legacy"
74 #define DRV_VERSION "0.6.5"
79 module_param(all, int, 0444);
80 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
92 QDI6580DP = 9, /* Dual channel mode is different */
103 enum controller type;
104 struct platform_device *platform_dev;
107 struct legacy_probe {
112 enum controller type;
113 unsigned long private;
116 struct legacy_controller {
118 struct ata_port_operations *ops;
119 unsigned int pio_mask;
122 int (*setup)(struct platform_device *, struct legacy_probe *probe,
123 struct legacy_data *data);
126 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
128 static struct legacy_probe probe_list[NR_HOST];
129 static struct legacy_data legacy_data[NR_HOST];
130 static struct ata_host *legacy_host[NR_HOST];
131 static int nr_legacy_host;
134 static int probe_all; /* Set to check all ISA port ranges */
135 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
136 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
137 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
138 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
139 static int autospeed; /* Chip present which snoops speed changes */
140 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
141 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
143 /* Set to probe QDI controllers */
144 #ifdef CONFIG_PATA_QDI_MODULE
150 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
151 static int winbond = 1; /* Set to probe Winbond controllers,
152 give I/O port if non standard */
154 static int winbond; /* Set to probe Winbond controllers,
155 give I/O port if non standard */
159 * legacy_probe_add - Add interface to probe list
160 * @port: Controller port
162 * @type: Controller type
163 * @private: Controller specific info
165 * Add an entry into the probe list for ATA controllers. This is used
166 * to add the default ISA slots and then to build up the table
167 * further according to other ISA/VLB/Weird device scans
169 * An I/O port list is used to keep ordering stable and sane, as we
170 * don't have any good way to talk about ordering otherwise
173 static int legacy_probe_add(unsigned long port, unsigned int irq,
174 enum controller type, unsigned long private)
176 struct legacy_probe *lp = &probe_list[0];
178 struct legacy_probe *free = NULL;
180 for (i = 0; i < NR_HOST; i++) {
181 if (lp->port == 0 && free == NULL)
183 /* Matching port, or the correct slot for ordering */
184 if (lp->port == port || legacy_port[i] == port) {
191 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
194 /* Fill in the entry for later probing */
198 free->private = private;
204 * legacy_set_mode - mode setting
206 * @unused: Device that failed when error is returned
208 * Use a non standard set_mode function. We don't want to be tuned.
210 * The BIOS configured everything. Our job is not to fiddle. Just use
211 * whatever PIO the hardware is using and leave it at that. When we
212 * get some kind of nice user driven API for control then we can
213 * expand on this as per hdparm in the base kernel.
216 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
218 struct ata_device *dev;
220 ata_for_each_dev(dev, link, ENABLED) {
221 ata_dev_info(dev, "configured for PIO\n");
222 dev->pio_mode = XFER_PIO_0;
223 dev->xfer_mode = XFER_PIO_0;
224 dev->xfer_shift = ATA_SHIFT_PIO;
225 dev->flags |= ATA_DFLAG_PIO;
230 static struct scsi_host_template legacy_sht = {
231 ATA_PIO_SHT(DRV_NAME),
234 static const struct ata_port_operations legacy_base_port_ops = {
235 .inherits = &ata_sff_port_ops,
236 .cable_detect = ata_cable_40wire,
240 * These ops are used if the user indicates the hardware
241 * snoops the commands to decide on the mode and handles the
242 * mode selection "magically" itself. Several legacy controllers
243 * do this. The mode range can be set if it is not 0x1F by setting
247 static struct ata_port_operations simple_port_ops = {
248 .inherits = &legacy_base_port_ops,
249 .sff_data_xfer = ata_sff_data_xfer_noirq,
252 static struct ata_port_operations legacy_port_ops = {
253 .inherits = &legacy_base_port_ops,
254 .sff_data_xfer = ata_sff_data_xfer_noirq,
255 .set_mode = legacy_set_mode,
259 * Promise 20230C and 20620 support
261 * This controller supports PIO0 to PIO2. We set PIO timings
262 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
263 * support is weird being DMA to controller and PIO'd to the host
267 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
270 int pio = adev->pio_mode - XFER_PIO_0;
274 /* Safe as UP only. Force I/Os to occur together */
276 local_irq_save(flags);
278 /* Unlock the control interface */
281 outb(inb(0x1F2) | 0x80, 0x1F2);
288 while ((inb(0x1F2) & 0x80) && --tries);
290 local_irq_restore(flags);
292 outb(inb(0x1F4) & 0x07, 0x1F4);
295 rt &= 0x07 << (3 * adev->devno);
297 rt |= (1 + 3 * pio) << (3 * adev->devno);
300 outb(inb(0x1F2) | 0x01, 0x1F2);
306 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
307 unsigned char *buf, unsigned int buflen, int rw)
309 struct ata_device *dev = qc->dev;
310 struct ata_port *ap = dev->link->ap;
311 int slop = buflen & 3;
313 /* 32bit I/O capable *and* we need to write a whole number of dwords */
314 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
315 && (ap->pflags & ATA_PFLAG_PIO32)) {
318 local_irq_save(flags);
320 /* Perform the 32bit I/O synchronization sequence */
321 ioread8(ap->ioaddr.nsect_addr);
322 ioread8(ap->ioaddr.nsect_addr);
323 ioread8(ap->ioaddr.nsect_addr);
327 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
329 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
331 if (unlikely(slop)) {
335 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
336 memcpy(buf + buflen - slop, &pad, slop);
338 memcpy(&pad, buf + buflen - slop, slop);
339 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
343 local_irq_restore(flags);
345 buflen = ata_sff_data_xfer_noirq(qc, buf, buflen, rw);
350 static struct ata_port_operations pdc20230_port_ops = {
351 .inherits = &legacy_base_port_ops,
352 .set_piomode = pdc20230_set_piomode,
353 .sff_data_xfer = pdc_data_xfer_vlb,
357 * Holtek 6560A support
359 * This controller supports PIO0 to PIO2 (no IORDY even though higher
360 * timings can be loaded).
363 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
368 /* Get the timing data in cycles. For now play safe at 50Mhz */
369 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
371 active = clamp_val(t.active, 2, 15);
372 recover = clamp_val(t.recover, 4, 15);
379 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
380 ioread8(ap->ioaddr.status_addr);
383 static struct ata_port_operations ht6560a_port_ops = {
384 .inherits = &legacy_base_port_ops,
385 .set_piomode = ht6560a_set_piomode,
389 * Holtek 6560B support
391 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
392 * setting unless we see an ATAPI device in which case we force it off.
394 * FIXME: need to implement 2nd channel support.
397 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
402 /* Get the timing data in cycles. For now play safe at 50Mhz */
403 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
405 active = clamp_val(t.active, 2, 15);
406 recover = clamp_val(t.recover, 2, 16) & 0x0F;
413 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
415 if (adev->class != ATA_DEV_ATA) {
416 u8 rconf = inb(0x3E6);
422 ioread8(ap->ioaddr.status_addr);
425 static struct ata_port_operations ht6560b_port_ops = {
426 .inherits = &legacy_base_port_ops,
427 .set_piomode = ht6560b_set_piomode,
431 * Opti core chipset helpers
435 * opti_syscfg - read OPTI chipset configuration
436 * @reg: Configuration register to read
438 * Returns the value of an OPTI system board configuration register.
441 static u8 opti_syscfg(u8 reg)
446 /* Uniprocessor chipset and must force cycles adjancent */
447 local_irq_save(flags);
450 local_irq_restore(flags);
457 * This controller supports PIO0 to PIO3.
460 static void opti82c611a_set_piomode(struct ata_port *ap,
461 struct ata_device *adev)
463 u8 active, recover, setup;
465 struct ata_device *pair = ata_dev_pair(adev);
467 int khz[4] = { 50000, 40000, 33000, 25000 };
470 /* Enter configuration mode */
471 ioread16(ap->ioaddr.error_addr);
472 ioread16(ap->ioaddr.error_addr);
473 iowrite8(3, ap->ioaddr.nsect_addr);
475 /* Read VLB clock strapping */
476 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
478 /* Get the timing data in cycles */
479 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
481 /* Setup timing is shared */
483 struct ata_timing tp;
484 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
486 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
489 active = clamp_val(t.active, 2, 17) - 2;
490 recover = clamp_val(t.recover, 1, 16) - 1;
491 setup = clamp_val(t.setup, 1, 4) - 1;
493 /* Select the right timing bank for write timing */
494 rc = ioread8(ap->ioaddr.lbal_addr);
496 rc |= (adev->devno << 7);
497 iowrite8(rc, ap->ioaddr.lbal_addr);
499 /* Write the timings */
500 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
502 /* Select the right bank for read timings, also
503 load the shared timings for address */
504 rc = ioread8(ap->ioaddr.device_addr);
506 rc |= adev->devno; /* Index select */
507 rc |= (setup << 4) | 0x04;
508 iowrite8(rc, ap->ioaddr.device_addr);
510 /* Load the read timings */
511 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
513 /* Ensure the timing register mode is right */
514 rc = ioread8(ap->ioaddr.lbal_addr);
517 iowrite8(rc, ap->ioaddr.lbal_addr);
519 /* Exit command mode */
520 iowrite8(0x83, ap->ioaddr.nsect_addr);
524 static struct ata_port_operations opti82c611a_port_ops = {
525 .inherits = &legacy_base_port_ops,
526 .set_piomode = opti82c611a_set_piomode,
532 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
533 * version is dual channel but doesn't have a lot of unique registers.
536 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
538 u8 active, recover, setup;
540 struct ata_device *pair = ata_dev_pair(adev);
542 int khz[4] = { 50000, 40000, 33000, 25000 };
547 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
549 /* Enter configuration mode */
550 ioread16(ap->ioaddr.error_addr);
551 ioread16(ap->ioaddr.error_addr);
552 iowrite8(3, ap->ioaddr.nsect_addr);
554 /* Read VLB clock strapping */
555 clock = 1000000000 / khz[sysclk];
557 /* Get the timing data in cycles */
558 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
560 /* Setup timing is shared */
562 struct ata_timing tp;
563 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
565 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
568 active = clamp_val(t.active, 2, 17) - 2;
569 recover = clamp_val(t.recover, 1, 16) - 1;
570 setup = clamp_val(t.setup, 1, 4) - 1;
572 /* Select the right timing bank for write timing */
573 rc = ioread8(ap->ioaddr.lbal_addr);
575 rc |= (adev->devno << 7);
576 iowrite8(rc, ap->ioaddr.lbal_addr);
578 /* Write the timings */
579 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
581 /* Select the right bank for read timings, also
582 load the shared timings for address */
583 rc = ioread8(ap->ioaddr.device_addr);
585 rc |= adev->devno; /* Index select */
586 rc |= (setup << 4) | 0x04;
587 iowrite8(rc, ap->ioaddr.device_addr);
589 /* Load the read timings */
590 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
592 /* Ensure the timing register mode is right */
593 rc = ioread8(ap->ioaddr.lbal_addr);
596 iowrite8(rc, ap->ioaddr.lbal_addr);
598 /* Exit command mode */
599 iowrite8(0x83, ap->ioaddr.nsect_addr);
601 /* We need to know this for quad device on the MVB */
602 ap->host->private_data = ap;
606 * opt82c465mv_qc_issue - command issue
607 * @qc: command pending
609 * Called when the libata layer is about to issue a command. We wrap
610 * this interface so that we can load the correct ATA timings. The
611 * MVB has a single set of timing registers and these are shared
612 * across channels. As there are two registers we really ought to
613 * track the last two used values as a sort of register window. For
614 * now we just reload on a channel switch. On the single channel
615 * setup this condition never fires so we do nothing extra.
617 * FIXME: dual channel needs ->serialize support
620 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
622 struct ata_port *ap = qc->ap;
623 struct ata_device *adev = qc->dev;
625 /* If timings are set and for the wrong channel (2nd test is
626 due to a libata shortcoming and will eventually go I hope) */
627 if (ap->host->private_data != ap->host
628 && ap->host->private_data != NULL)
629 opti82c46x_set_piomode(ap, adev);
631 return ata_sff_qc_issue(qc);
634 static struct ata_port_operations opti82c46x_port_ops = {
635 .inherits = &legacy_base_port_ops,
636 .set_piomode = opti82c46x_set_piomode,
637 .qc_issue = opti82c46x_qc_issue,
641 * qdi65x0_set_piomode - PIO setup for QDI65x0
645 * In single channel mode the 6580 has one clock per device and we can
646 * avoid the requirement to clock switch. We also have to load the timing
647 * into the right clock according to whether we are master or slave.
649 * In dual channel mode the 6580 has one clock per channel and we have
650 * to software clockswitch in qc_issue.
653 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
656 struct legacy_data *ld_qdi = ap->host->private_data;
657 int active, recovery;
660 /* Get the timing data in cycles */
661 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
664 active = 8 - clamp_val(t.active, 1, 8);
665 recovery = 18 - clamp_val(t.recover, 3, 18);
667 active = 9 - clamp_val(t.active, 2, 9);
668 recovery = 15 - clamp_val(t.recover, 0, 15);
670 timing = (recovery << 4) | active | 0x08;
671 ld_qdi->clock[adev->devno] = timing;
673 if (ld_qdi->type == QDI6580)
674 outb(timing, ld_qdi->timing + 2 * adev->devno);
676 outb(timing, ld_qdi->timing + 2 * ap->port_no);
679 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
680 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
684 * qdi_qc_issue - command issue
685 * @qc: command pending
687 * Called when the libata layer is about to issue a command. We wrap
688 * this interface so that we can load the correct ATA timings.
691 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
693 struct ata_port *ap = qc->ap;
694 struct ata_device *adev = qc->dev;
695 struct legacy_data *ld_qdi = ap->host->private_data;
697 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
698 if (adev->pio_mode) {
699 ld_qdi->last = ld_qdi->clock[adev->devno];
700 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
704 return ata_sff_qc_issue(qc);
707 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
709 unsigned int buflen, int rw)
711 struct ata_device *adev = qc->dev;
712 struct ata_port *ap = adev->link->ap;
713 int slop = buflen & 3;
715 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
716 && (ap->pflags & ATA_PFLAG_PIO32)) {
718 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
720 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
722 if (unlikely(slop)) {
726 memcpy(&pad, buf + buflen - slop, slop);
727 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
729 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
730 memcpy(buf + buflen - slop, &pad, slop);
733 return (buflen + 3) & ~3;
735 return ata_sff_data_xfer(qc, buf, buflen, rw);
738 static int qdi_port(struct platform_device *dev,
739 struct legacy_probe *lp, struct legacy_data *ld)
741 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
743 ld->timing = lp->private;
747 static struct ata_port_operations qdi6500_port_ops = {
748 .inherits = &legacy_base_port_ops,
749 .set_piomode = qdi65x0_set_piomode,
750 .qc_issue = qdi_qc_issue,
751 .sff_data_xfer = vlb32_data_xfer,
754 static struct ata_port_operations qdi6580_port_ops = {
755 .inherits = &legacy_base_port_ops,
756 .set_piomode = qdi65x0_set_piomode,
757 .sff_data_xfer = vlb32_data_xfer,
760 static struct ata_port_operations qdi6580dp_port_ops = {
761 .inherits = &legacy_base_port_ops,
762 .set_piomode = qdi65x0_set_piomode,
763 .qc_issue = qdi_qc_issue,
764 .sff_data_xfer = vlb32_data_xfer,
767 static DEFINE_SPINLOCK(winbond_lock);
769 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
772 spin_lock_irqsave(&winbond_lock, flags);
773 outb(reg, port + 0x01);
774 outb(val, port + 0x02);
775 spin_unlock_irqrestore(&winbond_lock, flags);
778 static u8 winbond_readcfg(unsigned long port, u8 reg)
783 spin_lock_irqsave(&winbond_lock, flags);
784 outb(reg, port + 0x01);
785 val = inb(port + 0x02);
786 spin_unlock_irqrestore(&winbond_lock, flags);
791 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
794 struct legacy_data *ld_winbond = ap->host->private_data;
795 int active, recovery;
797 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
799 reg = winbond_readcfg(ld_winbond->timing, 0x81);
801 /* Get the timing data in cycles */
802 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
803 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
805 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
807 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
808 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
809 timing = (active << 4) | recovery;
810 winbond_writecfg(ld_winbond->timing, timing, reg);
812 /* Load the setup timing */
815 if (adev->class != ATA_DEV_ATA)
816 reg |= 0x08; /* FIFO off */
817 if (!ata_pio_need_iordy(adev))
818 reg |= 0x02; /* IORDY off */
819 reg |= (clamp_val(t.setup, 0, 3) << 6);
820 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
823 static int winbond_port(struct platform_device *dev,
824 struct legacy_probe *lp, struct legacy_data *ld)
826 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
828 ld->timing = lp->private;
832 static struct ata_port_operations winbond_port_ops = {
833 .inherits = &legacy_base_port_ops,
834 .set_piomode = winbond_set_piomode,
835 .sff_data_xfer = vlb32_data_xfer,
838 static struct legacy_controller controllers[] = {
839 {"BIOS", &legacy_port_ops, ATA_PIO4,
840 ATA_FLAG_NO_IORDY, 0, NULL },
841 {"Snooping", &simple_port_ops, ATA_PIO4,
843 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
845 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
846 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
847 ATA_FLAG_NO_IORDY, 0, NULL },
848 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
849 ATA_FLAG_NO_IORDY, 0, NULL },
850 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
852 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
854 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
856 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
857 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
858 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
859 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
860 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
861 {"W83759A", &winbond_port_ops, ATA_PIO4,
862 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
867 * probe_chip_type - Discover controller
868 * @probe: Probe entry to check
870 * Probe an ATA port and identify the type of controller. We don't
871 * check if the controller appears to be driveless at this point.
874 static __init int probe_chip_type(struct legacy_probe *probe)
876 int mask = 1 << probe->slot;
878 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
879 u8 reg = winbond_readcfg(winbond, 0x81);
880 reg |= 0x80; /* jumpered mode off */
881 winbond_writecfg(winbond, 0x81, reg);
882 reg = winbond_readcfg(winbond, 0x83);
883 reg |= 0xF0; /* local control */
884 winbond_writecfg(winbond, 0x83, reg);
885 reg = winbond_readcfg(winbond, 0x85);
886 reg |= 0xF0; /* programmable timing */
887 winbond_writecfg(winbond, 0x85, reg);
889 reg = winbond_readcfg(winbond, 0x81);
894 if (probe->port == 0x1F0) {
896 local_irq_save(flags);
898 outb(inb(0x1F2) | 0x80, 0x1F2);
906 if ((inb(0x1F2) & 0x80) == 0) {
907 /* PDC20230c or 20630 ? */
908 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
912 local_irq_restore(flags);
918 if (inb(0x1F2) == 0x00)
919 printk(KERN_INFO "PDC20230-B VLB ATA "
920 "controller detected.\n");
921 local_irq_restore(flags);
930 if (opti82c611a & mask)
932 if (opti82c46x & mask)
934 if (autospeed & mask)
941 * legacy_init_one - attach a legacy interface
944 * Register an ISA bus IDE interface. Such interfaces are PIO and we
945 * assume do not support IRQ sharing.
948 static __init int legacy_init_one(struct legacy_probe *probe)
950 struct legacy_controller *controller = &controllers[probe->type];
951 int pio_modes = controller->pio_mask;
952 unsigned long io = probe->port;
953 u32 mask = (1 << probe->slot);
954 struct ata_port_operations *ops = controller->ops;
955 struct legacy_data *ld = &legacy_data[probe->slot];
956 struct ata_host *host = NULL;
958 struct platform_device *pdev;
959 struct ata_device *dev;
960 void __iomem *io_addr, *ctrl_addr;
961 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
964 iordy |= controller->flags;
966 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
968 return PTR_ERR(pdev);
971 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
972 devm_request_region(&pdev->dev, io + 0x0206, 1,
973 "pata_legacy") == NULL)
977 io_addr = devm_ioport_map(&pdev->dev, io, 8);
978 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
979 if (!io_addr || !ctrl_addr)
981 ld->type = probe->type;
982 if (controller->setup)
983 if (controller->setup(pdev, probe, ld) < 0)
985 host = ata_host_alloc(&pdev->dev, 1);
991 ap->pio_mask = pio_modes;
992 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
993 ap->pflags |= controller->pflags;
994 ap->ioaddr.cmd_addr = io_addr;
995 ap->ioaddr.altstatus_addr = ctrl_addr;
996 ap->ioaddr.ctl_addr = ctrl_addr;
997 ata_sff_std_ports(&ap->ioaddr);
998 ap->host->private_data = ld;
1000 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
1002 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
1006 async_synchronize_full();
1007 ld->platform_dev = pdev;
1009 /* Nothing found means we drop the port as its probably not there */
1012 ata_for_each_dev(dev, &ap->link, ALL) {
1013 if (!ata_dev_absent(dev)) {
1014 legacy_host[probe->slot] = host;
1015 ld->platform_dev = pdev;
1019 ata_host_detach(host);
1021 platform_device_unregister(pdev);
1026 * legacy_check_special_cases - ATA special cases
1027 * @p: PCI device to check
1028 * @master: set this if we find an ATA master
1029 * @master: set this if we find an ATA secondary
1031 * A small number of vendors implemented early PCI ATA interfaces
1032 * on bridge logic without the ATA interface being PCI visible.
1033 * Where we have a matching PCI driver we must skip the relevant
1034 * device here. If we don't know about it then the legacy driver
1035 * is the right driver anyway.
1038 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1041 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1042 if (p->vendor == 0x1078 && p->device == 0x0000) {
1043 *primary = *secondary = 1;
1046 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1047 if (p->vendor == 0x1078 && p->device == 0x0002) {
1048 *primary = *secondary = 1;
1051 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1052 if (p->vendor == 0x8086 && p->device == 0x1234) {
1054 pci_read_config_word(p, 0x6C, &r);
1056 /* ATA port enabled */
1066 static __init void probe_opti_vlb(void)
1068 /* If an OPTI 82C46X is present find out where the channels are */
1069 static const char *optis[4] = {
1074 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1076 opti82c46x = 3; /* Assume master and slave first */
1077 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1080 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1081 ctrl = opti_syscfg(0xAC);
1082 /* Check enabled and this port is the 465MV port. On the
1083 MVB we may have two channels */
1086 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1087 legacy_probe_add(0x170, 15, OPTI46X, 0);
1090 legacy_probe_add(0x170, 15, OPTI46X, 0);
1092 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1094 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1097 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1099 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1100 /* Check card type */
1101 if ((r & 0xF0) == 0xC0) {
1102 /* QD6500: single channel */
1106 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1109 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1110 /* QD6580: dual channel */
1111 if (!request_region(port + 2 , 2, "pata_qdi")) {
1112 release_region(port, 2);
1115 res = inb(port + 3);
1116 /* Single channel mode ? */
1118 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1120 else { /* Dual channel mode */
1121 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1122 /* port + 0x02, r & 0x04 */
1123 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1125 release_region(port + 2, 2);
1129 static __init void probe_qdi_vlb(void)
1131 unsigned long flags;
1132 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1136 * Check each possible QD65xx base address
1139 for (i = 0; i < 2; i++) {
1140 unsigned long port = qd_port[i];
1144 if (request_region(port, 2, "pata_qdi")) {
1145 /* Check for a card */
1146 local_irq_save(flags);
1147 /* I have no h/w that needs this delay but it
1148 is present in the historic code */
1157 local_irq_restore(flags);
1161 release_region(port, 2);
1164 /* Passes the presence test */
1167 /* Check port agrees with port set */
1168 if ((r & 2) >> 1 == i)
1169 qdi65_identify_port(r, res, port);
1170 release_region(port, 2);
1176 * legacy_init - attach legacy interfaces
1178 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1179 * Right now we do not scan the ide0 and ide1 address but should do so
1180 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1181 * If you fix that note there are special cases to consider like VLB
1182 * drivers and CS5510/20.
1185 static __init int legacy_init(void)
1191 int pci_present = 0;
1192 struct legacy_probe *pl = &probe_list[0];
1195 struct pci_dev *p = NULL;
1197 for_each_pci_dev(p) {
1199 /* Check for any overlap of the system ATA mappings. Native
1200 mode controllers stuck on these addresses or some devices
1201 in 'raid' mode won't be found by the storage class test */
1202 for (r = 0; r < 6; r++) {
1203 if (pci_resource_start(p, r) == 0x1f0)
1205 if (pci_resource_start(p, r) == 0x170)
1208 /* Check for special cases */
1209 legacy_check_special_cases(p, &primary, &secondary);
1211 /* If PCI bus is present then don't probe for tertiary
1217 winbond = 0x130; /* Default port, alt is 1B0 */
1219 if (primary == 0 || all)
1220 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1221 if (secondary == 0 || all)
1222 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1224 if (probe_all || !pci_present) {
1225 /* ISA/VLB extra ports */
1226 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1227 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1228 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1229 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1237 for (i = 0; i < NR_HOST; i++, pl++) {
1240 if (pl->type == UNKNOWN)
1241 pl->type = probe_chip_type(pl);
1243 if (legacy_init_one(pl) == 0)
1251 static __exit void legacy_exit(void)
1255 for (i = 0; i < nr_legacy_host; i++) {
1256 struct legacy_data *ld = &legacy_data[i];
1257 ata_host_detach(legacy_host[i]);
1258 platform_device_unregister(ld->platform_dev);
1262 MODULE_AUTHOR("Alan Cox");
1263 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1264 MODULE_LICENSE("GPL");
1265 MODULE_VERSION(DRV_VERSION);
1266 MODULE_ALIAS("pata_qdi");
1267 MODULE_ALIAS("pata_winbond");
1269 module_param(probe_all, int, 0);
1270 module_param(autospeed, int, 0);
1271 module_param(ht6560a, int, 0);
1272 module_param(ht6560b, int, 0);
1273 module_param(opti82c611a, int, 0);
1274 module_param(opti82c46x, int, 0);
1275 module_param(qdi, int, 0);
1276 module_param(winbond, int, 0);
1277 module_param(pio_mask, int, 0);
1278 module_param(iordy_mask, int, 0);
1280 module_init(legacy_init);
1281 module_exit(legacy_exit);