2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/driver-api/libata.rst
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/pci.h>
38 #include <linux/module.h>
39 #include <linux/libata.h>
40 #include <linux/highmem.h>
44 static struct workqueue_struct *ata_sff_wq;
46 const struct ata_port_operations ata_sff_port_ops = {
47 .inherits = &ata_base_port_ops,
49 .qc_prep = ata_noop_qc_prep,
50 .qc_issue = ata_sff_qc_issue,
51 .qc_fill_rtf = ata_sff_qc_fill_rtf,
53 .freeze = ata_sff_freeze,
55 .prereset = ata_sff_prereset,
56 .softreset = ata_sff_softreset,
57 .hardreset = sata_sff_hardreset,
58 .postreset = ata_sff_postreset,
59 .error_handler = ata_sff_error_handler,
61 .sff_dev_select = ata_sff_dev_select,
62 .sff_check_status = ata_sff_check_status,
63 .sff_tf_load = ata_sff_tf_load,
64 .sff_tf_read = ata_sff_tf_read,
65 .sff_exec_command = ata_sff_exec_command,
66 .sff_data_xfer = ata_sff_data_xfer,
67 .sff_drain_fifo = ata_sff_drain_fifo,
69 .lost_interrupt = ata_sff_lost_interrupt,
71 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
74 * ata_sff_check_status - Read device status reg & clear interrupt
75 * @ap: port where the device is
77 * Reads ATA taskfile status register for currently-selected device
78 * and return its value. This also clears pending interrupts
82 * Inherited from caller.
84 u8 ata_sff_check_status(struct ata_port *ap)
86 return ioread8(ap->ioaddr.status_addr);
88 EXPORT_SYMBOL_GPL(ata_sff_check_status);
91 * ata_sff_altstatus - Read device alternate status reg
92 * @ap: port where the device is
94 * Reads ATA taskfile alternate status register for
95 * currently-selected device and return its value.
97 * Note: may NOT be used as the check_altstatus() entry in
98 * ata_port_operations.
101 * Inherited from caller.
103 static u8 ata_sff_altstatus(struct ata_port *ap)
105 if (ap->ops->sff_check_altstatus)
106 return ap->ops->sff_check_altstatus(ap);
108 return ioread8(ap->ioaddr.altstatus_addr);
112 * ata_sff_irq_status - Check if the device is busy
113 * @ap: port where the device is
115 * Determine if the port is currently busy. Uses altstatus
116 * if available in order to avoid clearing shared IRQ status
117 * when finding an IRQ source. Non ctl capable devices don't
118 * share interrupt lines fortunately for us.
121 * Inherited from caller.
123 static u8 ata_sff_irq_status(struct ata_port *ap)
127 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
128 status = ata_sff_altstatus(ap);
129 /* Not us: We are busy */
130 if (status & ATA_BUSY)
133 /* Clear INTRQ latch */
134 status = ap->ops->sff_check_status(ap);
139 * ata_sff_sync - Flush writes
140 * @ap: Port to wait for.
143 * If we have an mmio device with no ctl and no altstatus
144 * method this will fail. No such devices are known to exist.
147 * Inherited from caller.
150 static void ata_sff_sync(struct ata_port *ap)
152 if (ap->ops->sff_check_altstatus)
153 ap->ops->sff_check_altstatus(ap);
154 else if (ap->ioaddr.altstatus_addr)
155 ioread8(ap->ioaddr.altstatus_addr);
159 * ata_sff_pause - Flush writes and wait 400nS
160 * @ap: Port to pause for.
163 * If we have an mmio device with no ctl and no altstatus
164 * method this will fail. No such devices are known to exist.
167 * Inherited from caller.
170 void ata_sff_pause(struct ata_port *ap)
175 EXPORT_SYMBOL_GPL(ata_sff_pause);
178 * ata_sff_dma_pause - Pause before commencing DMA
179 * @ap: Port to pause for.
181 * Perform I/O fencing and ensure sufficient cycle delays occur
182 * for the HDMA1:0 transition
185 void ata_sff_dma_pause(struct ata_port *ap)
187 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
188 /* An altstatus read will cause the needed delay without
189 messing up the IRQ status */
190 ata_sff_altstatus(ap);
193 /* There are no DMA controllers without ctl. BUG here to ensure
194 we never violate the HDMA1:0 transition timing and risk
198 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
201 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
202 * @ap: port containing status register to be polled
203 * @tmout_pat: impatience timeout in msecs
204 * @tmout: overall timeout in msecs
206 * Sleep until ATA Status register bit BSY clears,
207 * or a timeout occurs.
210 * Kernel thread context (may sleep).
213 * 0 on success, -errno otherwise.
215 int ata_sff_busy_sleep(struct ata_port *ap,
216 unsigned long tmout_pat, unsigned long tmout)
218 unsigned long timer_start, timeout;
221 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
222 timer_start = jiffies;
223 timeout = ata_deadline(timer_start, tmout_pat);
224 while (status != 0xff && (status & ATA_BUSY) &&
225 time_before(jiffies, timeout)) {
227 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
230 if (status != 0xff && (status & ATA_BUSY))
232 "port is slow to respond, please be patient (Status 0x%x)\n",
235 timeout = ata_deadline(timer_start, tmout);
236 while (status != 0xff && (status & ATA_BUSY) &&
237 time_before(jiffies, timeout)) {
239 status = ap->ops->sff_check_status(ap);
245 if (status & ATA_BUSY) {
247 "port failed to respond (%lu secs, Status 0x%x)\n",
248 DIV_ROUND_UP(tmout, 1000), status);
254 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
256 static int ata_sff_check_ready(struct ata_link *link)
258 u8 status = link->ap->ops->sff_check_status(link->ap);
260 return ata_check_ready(status);
264 * ata_sff_wait_ready - sleep until BSY clears, or timeout
265 * @link: SFF link to wait ready status for
266 * @deadline: deadline jiffies for the operation
268 * Sleep until ATA Status register bit BSY clears, or timeout
272 * Kernel thread context (may sleep).
275 * 0 on success, -errno otherwise.
277 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
279 return ata_wait_ready(link, deadline, ata_sff_check_ready);
281 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
284 * ata_sff_set_devctl - Write device control reg
285 * @ap: port where the device is
286 * @ctl: value to write
288 * Writes ATA taskfile device control register.
290 * Note: may NOT be used as the sff_set_devctl() entry in
291 * ata_port_operations.
294 * Inherited from caller.
296 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
298 if (ap->ops->sff_set_devctl)
299 ap->ops->sff_set_devctl(ap, ctl);
301 iowrite8(ctl, ap->ioaddr.ctl_addr);
305 * ata_sff_dev_select - Select device 0/1 on ATA bus
306 * @ap: ATA channel to manipulate
307 * @device: ATA device (numbered from zero) to select
309 * Use the method defined in the ATA specification to
310 * make either device 0, or device 1, active on the
311 * ATA channel. Works with both PIO and MMIO.
313 * May be used as the dev_select() entry in ata_port_operations.
318 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
323 tmp = ATA_DEVICE_OBS;
325 tmp = ATA_DEVICE_OBS | ATA_DEV1;
327 iowrite8(tmp, ap->ioaddr.device_addr);
328 ata_sff_pause(ap); /* needed; also flushes, for mmio */
330 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
333 * ata_dev_select - Select device 0/1 on ATA bus
334 * @ap: ATA channel to manipulate
335 * @device: ATA device (numbered from zero) to select
336 * @wait: non-zero to wait for Status register BSY bit to clear
337 * @can_sleep: non-zero if context allows sleeping
339 * Use the method defined in the ATA specification to
340 * make either device 0, or device 1, active on the
343 * This is a high-level version of ata_sff_dev_select(), which
344 * additionally provides the services of inserting the proper
345 * pauses and status polling, where needed.
350 static void ata_dev_select(struct ata_port *ap, unsigned int device,
351 unsigned int wait, unsigned int can_sleep)
353 if (ata_msg_probe(ap))
354 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
360 ap->ops->sff_dev_select(ap, device);
363 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
370 * ata_sff_irq_on - Enable interrupts on a port.
371 * @ap: Port on which interrupts are enabled.
373 * Enable interrupts on a legacy IDE device using MMIO or PIO,
374 * wait for idle, clear any pending interrupts.
376 * Note: may NOT be used as the sff_irq_on() entry in
377 * ata_port_operations.
380 * Inherited from caller.
382 void ata_sff_irq_on(struct ata_port *ap)
384 struct ata_ioports *ioaddr = &ap->ioaddr;
386 if (ap->ops->sff_irq_on) {
387 ap->ops->sff_irq_on(ap);
391 ap->ctl &= ~ATA_NIEN;
392 ap->last_ctl = ap->ctl;
394 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
395 ata_sff_set_devctl(ap, ap->ctl);
398 if (ap->ops->sff_irq_clear)
399 ap->ops->sff_irq_clear(ap);
401 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
404 * ata_sff_tf_load - send taskfile registers to host controller
405 * @ap: Port to which output is sent
406 * @tf: ATA taskfile register set
408 * Outputs ATA taskfile to standard ATA host controller.
411 * Inherited from caller.
413 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
415 struct ata_ioports *ioaddr = &ap->ioaddr;
416 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
418 if (tf->ctl != ap->last_ctl) {
419 if (ioaddr->ctl_addr)
420 iowrite8(tf->ctl, ioaddr->ctl_addr);
421 ap->last_ctl = tf->ctl;
425 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
426 WARN_ON_ONCE(!ioaddr->ctl_addr);
427 iowrite8(tf->hob_feature, ioaddr->feature_addr);
428 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
429 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
430 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
431 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
432 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
441 iowrite8(tf->feature, ioaddr->feature_addr);
442 iowrite8(tf->nsect, ioaddr->nsect_addr);
443 iowrite8(tf->lbal, ioaddr->lbal_addr);
444 iowrite8(tf->lbam, ioaddr->lbam_addr);
445 iowrite8(tf->lbah, ioaddr->lbah_addr);
446 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
454 if (tf->flags & ATA_TFLAG_DEVICE) {
455 iowrite8(tf->device, ioaddr->device_addr);
456 VPRINTK("device 0x%X\n", tf->device);
461 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
464 * ata_sff_tf_read - input device's ATA taskfile shadow registers
465 * @ap: Port from which input is read
466 * @tf: ATA taskfile register set for storing input
468 * Reads ATA taskfile registers for currently-selected device
469 * into @tf. Assumes the device has a fully SFF compliant task file
470 * layout and behaviour. If you device does not (eg has a different
471 * status method) then you will need to provide a replacement tf_read
474 * Inherited from caller.
476 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
478 struct ata_ioports *ioaddr = &ap->ioaddr;
480 tf->command = ata_sff_check_status(ap);
481 tf->feature = ioread8(ioaddr->error_addr);
482 tf->nsect = ioread8(ioaddr->nsect_addr);
483 tf->lbal = ioread8(ioaddr->lbal_addr);
484 tf->lbam = ioread8(ioaddr->lbam_addr);
485 tf->lbah = ioread8(ioaddr->lbah_addr);
486 tf->device = ioread8(ioaddr->device_addr);
488 if (tf->flags & ATA_TFLAG_LBA48) {
489 if (likely(ioaddr->ctl_addr)) {
490 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
491 tf->hob_feature = ioread8(ioaddr->error_addr);
492 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
493 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
494 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
495 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
496 iowrite8(tf->ctl, ioaddr->ctl_addr);
497 ap->last_ctl = tf->ctl;
502 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
505 * ata_sff_exec_command - issue ATA command to host controller
506 * @ap: port to which command is being issued
507 * @tf: ATA taskfile register set
509 * Issues ATA command, with proper synchronization with interrupt
510 * handler / other threads.
513 * spin_lock_irqsave(host lock)
515 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
517 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
519 iowrite8(tf->command, ap->ioaddr.command_addr);
522 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
525 * ata_tf_to_host - issue ATA taskfile to host controller
526 * @ap: port to which command is being issued
527 * @tf: ATA taskfile register set
529 * Issues ATA taskfile register set to ATA host controller,
530 * with proper synchronization with interrupt handler and
534 * spin_lock_irqsave(host lock)
536 static inline void ata_tf_to_host(struct ata_port *ap,
537 const struct ata_taskfile *tf)
539 ap->ops->sff_tf_load(ap, tf);
540 ap->ops->sff_exec_command(ap, tf);
544 * ata_sff_data_xfer - Transfer data by PIO
545 * @qc: queued command
547 * @buflen: buffer length
550 * Transfer data from/to the device data register by PIO.
553 * Inherited from caller.
558 unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf,
559 unsigned int buflen, int rw)
561 struct ata_port *ap = qc->dev->link->ap;
562 void __iomem *data_addr = ap->ioaddr.data_addr;
563 unsigned int words = buflen >> 1;
565 /* Transfer multiple of 2 bytes */
567 ioread16_rep(data_addr, buf, words);
569 iowrite16_rep(data_addr, buf, words);
571 /* Transfer trailing byte, if any. */
572 if (unlikely(buflen & 0x01)) {
573 unsigned char pad[2] = { };
575 /* Point buf to the tail of buffer */
579 * Use io*16_rep() accessors here as well to avoid pointlessly
580 * swapping bytes to and from on the big endian machines...
583 ioread16_rep(data_addr, pad, 1);
587 iowrite16_rep(data_addr, pad, 1);
594 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
597 * ata_sff_data_xfer32 - Transfer data by PIO
598 * @qc: queued command
600 * @buflen: buffer length
603 * Transfer data from/to the device data register by PIO using 32bit
607 * Inherited from caller.
613 unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
614 unsigned int buflen, int rw)
616 struct ata_device *dev = qc->dev;
617 struct ata_port *ap = dev->link->ap;
618 void __iomem *data_addr = ap->ioaddr.data_addr;
619 unsigned int words = buflen >> 2;
620 int slop = buflen & 3;
622 if (!(ap->pflags & ATA_PFLAG_PIO32))
623 return ata_sff_data_xfer(qc, buf, buflen, rw);
625 /* Transfer multiple of 4 bytes */
627 ioread32_rep(data_addr, buf, words);
629 iowrite32_rep(data_addr, buf, words);
631 /* Transfer trailing bytes, if any */
632 if (unlikely(slop)) {
633 unsigned char pad[4] = { };
635 /* Point buf to the tail of buffer */
636 buf += buflen - slop;
639 * Use io*_rep() accessors here as well to avoid pointlessly
640 * swapping bytes to and from on the big endian machines...
644 ioread16_rep(data_addr, pad, 1);
646 ioread32_rep(data_addr, pad, 1);
647 memcpy(buf, pad, slop);
649 memcpy(pad, buf, slop);
651 iowrite16_rep(data_addr, pad, 1);
653 iowrite32_rep(data_addr, pad, 1);
656 return (buflen + 1) & ~1;
658 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
660 static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
661 unsigned int offset, size_t xfer_size)
663 bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
666 buf = kmap_atomic(page);
667 qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
670 if (!do_write && !PageSlab(page))
671 flush_dcache_page(page);
675 * ata_sff_data_xfer_noirq - Transfer data by PIO
676 * @qc: queued command
678 * @buflen: buffer length
681 * Transfer data from/to the device data register by PIO. Do the
682 * transfer with interrupts disabled.
685 * Inherited from caller.
690 unsigned int ata_sff_data_xfer_noirq(struct ata_queued_cmd *qc, unsigned char *buf,
691 unsigned int buflen, int rw)
694 unsigned int consumed;
696 local_irq_save(flags);
697 consumed = ata_sff_data_xfer32(qc, buf, buflen, rw);
698 local_irq_restore(flags);
702 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
705 * ata_pio_sector - Transfer a sector of data.
706 * @qc: Command on going
708 * Transfer qc->sect_size bytes of data from/to the ATA device.
711 * Inherited from caller.
713 static void ata_pio_sector(struct ata_queued_cmd *qc)
715 struct ata_port *ap = qc->ap;
720 qc->curbytes = qc->nbytes;
723 if (qc->curbytes == qc->nbytes - qc->sect_size)
724 ap->hsm_task_state = HSM_ST_LAST;
726 page = sg_page(qc->cursg);
727 offset = qc->cursg->offset + qc->cursg_ofs;
729 /* get the current page and offset */
730 page = nth_page(page, (offset >> PAGE_SHIFT));
733 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
736 * Split the transfer when it splits a page boundary. Note that the
737 * split still has to be dword aligned like all ATA data transfers.
739 WARN_ON_ONCE(offset % 4);
740 if (offset + qc->sect_size > PAGE_SIZE) {
741 unsigned int split_len = PAGE_SIZE - offset;
743 ata_pio_xfer(qc, page, offset, split_len);
744 ata_pio_xfer(qc, nth_page(page, 1), 0,
745 qc->sect_size - split_len);
747 ata_pio_xfer(qc, page, offset, qc->sect_size);
750 qc->curbytes += qc->sect_size;
751 qc->cursg_ofs += qc->sect_size;
753 if (qc->cursg_ofs == qc->cursg->length) {
754 qc->cursg = sg_next(qc->cursg);
756 ap->hsm_task_state = HSM_ST_LAST;
762 * ata_pio_sectors - Transfer one or many sectors.
763 * @qc: Command on going
765 * Transfer one or many sectors of data from/to the
766 * ATA device for the DRQ request.
769 * Inherited from caller.
771 static void ata_pio_sectors(struct ata_queued_cmd *qc)
773 if (is_multi_taskfile(&qc->tf)) {
774 /* READ/WRITE MULTIPLE */
777 WARN_ON_ONCE(qc->dev->multi_count == 0);
779 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
780 qc->dev->multi_count);
786 ata_sff_sync(qc->ap); /* flush */
790 * atapi_send_cdb - Write CDB bytes to hardware
791 * @ap: Port to which ATAPI device is attached.
792 * @qc: Taskfile currently active
794 * When device has indicated its readiness to accept
795 * a CDB, this function is called. Send the CDB.
800 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
803 DPRINTK("send cdb\n");
804 WARN_ON_ONCE(qc->dev->cdb_len < 12);
806 ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
808 /* FIXME: If the CDB is for DMA do we need to do the transition delay
809 or is bmdma_start guaranteed to do it ? */
810 switch (qc->tf.protocol) {
812 ap->hsm_task_state = HSM_ST;
814 case ATAPI_PROT_NODATA:
815 ap->hsm_task_state = HSM_ST_LAST;
817 #ifdef CONFIG_ATA_BMDMA
819 ap->hsm_task_state = HSM_ST_LAST;
821 ap->ops->bmdma_start(qc);
823 #endif /* CONFIG_ATA_BMDMA */
830 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
831 * @qc: Command on going
832 * @bytes: number of bytes
834 * Transfer Transfer data from/to the ATAPI device.
837 * Inherited from caller.
840 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
842 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
843 struct ata_port *ap = qc->ap;
844 struct ata_device *dev = qc->dev;
845 struct ata_eh_info *ehi = &dev->link->eh_info;
846 struct scatterlist *sg;
849 unsigned int offset, count, consumed;
854 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
855 "buf=%u cur=%u bytes=%u",
856 qc->nbytes, qc->curbytes, bytes);
861 offset = sg->offset + qc->cursg_ofs;
863 /* get the current page and offset */
864 page = nth_page(page, (offset >> PAGE_SHIFT));
867 /* don't overrun current sg */
868 count = min(sg->length - qc->cursg_ofs, bytes);
870 /* don't cross page boundaries */
871 count = min(count, (unsigned int)PAGE_SIZE - offset);
873 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
875 /* do the actual data transfer */
876 buf = kmap_atomic(page);
877 consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw);
880 bytes -= min(bytes, consumed);
881 qc->curbytes += count;
882 qc->cursg_ofs += count;
884 if (qc->cursg_ofs == sg->length) {
885 qc->cursg = sg_next(qc->cursg);
890 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
891 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
892 * check correctly as it doesn't know if it is the last request being
893 * made. Somebody should implement a proper sanity check.
901 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
902 * @qc: Command on going
904 * Transfer Transfer data from/to the ATAPI device.
907 * Inherited from caller.
909 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
911 struct ata_port *ap = qc->ap;
912 struct ata_device *dev = qc->dev;
913 struct ata_eh_info *ehi = &dev->link->eh_info;
914 unsigned int ireason, bc_lo, bc_hi, bytes;
915 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
917 /* Abuse qc->result_tf for temp storage of intermediate TF
918 * here to save some kernel stack usage.
919 * For normal completion, qc->result_tf is not relevant. For
920 * error, qc->result_tf is later overwritten by ata_qc_complete().
921 * So, the correctness of qc->result_tf is not affected.
923 ap->ops->sff_tf_read(ap, &qc->result_tf);
924 ireason = qc->result_tf.nsect;
925 bc_lo = qc->result_tf.lbam;
926 bc_hi = qc->result_tf.lbah;
927 bytes = (bc_hi << 8) | bc_lo;
929 /* shall be cleared to zero, indicating xfer of data */
930 if (unlikely(ireason & ATAPI_COD))
933 /* make sure transfer direction matches expected */
934 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
935 if (unlikely(do_write != i_write))
938 if (unlikely(!bytes))
941 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
943 if (unlikely(__atapi_pio_bytes(qc, bytes)))
945 ata_sff_sync(ap); /* flush */
950 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
953 qc->err_mask |= AC_ERR_HSM;
954 ap->hsm_task_state = HSM_ST_ERR;
958 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
959 * @ap: the target ata_port
963 * 1 if ok in workqueue, 0 otherwise.
965 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
966 struct ata_queued_cmd *qc)
968 if (qc->tf.flags & ATA_TFLAG_POLLING)
971 if (ap->hsm_task_state == HSM_ST_FIRST) {
972 if (qc->tf.protocol == ATA_PROT_PIO &&
973 (qc->tf.flags & ATA_TFLAG_WRITE))
976 if (ata_is_atapi(qc->tf.protocol) &&
977 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
985 * ata_hsm_qc_complete - finish a qc running on standard HSM
986 * @qc: Command to complete
987 * @in_wq: 1 if called from workqueue, 0 otherwise
989 * Finish @qc which is running on standard HSM.
992 * If @in_wq is zero, spin_lock_irqsave(host lock).
993 * Otherwise, none on entry and grabs host lock.
995 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
997 struct ata_port *ap = qc->ap;
999 if (ap->ops->error_handler) {
1001 /* EH might have kicked in while host lock is
1004 qc = ata_qc_from_tag(ap, qc->tag);
1006 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1008 ata_qc_complete(qc);
1010 ata_port_freeze(ap);
1013 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1014 ata_qc_complete(qc);
1016 ata_port_freeze(ap);
1021 ata_qc_complete(qc);
1023 ata_qc_complete(qc);
1028 * ata_sff_hsm_move - move the HSM to the next state.
1029 * @ap: the target ata_port
1031 * @status: current device status
1032 * @in_wq: 1 if called from workqueue, 0 otherwise
1035 * 1 when poll next status needed, 0 otherwise.
1037 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1038 u8 status, int in_wq)
1040 struct ata_link *link = qc->dev->link;
1041 struct ata_eh_info *ehi = &link->eh_info;
1044 lockdep_assert_held(ap->lock);
1046 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1048 /* Make sure ata_sff_qc_issue() does not throw things
1049 * like DMA polling into the workqueue. Notice that
1050 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1052 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1055 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1056 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1058 switch (ap->hsm_task_state) {
1060 /* Send first data block or PACKET CDB */
1062 /* If polling, we will stay in the work queue after
1063 * sending the data. Otherwise, interrupt handler
1064 * takes over after sending the data.
1066 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1068 /* check device status */
1069 if (unlikely((status & ATA_DRQ) == 0)) {
1070 /* handle BSY=0, DRQ=0 as error */
1071 if (likely(status & (ATA_ERR | ATA_DF)))
1072 /* device stops HSM for abort/error */
1073 qc->err_mask |= AC_ERR_DEV;
1075 /* HSM violation. Let EH handle this */
1076 ata_ehi_push_desc(ehi,
1077 "ST_FIRST: !(DRQ|ERR|DF)");
1078 qc->err_mask |= AC_ERR_HSM;
1081 ap->hsm_task_state = HSM_ST_ERR;
1085 /* Device should not ask for data transfer (DRQ=1)
1086 * when it finds something wrong.
1087 * We ignore DRQ here and stop the HSM by
1088 * changing hsm_task_state to HSM_ST_ERR and
1089 * let the EH abort the command or reset the device.
1091 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1092 /* Some ATAPI tape drives forget to clear the ERR bit
1093 * when doing the next command (mostly request sense).
1094 * We ignore ERR here to workaround and proceed sending
1097 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1098 ata_ehi_push_desc(ehi, "ST_FIRST: "
1099 "DRQ=1 with device error, "
1100 "dev_stat 0x%X", status);
1101 qc->err_mask |= AC_ERR_HSM;
1102 ap->hsm_task_state = HSM_ST_ERR;
1107 if (qc->tf.protocol == ATA_PROT_PIO) {
1108 /* PIO data out protocol.
1109 * send first data block.
1112 /* ata_pio_sectors() might change the state
1113 * to HSM_ST_LAST. so, the state is changed here
1114 * before ata_pio_sectors().
1116 ap->hsm_task_state = HSM_ST;
1117 ata_pio_sectors(qc);
1120 atapi_send_cdb(ap, qc);
1122 /* if polling, ata_sff_pio_task() handles the rest.
1123 * otherwise, interrupt handler takes over from here.
1128 /* complete command or read/write the data register */
1129 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1130 /* ATAPI PIO protocol */
1131 if ((status & ATA_DRQ) == 0) {
1132 /* No more data to transfer or device error.
1133 * Device error will be tagged in HSM_ST_LAST.
1135 ap->hsm_task_state = HSM_ST_LAST;
1139 /* Device should not ask for data transfer (DRQ=1)
1140 * when it finds something wrong.
1141 * We ignore DRQ here and stop the HSM by
1142 * changing hsm_task_state to HSM_ST_ERR and
1143 * let the EH abort the command or reset the device.
1145 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1146 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1147 "DRQ=1 with device error, "
1148 "dev_stat 0x%X", status);
1149 qc->err_mask |= AC_ERR_HSM;
1150 ap->hsm_task_state = HSM_ST_ERR;
1154 atapi_pio_bytes(qc);
1156 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1157 /* bad ireason reported by device */
1161 /* ATA PIO protocol */
1162 if (unlikely((status & ATA_DRQ) == 0)) {
1163 /* handle BSY=0, DRQ=0 as error */
1164 if (likely(status & (ATA_ERR | ATA_DF))) {
1165 /* device stops HSM for abort/error */
1166 qc->err_mask |= AC_ERR_DEV;
1168 /* If diagnostic failed and this is
1169 * IDENTIFY, it's likely a phantom
1170 * device. Mark hint.
1172 if (qc->dev->horkage &
1173 ATA_HORKAGE_DIAGNOSTIC)
1177 /* HSM violation. Let EH handle this.
1178 * Phantom devices also trigger this
1179 * condition. Mark hint.
1181 ata_ehi_push_desc(ehi, "ST-ATA: "
1182 "DRQ=0 without device error, "
1183 "dev_stat 0x%X", status);
1184 qc->err_mask |= AC_ERR_HSM |
1188 ap->hsm_task_state = HSM_ST_ERR;
1192 /* For PIO reads, some devices may ask for
1193 * data transfer (DRQ=1) alone with ERR=1.
1194 * We respect DRQ here and transfer one
1195 * block of junk data before changing the
1196 * hsm_task_state to HSM_ST_ERR.
1198 * For PIO writes, ERR=1 DRQ=1 doesn't make
1199 * sense since the data block has been
1200 * transferred to the device.
1202 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1203 /* data might be corrputed */
1204 qc->err_mask |= AC_ERR_DEV;
1206 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1207 ata_pio_sectors(qc);
1208 status = ata_wait_idle(ap);
1211 if (status & (ATA_BUSY | ATA_DRQ)) {
1212 ata_ehi_push_desc(ehi, "ST-ATA: "
1213 "BUSY|DRQ persists on ERR|DF, "
1214 "dev_stat 0x%X", status);
1215 qc->err_mask |= AC_ERR_HSM;
1218 /* There are oddball controllers with
1219 * status register stuck at 0x7f and
1220 * lbal/m/h at zero which makes it
1221 * pass all other presence detection
1222 * mechanisms we have. Set NODEV_HINT
1223 * for it. Kernel bz#7241.
1226 qc->err_mask |= AC_ERR_NODEV_HINT;
1228 /* ata_pio_sectors() might change the
1229 * state to HSM_ST_LAST. so, the state
1230 * is changed after ata_pio_sectors().
1232 ap->hsm_task_state = HSM_ST_ERR;
1236 ata_pio_sectors(qc);
1238 if (ap->hsm_task_state == HSM_ST_LAST &&
1239 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1241 status = ata_wait_idle(ap);
1250 if (unlikely(!ata_ok(status))) {
1251 qc->err_mask |= __ac_err_mask(status);
1252 ap->hsm_task_state = HSM_ST_ERR;
1256 /* no more data to transfer */
1257 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1258 ap->print_id, qc->dev->devno, status);
1260 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1262 ap->hsm_task_state = HSM_ST_IDLE;
1264 /* complete taskfile transaction */
1265 ata_hsm_qc_complete(qc, in_wq);
1271 ap->hsm_task_state = HSM_ST_IDLE;
1273 /* complete taskfile transaction */
1274 ata_hsm_qc_complete(qc, in_wq);
1280 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1281 ap->print_id, ap->hsm_task_state);
1286 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1288 void ata_sff_queue_work(struct work_struct *work)
1290 queue_work(ata_sff_wq, work);
1292 EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1294 void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1296 queue_delayed_work(ata_sff_wq, dwork, delay);
1298 EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1300 void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1302 struct ata_port *ap = link->ap;
1304 WARN_ON((ap->sff_pio_task_link != NULL) &&
1305 (ap->sff_pio_task_link != link));
1306 ap->sff_pio_task_link = link;
1308 /* may fail if ata_sff_flush_pio_task() in progress */
1309 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1311 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1313 void ata_sff_flush_pio_task(struct ata_port *ap)
1317 cancel_delayed_work_sync(&ap->sff_pio_task);
1320 * We wanna reset the HSM state to IDLE. If we do so without
1321 * grabbing the port lock, critical sections protected by it which
1322 * expect the HSM state to stay stable may get surprised. For
1323 * example, we may set IDLE in between the time
1324 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1325 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1327 spin_lock_irq(ap->lock);
1328 ap->hsm_task_state = HSM_ST_IDLE;
1329 spin_unlock_irq(ap->lock);
1331 ap->sff_pio_task_link = NULL;
1333 if (ata_msg_ctl(ap))
1334 ata_port_dbg(ap, "%s: EXIT\n", __func__);
1337 static void ata_sff_pio_task(struct work_struct *work)
1339 struct ata_port *ap =
1340 container_of(work, struct ata_port, sff_pio_task.work);
1341 struct ata_link *link = ap->sff_pio_task_link;
1342 struct ata_queued_cmd *qc;
1346 spin_lock_irq(ap->lock);
1348 BUG_ON(ap->sff_pio_task_link == NULL);
1349 /* qc can be NULL if timeout occurred */
1350 qc = ata_qc_from_tag(ap, link->active_tag);
1352 ap->sff_pio_task_link = NULL;
1357 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1360 * This is purely heuristic. This is a fast path.
1361 * Sometimes when we enter, BSY will be cleared in
1362 * a chk-status or two. If not, the drive is probably seeking
1363 * or something. Snooze for a couple msecs, then
1364 * chk-status again. If still busy, queue delayed work.
1366 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1367 if (status & ATA_BUSY) {
1368 spin_unlock_irq(ap->lock);
1370 spin_lock_irq(ap->lock);
1372 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1373 if (status & ATA_BUSY) {
1374 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1380 * hsm_move() may trigger another command to be processed.
1381 * clean the link beforehand.
1383 ap->sff_pio_task_link = NULL;
1385 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1387 /* another command or interrupt handler
1388 * may be running at this point.
1393 spin_unlock_irq(ap->lock);
1397 * ata_sff_qc_issue - issue taskfile to a SFF controller
1398 * @qc: command to issue to device
1400 * This function issues a PIO or NODATA command to a SFF
1404 * spin_lock_irqsave(host lock)
1407 * Zero on success, AC_ERR_* mask on failure
1409 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1411 struct ata_port *ap = qc->ap;
1412 struct ata_link *link = qc->dev->link;
1414 /* Use polling pio if the LLD doesn't handle
1415 * interrupt driven pio and atapi CDB interrupt.
1417 if (ap->flags & ATA_FLAG_PIO_POLLING)
1418 qc->tf.flags |= ATA_TFLAG_POLLING;
1420 /* select the device */
1421 ata_dev_select(ap, qc->dev->devno, 1, 0);
1423 /* start the command */
1424 switch (qc->tf.protocol) {
1425 case ATA_PROT_NODATA:
1426 if (qc->tf.flags & ATA_TFLAG_POLLING)
1427 ata_qc_set_polling(qc);
1429 ata_tf_to_host(ap, &qc->tf);
1430 ap->hsm_task_state = HSM_ST_LAST;
1432 if (qc->tf.flags & ATA_TFLAG_POLLING)
1433 ata_sff_queue_pio_task(link, 0);
1438 if (qc->tf.flags & ATA_TFLAG_POLLING)
1439 ata_qc_set_polling(qc);
1441 ata_tf_to_host(ap, &qc->tf);
1443 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1444 /* PIO data out protocol */
1445 ap->hsm_task_state = HSM_ST_FIRST;
1446 ata_sff_queue_pio_task(link, 0);
1448 /* always send first data block using the
1449 * ata_sff_pio_task() codepath.
1452 /* PIO data in protocol */
1453 ap->hsm_task_state = HSM_ST;
1455 if (qc->tf.flags & ATA_TFLAG_POLLING)
1456 ata_sff_queue_pio_task(link, 0);
1458 /* if polling, ata_sff_pio_task() handles the
1459 * rest. otherwise, interrupt handler takes
1466 case ATAPI_PROT_PIO:
1467 case ATAPI_PROT_NODATA:
1468 if (qc->tf.flags & ATA_TFLAG_POLLING)
1469 ata_qc_set_polling(qc);
1471 ata_tf_to_host(ap, &qc->tf);
1473 ap->hsm_task_state = HSM_ST_FIRST;
1475 /* send cdb by polling if no cdb interrupt */
1476 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1477 (qc->tf.flags & ATA_TFLAG_POLLING))
1478 ata_sff_queue_pio_task(link, 0);
1482 return AC_ERR_SYSTEM;
1487 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1490 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1491 * @qc: qc to fill result TF for
1493 * @qc is finished and result TF needs to be filled. Fill it
1494 * using ->sff_tf_read.
1497 * spin_lock_irqsave(host lock)
1500 * true indicating that result TF is successfully filled.
1502 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1504 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1507 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1509 static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1511 ap->stats.idle_irq++;
1514 if ((ap->stats.idle_irq % 1000) == 0) {
1515 ap->ops->sff_check_status(ap);
1516 if (ap->ops->sff_irq_clear)
1517 ap->ops->sff_irq_clear(ap);
1518 ata_port_warn(ap, "irq trap\n");
1522 return 0; /* irq not handled */
1525 static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1526 struct ata_queued_cmd *qc,
1531 VPRINTK("ata%u: protocol %d task_state %d\n",
1532 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1534 /* Check whether we are expecting interrupt in this state */
1535 switch (ap->hsm_task_state) {
1537 /* Some pre-ATAPI-4 devices assert INTRQ
1538 * at this state when ready to receive CDB.
1541 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1542 * The flag was turned on only for atapi devices. No
1543 * need to check ata_is_atapi(qc->tf.protocol) again.
1545 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1546 return ata_sff_idle_irq(ap);
1549 return ata_sff_idle_irq(ap);
1554 /* check main status, clearing INTRQ if needed */
1555 status = ata_sff_irq_status(ap);
1556 if (status & ATA_BUSY) {
1558 /* BMDMA engine is already stopped, we're screwed */
1559 qc->err_mask |= AC_ERR_HSM;
1560 ap->hsm_task_state = HSM_ST_ERR;
1562 return ata_sff_idle_irq(ap);
1565 /* clear irq events */
1566 if (ap->ops->sff_irq_clear)
1567 ap->ops->sff_irq_clear(ap);
1569 ata_sff_hsm_move(ap, qc, status, 0);
1571 return 1; /* irq handled */
1575 * ata_sff_port_intr - Handle SFF port interrupt
1576 * @ap: Port on which interrupt arrived (possibly...)
1577 * @qc: Taskfile currently active in engine
1579 * Handle port interrupt for given queued command.
1582 * spin_lock_irqsave(host lock)
1585 * One if interrupt was handled, zero if not (shared irq).
1587 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1589 return __ata_sff_port_intr(ap, qc, false);
1591 EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1593 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1594 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1596 struct ata_host *host = dev_instance;
1597 bool retried = false;
1599 unsigned int handled, idle, polling;
1600 unsigned long flags;
1602 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1603 spin_lock_irqsave(&host->lock, flags);
1606 handled = idle = polling = 0;
1607 for (i = 0; i < host->n_ports; i++) {
1608 struct ata_port *ap = host->ports[i];
1609 struct ata_queued_cmd *qc;
1611 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1613 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1614 handled |= port_intr(ap, qc);
1622 * If no port was expecting IRQ but the controller is actually
1623 * asserting IRQ line, nobody cared will ensue. Check IRQ
1624 * pending status if available and clear spurious IRQ.
1626 if (!handled && !retried) {
1629 for (i = 0; i < host->n_ports; i++) {
1630 struct ata_port *ap = host->ports[i];
1632 if (polling & (1 << i))
1635 if (!ap->ops->sff_irq_check ||
1636 !ap->ops->sff_irq_check(ap))
1639 if (idle & (1 << i)) {
1640 ap->ops->sff_check_status(ap);
1641 if (ap->ops->sff_irq_clear)
1642 ap->ops->sff_irq_clear(ap);
1644 /* clear INTRQ and check if BUSY cleared */
1645 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1648 * With command in flight, we can't do
1649 * sff_irq_clear() w/o racing with completion.
1660 spin_unlock_irqrestore(&host->lock, flags);
1662 return IRQ_RETVAL(handled);
1666 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1667 * @irq: irq line (unused)
1668 * @dev_instance: pointer to our ata_host information structure
1670 * Default interrupt handler for PCI IDE devices. Calls
1671 * ata_sff_port_intr() for each port that is not disabled.
1674 * Obtains host lock during operation.
1677 * IRQ_NONE or IRQ_HANDLED.
1679 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1681 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1683 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1686 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1687 * @ap: port that appears to have timed out
1689 * Called from the libata error handlers when the core code suspects
1690 * an interrupt has been lost. If it has complete anything we can and
1691 * then return. Interface must support altstatus for this faster
1692 * recovery to occur.
1695 * Caller holds host lock
1698 void ata_sff_lost_interrupt(struct ata_port *ap)
1701 struct ata_queued_cmd *qc;
1703 /* Only one outstanding command per SFF channel */
1704 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1705 /* We cannot lose an interrupt on a non-existent or polled command */
1706 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1708 /* See if the controller thinks it is still busy - if so the command
1709 isn't a lost IRQ but is still in progress */
1710 status = ata_sff_altstatus(ap);
1711 if (status & ATA_BUSY)
1714 /* There was a command running, we are no longer busy and we have
1716 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
1718 /* Run the host interrupt logic as if the interrupt had not been
1720 ata_sff_port_intr(ap, qc);
1722 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1725 * ata_sff_freeze - Freeze SFF controller port
1726 * @ap: port to freeze
1728 * Freeze SFF controller port.
1731 * Inherited from caller.
1733 void ata_sff_freeze(struct ata_port *ap)
1735 ap->ctl |= ATA_NIEN;
1736 ap->last_ctl = ap->ctl;
1738 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1739 ata_sff_set_devctl(ap, ap->ctl);
1741 /* Under certain circumstances, some controllers raise IRQ on
1742 * ATA_NIEN manipulation. Also, many controllers fail to mask
1743 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1745 ap->ops->sff_check_status(ap);
1747 if (ap->ops->sff_irq_clear)
1748 ap->ops->sff_irq_clear(ap);
1750 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1753 * ata_sff_thaw - Thaw SFF controller port
1756 * Thaw SFF controller port.
1759 * Inherited from caller.
1761 void ata_sff_thaw(struct ata_port *ap)
1763 /* clear & re-enable interrupts */
1764 ap->ops->sff_check_status(ap);
1765 if (ap->ops->sff_irq_clear)
1766 ap->ops->sff_irq_clear(ap);
1769 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1772 * ata_sff_prereset - prepare SFF link for reset
1773 * @link: SFF link to be reset
1774 * @deadline: deadline jiffies for the operation
1776 * SFF link @link is about to be reset. Initialize it. It first
1777 * calls ata_std_prereset() and wait for !BSY if the port is
1781 * Kernel thread context (may sleep)
1784 * 0 on success, -errno otherwise.
1786 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1788 struct ata_eh_context *ehc = &link->eh_context;
1791 rc = ata_std_prereset(link, deadline);
1795 /* if we're about to do hardreset, nothing more to do */
1796 if (ehc->i.action & ATA_EH_HARDRESET)
1799 /* wait for !BSY if we don't know that no device is attached */
1800 if (!ata_link_offline(link)) {
1801 rc = ata_sff_wait_ready(link, deadline);
1802 if (rc && rc != -ENODEV) {
1804 "device not ready (errno=%d), forcing hardreset\n",
1806 ehc->i.action |= ATA_EH_HARDRESET;
1812 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1815 * ata_devchk - PATA device presence detection
1816 * @ap: ATA channel to examine
1817 * @device: Device to examine (starting at zero)
1819 * This technique was originally described in
1820 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1821 * later found its way into the ATA/ATAPI spec.
1823 * Write a pattern to the ATA shadow registers,
1824 * and if a device is present, it will respond by
1825 * correctly storing and echoing back the
1826 * ATA shadow register contents.
1831 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1833 struct ata_ioports *ioaddr = &ap->ioaddr;
1836 ap->ops->sff_dev_select(ap, device);
1838 iowrite8(0x55, ioaddr->nsect_addr);
1839 iowrite8(0xaa, ioaddr->lbal_addr);
1841 iowrite8(0xaa, ioaddr->nsect_addr);
1842 iowrite8(0x55, ioaddr->lbal_addr);
1844 iowrite8(0x55, ioaddr->nsect_addr);
1845 iowrite8(0xaa, ioaddr->lbal_addr);
1847 nsect = ioread8(ioaddr->nsect_addr);
1848 lbal = ioread8(ioaddr->lbal_addr);
1850 if ((nsect == 0x55) && (lbal == 0xaa))
1851 return 1; /* we found a device */
1853 return 0; /* nothing found */
1857 * ata_sff_dev_classify - Parse returned ATA device signature
1858 * @dev: ATA device to classify (starting at zero)
1859 * @present: device seems present
1860 * @r_err: Value of error register on completion
1862 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1863 * an ATA/ATAPI-defined set of values is placed in the ATA
1864 * shadow registers, indicating the results of device detection
1867 * Select the ATA device, and read the values from the ATA shadow
1868 * registers. Then parse according to the Error register value,
1869 * and the spec-defined values examined by ata_dev_classify().
1875 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1877 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1880 struct ata_port *ap = dev->link->ap;
1881 struct ata_taskfile tf;
1885 ap->ops->sff_dev_select(ap, dev->devno);
1887 memset(&tf, 0, sizeof(tf));
1889 ap->ops->sff_tf_read(ap, &tf);
1894 /* see if device passed diags: continue and warn later */
1896 /* diagnostic fail : do nothing _YET_ */
1897 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1900 else if ((dev->devno == 0) && (err == 0x81))
1903 return ATA_DEV_NONE;
1905 /* determine if device is ATA or ATAPI */
1906 class = ata_dev_classify(&tf);
1908 if (class == ATA_DEV_UNKNOWN) {
1909 /* If the device failed diagnostic, it's likely to
1910 * have reported incorrect device signature too.
1911 * Assume ATA device if the device seems present but
1912 * device signature is invalid with diagnostic
1915 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1916 class = ATA_DEV_ATA;
1918 class = ATA_DEV_NONE;
1919 } else if ((class == ATA_DEV_ATA) &&
1920 (ap->ops->sff_check_status(ap) == 0))
1921 class = ATA_DEV_NONE;
1925 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1928 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1929 * @link: SFF link which is just reset
1930 * @devmask: mask of present devices
1931 * @deadline: deadline jiffies for the operation
1933 * Wait devices attached to SFF @link to become ready after
1934 * reset. It contains preceding 150ms wait to avoid accessing TF
1935 * status register too early.
1938 * Kernel thread context (may sleep).
1941 * 0 on success, -ENODEV if some or all of devices in @devmask
1942 * don't seem to exist. -errno on other errors.
1944 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1945 unsigned long deadline)
1947 struct ata_port *ap = link->ap;
1948 struct ata_ioports *ioaddr = &ap->ioaddr;
1949 unsigned int dev0 = devmask & (1 << 0);
1950 unsigned int dev1 = devmask & (1 << 1);
1953 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1955 /* always check readiness of the master device */
1956 rc = ata_sff_wait_ready(link, deadline);
1957 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1958 * and TF status is 0xff, bail out on it too.
1963 /* if device 1 was found in ata_devchk, wait for register
1964 * access briefly, then wait for BSY to clear.
1969 ap->ops->sff_dev_select(ap, 1);
1971 /* Wait for register access. Some ATAPI devices fail
1972 * to set nsect/lbal after reset, so don't waste too
1973 * much time on it. We're gonna wait for !BSY anyway.
1975 for (i = 0; i < 2; i++) {
1978 nsect = ioread8(ioaddr->nsect_addr);
1979 lbal = ioread8(ioaddr->lbal_addr);
1980 if ((nsect == 1) && (lbal == 1))
1982 ata_msleep(ap, 50); /* give drive a breather */
1985 rc = ata_sff_wait_ready(link, deadline);
1993 /* is all this really necessary? */
1994 ap->ops->sff_dev_select(ap, 0);
1996 ap->ops->sff_dev_select(ap, 1);
1998 ap->ops->sff_dev_select(ap, 0);
2002 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2004 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2005 unsigned long deadline)
2007 struct ata_ioports *ioaddr = &ap->ioaddr;
2009 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2011 if (ap->ioaddr.ctl_addr) {
2012 /* software reset. causes dev0 to be selected */
2013 iowrite8(ap->ctl, ioaddr->ctl_addr);
2014 udelay(20); /* FIXME: flush */
2015 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2016 udelay(20); /* FIXME: flush */
2017 iowrite8(ap->ctl, ioaddr->ctl_addr);
2018 ap->last_ctl = ap->ctl;
2021 /* wait the port to become ready */
2022 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2026 * ata_sff_softreset - reset host port via ATA SRST
2027 * @link: ATA link to reset
2028 * @classes: resulting classes of attached devices
2029 * @deadline: deadline jiffies for the operation
2031 * Reset host port using ATA SRST.
2034 * Kernel thread context (may sleep)
2037 * 0 on success, -errno otherwise.
2039 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2040 unsigned long deadline)
2042 struct ata_port *ap = link->ap;
2043 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2044 unsigned int devmask = 0;
2050 /* determine if device 0/1 are present */
2051 if (ata_devchk(ap, 0))
2052 devmask |= (1 << 0);
2053 if (slave_possible && ata_devchk(ap, 1))
2054 devmask |= (1 << 1);
2056 /* select device 0 again */
2057 ap->ops->sff_dev_select(ap, 0);
2059 /* issue bus reset */
2060 DPRINTK("about to softreset, devmask=%x\n", devmask);
2061 rc = ata_bus_softreset(ap, devmask, deadline);
2062 /* if link is occupied, -ENODEV too is an error */
2063 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2064 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
2068 /* determine by signature whether we have ATA or ATAPI devices */
2069 classes[0] = ata_sff_dev_classify(&link->device[0],
2070 devmask & (1 << 0), &err);
2071 if (slave_possible && err != 0x81)
2072 classes[1] = ata_sff_dev_classify(&link->device[1],
2073 devmask & (1 << 1), &err);
2075 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2078 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2081 * sata_sff_hardreset - reset host port via SATA phy reset
2082 * @link: link to reset
2083 * @class: resulting class of attached device
2084 * @deadline: deadline jiffies for the operation
2086 * SATA phy-reset host port using DET bits of SControl register,
2087 * wait for !BSY and classify the attached device.
2090 * Kernel thread context (may sleep)
2093 * 0 on success, -errno otherwise.
2095 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2096 unsigned long deadline)
2098 struct ata_eh_context *ehc = &link->eh_context;
2099 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2103 rc = sata_link_hardreset(link, timing, deadline, &online,
2104 ata_sff_check_ready);
2106 *class = ata_sff_dev_classify(link->device, 1, NULL);
2108 DPRINTK("EXIT, class=%u\n", *class);
2111 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2114 * ata_sff_postreset - SFF postreset callback
2115 * @link: the target SFF ata_link
2116 * @classes: classes of attached devices
2118 * This function is invoked after a successful reset. It first
2119 * calls ata_std_postreset() and performs SFF specific postreset
2123 * Kernel thread context (may sleep)
2125 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2127 struct ata_port *ap = link->ap;
2129 ata_std_postreset(link, classes);
2131 /* is double-select really necessary? */
2132 if (classes[0] != ATA_DEV_NONE)
2133 ap->ops->sff_dev_select(ap, 1);
2134 if (classes[1] != ATA_DEV_NONE)
2135 ap->ops->sff_dev_select(ap, 0);
2137 /* bail out if no device is present */
2138 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2139 DPRINTK("EXIT, no device\n");
2143 /* set up device control */
2144 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2145 ata_sff_set_devctl(ap, ap->ctl);
2146 ap->last_ctl = ap->ctl;
2149 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2152 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2155 * Drain the FIFO and device of any stuck data following a command
2156 * failing to complete. In some cases this is necessary before a
2157 * reset will recover the device.
2161 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2164 struct ata_port *ap;
2166 /* We only need to flush incoming data when a command was running */
2167 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2171 /* Drain up to 64K of data before we give up this recovery method */
2172 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2173 && count < 65536; count += 2)
2174 ioread16(ap->ioaddr.data_addr);
2176 /* Can become DEBUG later */
2178 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2181 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2184 * ata_sff_error_handler - Stock error handler for SFF controller
2185 * @ap: port to handle error for
2187 * Stock error handler for SFF controller. It can handle both
2188 * PATA and SATA controllers. Many controllers should be able to
2189 * use this EH as-is or with some added handling before and
2193 * Kernel thread context (may sleep)
2195 void ata_sff_error_handler(struct ata_port *ap)
2197 ata_reset_fn_t softreset = ap->ops->softreset;
2198 ata_reset_fn_t hardreset = ap->ops->hardreset;
2199 struct ata_queued_cmd *qc;
2200 unsigned long flags;
2202 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2203 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2206 spin_lock_irqsave(ap->lock, flags);
2209 * We *MUST* do FIFO draining before we issue a reset as
2210 * several devices helpfully clear their internal state and
2211 * will lock solid if we touch the data port post reset. Pass
2212 * qc in case anyone wants to do different PIO/DMA recovery or
2213 * has per command fixups
2215 if (ap->ops->sff_drain_fifo)
2216 ap->ops->sff_drain_fifo(qc);
2218 spin_unlock_irqrestore(ap->lock, flags);
2220 /* ignore built-in hardresets if SCR access is not available */
2221 if ((hardreset == sata_std_hardreset ||
2222 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2225 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2226 ap->ops->postreset);
2228 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2231 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2232 * @ioaddr: IO address structure to be initialized
2234 * Utility function which initializes data_addr, error_addr,
2235 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2236 * device_addr, status_addr, and command_addr to standard offsets
2237 * relative to cmd_addr.
2239 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2241 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2243 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2244 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2245 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2246 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2247 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2248 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2249 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2250 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2251 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2252 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2254 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2258 static int ata_resources_present(struct pci_dev *pdev, int port)
2262 /* Check the PCI resources for this channel are enabled */
2264 for (i = 0; i < 2; i++) {
2265 if (pci_resource_start(pdev, port + i) == 0 ||
2266 pci_resource_len(pdev, port + i) == 0)
2273 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2274 * @host: target ATA host
2276 * Acquire native PCI ATA resources for @host and initialize the
2277 * first two ports of @host accordingly. Ports marked dummy are
2278 * skipped and allocation failure makes the port dummy.
2280 * Note that native PCI resources are valid even for legacy hosts
2281 * as we fix up pdev resources array early in boot, so this
2282 * function can be used for both native and legacy SFF hosts.
2285 * Inherited from calling layer (may sleep).
2288 * 0 if at least one port is initialized, -ENODEV if no port is
2291 int ata_pci_sff_init_host(struct ata_host *host)
2293 struct device *gdev = host->dev;
2294 struct pci_dev *pdev = to_pci_dev(gdev);
2295 unsigned int mask = 0;
2298 /* request, iomap BARs and init port addresses accordingly */
2299 for (i = 0; i < 2; i++) {
2300 struct ata_port *ap = host->ports[i];
2302 void __iomem * const *iomap;
2304 if (ata_port_is_dummy(ap))
2307 /* Discard disabled ports. Some controllers show
2308 * their unused channels this way. Disabled ports are
2311 if (!ata_resources_present(pdev, i)) {
2312 ap->ops = &ata_dummy_port_ops;
2316 rc = pcim_iomap_regions(pdev, 0x3 << base,
2317 dev_driver_string(gdev));
2320 "failed to request/iomap BARs for port %d (errno=%d)\n",
2323 pcim_pin_device(pdev);
2324 ap->ops = &ata_dummy_port_ops;
2327 host->iomap = iomap = pcim_iomap_table(pdev);
2329 ap->ioaddr.cmd_addr = iomap[base];
2330 ap->ioaddr.altstatus_addr =
2331 ap->ioaddr.ctl_addr = (void __iomem *)
2332 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2333 ata_sff_std_ports(&ap->ioaddr);
2335 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2336 (unsigned long long)pci_resource_start(pdev, base),
2337 (unsigned long long)pci_resource_start(pdev, base + 1));
2343 dev_err(gdev, "no available native port\n");
2349 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2352 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2353 * @pdev: target PCI device
2354 * @ppi: array of port_info, must be enough for two ports
2355 * @r_host: out argument for the initialized ATA host
2357 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2358 * all PCI resources and initialize it accordingly in one go.
2361 * Inherited from calling layer (may sleep).
2364 * 0 on success, -errno otherwise.
2366 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2367 const struct ata_port_info * const *ppi,
2368 struct ata_host **r_host)
2370 struct ata_host *host;
2373 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2376 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2378 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2383 rc = ata_pci_sff_init_host(host);
2387 devres_remove_group(&pdev->dev, NULL);
2392 devres_release_group(&pdev->dev, NULL);
2395 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2398 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2399 * @host: target SFF ATA host
2400 * @irq_handler: irq_handler used when requesting IRQ(s)
2401 * @sht: scsi_host_template to use when registering the host
2403 * This is the counterpart of ata_host_activate() for SFF ATA
2404 * hosts. This separate helper is necessary because SFF hosts
2405 * use two separate interrupts in legacy mode.
2408 * Inherited from calling layer (may sleep).
2411 * 0 on success, -errno otherwise.
2413 int ata_pci_sff_activate_host(struct ata_host *host,
2414 irq_handler_t irq_handler,
2415 struct scsi_host_template *sht)
2417 struct device *dev = host->dev;
2418 struct pci_dev *pdev = to_pci_dev(dev);
2419 const char *drv_name = dev_driver_string(host->dev);
2420 int legacy_mode = 0, rc;
2422 rc = ata_host_start(host);
2426 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2430 * ATA spec says we should use legacy mode when one
2431 * port is in legacy mode, but disabled ports on some
2432 * PCI hosts appear as fixed legacy ports, e.g SB600/700
2433 * on which the secondary port is not wired, so
2434 * ignore ports that are marked as 'dummy' during
2437 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2438 if (!ata_port_is_dummy(host->ports[0]))
2440 if (!ata_port_is_dummy(host->ports[1]))
2442 if ((tmp8 & mask) != mask)
2446 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2449 if (!legacy_mode && pdev->irq) {
2452 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2453 IRQF_SHARED, drv_name, host);
2457 for (i = 0; i < 2; i++) {
2458 if (ata_port_is_dummy(host->ports[i]))
2460 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2462 } else if (legacy_mode) {
2463 if (!ata_port_is_dummy(host->ports[0])) {
2464 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2465 irq_handler, IRQF_SHARED,
2470 ata_port_desc(host->ports[0], "irq %d",
2471 ATA_PRIMARY_IRQ(pdev));
2474 if (!ata_port_is_dummy(host->ports[1])) {
2475 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2476 irq_handler, IRQF_SHARED,
2481 ata_port_desc(host->ports[1], "irq %d",
2482 ATA_SECONDARY_IRQ(pdev));
2486 rc = ata_host_register(host, sht);
2489 devres_remove_group(dev, NULL);
2491 devres_release_group(dev, NULL);
2495 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2497 static const struct ata_port_info *ata_sff_find_valid_pi(
2498 const struct ata_port_info * const *ppi)
2502 /* look up the first valid port_info */
2503 for (i = 0; i < 2 && ppi[i]; i++)
2504 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2510 static int ata_pci_init_one(struct pci_dev *pdev,
2511 const struct ata_port_info * const *ppi,
2512 struct scsi_host_template *sht, void *host_priv,
2513 int hflags, bool bmdma)
2515 struct device *dev = &pdev->dev;
2516 const struct ata_port_info *pi;
2517 struct ata_host *host = NULL;
2522 pi = ata_sff_find_valid_pi(ppi);
2524 dev_err(&pdev->dev, "no valid port_info specified\n");
2528 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2531 rc = pcim_enable_device(pdev);
2535 #ifdef CONFIG_ATA_BMDMA
2537 /* prepare and activate BMDMA host */
2538 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2541 /* prepare and activate SFF host */
2542 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2545 host->private_data = host_priv;
2546 host->flags |= hflags;
2548 #ifdef CONFIG_ATA_BMDMA
2550 pci_set_master(pdev);
2551 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2554 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2557 devres_remove_group(&pdev->dev, NULL);
2559 devres_release_group(&pdev->dev, NULL);
2565 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2566 * @pdev: Controller to be initialized
2567 * @ppi: array of port_info, must be enough for two ports
2568 * @sht: scsi_host_template to use when registering the host
2569 * @host_priv: host private_data
2570 * @hflag: host flags
2572 * This is a helper function which can be called from a driver's
2573 * xxx_init_one() probe function if the hardware uses traditional
2574 * IDE taskfile registers and is PIO only.
2577 * Nobody makes a single channel controller that appears solely as
2578 * the secondary legacy port on PCI.
2581 * Inherited from PCI layer (may sleep).
2584 * Zero on success, negative on errno-based value on error.
2586 int ata_pci_sff_init_one(struct pci_dev *pdev,
2587 const struct ata_port_info * const *ppi,
2588 struct scsi_host_template *sht, void *host_priv, int hflag)
2590 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2592 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2594 #endif /* CONFIG_PCI */
2600 #ifdef CONFIG_ATA_BMDMA
2602 const struct ata_port_operations ata_bmdma_port_ops = {
2603 .inherits = &ata_sff_port_ops,
2605 .error_handler = ata_bmdma_error_handler,
2606 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2608 .qc_prep = ata_bmdma_qc_prep,
2609 .qc_issue = ata_bmdma_qc_issue,
2611 .sff_irq_clear = ata_bmdma_irq_clear,
2612 .bmdma_setup = ata_bmdma_setup,
2613 .bmdma_start = ata_bmdma_start,
2614 .bmdma_stop = ata_bmdma_stop,
2615 .bmdma_status = ata_bmdma_status,
2617 .port_start = ata_bmdma_port_start,
2619 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2621 const struct ata_port_operations ata_bmdma32_port_ops = {
2622 .inherits = &ata_bmdma_port_ops,
2624 .sff_data_xfer = ata_sff_data_xfer32,
2625 .port_start = ata_bmdma_port_start32,
2627 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2630 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2631 * @qc: Metadata associated with taskfile to be transferred
2633 * Fill PCI IDE PRD (scatter-gather) table with segments
2634 * associated with the current disk command.
2637 * spin_lock_irqsave(host lock)
2640 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2642 struct ata_port *ap = qc->ap;
2643 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2644 struct scatterlist *sg;
2645 unsigned int si, pi;
2648 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2652 /* determine if physical DMA addr spans 64K boundary.
2653 * Note h/w doesn't support 64-bit, so we unconditionally
2654 * truncate dma_addr_t to u32.
2656 addr = (u32) sg_dma_address(sg);
2657 sg_len = sg_dma_len(sg);
2660 offset = addr & 0xffff;
2662 if ((offset + sg_len) > 0x10000)
2663 len = 0x10000 - offset;
2665 prd[pi].addr = cpu_to_le32(addr);
2666 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2667 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2675 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2679 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2680 * @qc: Metadata associated with taskfile to be transferred
2682 * Fill PCI IDE PRD (scatter-gather) table with segments
2683 * associated with the current disk command. Perform the fill
2684 * so that we avoid writing any length 64K records for
2685 * controllers that don't follow the spec.
2688 * spin_lock_irqsave(host lock)
2691 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2693 struct ata_port *ap = qc->ap;
2694 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2695 struct scatterlist *sg;
2696 unsigned int si, pi;
2699 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2701 u32 sg_len, len, blen;
2703 /* determine if physical DMA addr spans 64K boundary.
2704 * Note h/w doesn't support 64-bit, so we unconditionally
2705 * truncate dma_addr_t to u32.
2707 addr = (u32) sg_dma_address(sg);
2708 sg_len = sg_dma_len(sg);
2711 offset = addr & 0xffff;
2713 if ((offset + sg_len) > 0x10000)
2714 len = 0x10000 - offset;
2716 blen = len & 0xffff;
2717 prd[pi].addr = cpu_to_le32(addr);
2719 /* Some PATA chipsets like the CS5530 can't
2720 cope with 0x0000 meaning 64K as the spec
2722 prd[pi].flags_len = cpu_to_le32(0x8000);
2724 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2726 prd[pi].flags_len = cpu_to_le32(blen);
2727 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2735 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2739 * ata_bmdma_qc_prep - Prepare taskfile for submission
2740 * @qc: Metadata associated with taskfile to be prepared
2742 * Prepare ATA taskfile for submission.
2745 * spin_lock_irqsave(host lock)
2747 enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2749 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2752 ata_bmdma_fill_sg(qc);
2756 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2759 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2760 * @qc: Metadata associated with taskfile to be prepared
2762 * Prepare ATA taskfile for submission.
2765 * spin_lock_irqsave(host lock)
2767 enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2769 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2772 ata_bmdma_fill_sg_dumb(qc);
2776 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2779 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2780 * @qc: command to issue to device
2782 * This function issues a PIO, NODATA or DMA command to a
2783 * SFF/BMDMA controller. PIO and NODATA are handled by
2784 * ata_sff_qc_issue().
2787 * spin_lock_irqsave(host lock)
2790 * Zero on success, AC_ERR_* mask on failure
2792 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2794 struct ata_port *ap = qc->ap;
2795 struct ata_link *link = qc->dev->link;
2797 /* defer PIO handling to sff_qc_issue */
2798 if (!ata_is_dma(qc->tf.protocol))
2799 return ata_sff_qc_issue(qc);
2801 /* select the device */
2802 ata_dev_select(ap, qc->dev->devno, 1, 0);
2804 /* start the command */
2805 switch (qc->tf.protocol) {
2807 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2809 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2810 ap->ops->bmdma_setup(qc); /* set up bmdma */
2811 ap->ops->bmdma_start(qc); /* initiate bmdma */
2812 ap->hsm_task_state = HSM_ST_LAST;
2815 case ATAPI_PROT_DMA:
2816 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2818 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2819 ap->ops->bmdma_setup(qc); /* set up bmdma */
2820 ap->hsm_task_state = HSM_ST_FIRST;
2822 /* send cdb by polling if no cdb interrupt */
2823 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2824 ata_sff_queue_pio_task(link, 0);
2829 return AC_ERR_SYSTEM;
2834 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2837 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2838 * @ap: Port on which interrupt arrived (possibly...)
2839 * @qc: Taskfile currently active in engine
2841 * Handle port interrupt for given queued command.
2844 * spin_lock_irqsave(host lock)
2847 * One if interrupt was handled, zero if not (shared irq).
2849 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2851 struct ata_eh_info *ehi = &ap->link.eh_info;
2853 bool bmdma_stopped = false;
2854 unsigned int handled;
2856 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2857 /* check status of DMA engine */
2858 host_stat = ap->ops->bmdma_status(ap);
2859 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2861 /* if it's not our irq... */
2862 if (!(host_stat & ATA_DMA_INTR))
2863 return ata_sff_idle_irq(ap);
2865 /* before we do anything else, clear DMA-Start bit */
2866 ap->ops->bmdma_stop(qc);
2867 bmdma_stopped = true;
2869 if (unlikely(host_stat & ATA_DMA_ERR)) {
2870 /* error when transferring data to/from memory */
2871 qc->err_mask |= AC_ERR_HOST_BUS;
2872 ap->hsm_task_state = HSM_ST_ERR;
2876 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2878 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2879 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2883 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2886 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2887 * @irq: irq line (unused)
2888 * @dev_instance: pointer to our ata_host information structure
2890 * Default interrupt handler for PCI IDE devices. Calls
2891 * ata_bmdma_port_intr() for each port that is not disabled.
2894 * Obtains host lock during operation.
2897 * IRQ_NONE or IRQ_HANDLED.
2899 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2901 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2903 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2906 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2907 * @ap: port to handle error for
2909 * Stock error handler for BMDMA controller. It can handle both
2910 * PATA and SATA controllers. Most BMDMA controllers should be
2911 * able to use this EH as-is or with some added handling before
2915 * Kernel thread context (may sleep)
2917 void ata_bmdma_error_handler(struct ata_port *ap)
2919 struct ata_queued_cmd *qc;
2920 unsigned long flags;
2923 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2924 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2927 /* reset PIO HSM and stop DMA engine */
2928 spin_lock_irqsave(ap->lock, flags);
2930 if (qc && ata_is_dma(qc->tf.protocol)) {
2933 host_stat = ap->ops->bmdma_status(ap);
2935 /* BMDMA controllers indicate host bus error by
2936 * setting DMA_ERR bit and timing out. As it wasn't
2937 * really a timeout event, adjust error mask and
2938 * cancel frozen state.
2940 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2941 qc->err_mask = AC_ERR_HOST_BUS;
2945 ap->ops->bmdma_stop(qc);
2947 /* if we're gonna thaw, make sure IRQ is clear */
2949 ap->ops->sff_check_status(ap);
2950 if (ap->ops->sff_irq_clear)
2951 ap->ops->sff_irq_clear(ap);
2955 spin_unlock_irqrestore(ap->lock, flags);
2958 ata_eh_thaw_port(ap);
2960 ata_sff_error_handler(ap);
2962 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2965 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2966 * @qc: internal command to clean up
2969 * Kernel thread context (may sleep)
2971 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2973 struct ata_port *ap = qc->ap;
2974 unsigned long flags;
2976 if (ata_is_dma(qc->tf.protocol)) {
2977 spin_lock_irqsave(ap->lock, flags);
2978 ap->ops->bmdma_stop(qc);
2979 spin_unlock_irqrestore(ap->lock, flags);
2982 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2985 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2986 * @ap: Port associated with this ATA transaction.
2988 * Clear interrupt and error flags in DMA status register.
2990 * May be used as the irq_clear() entry in ata_port_operations.
2993 * spin_lock_irqsave(host lock)
2995 void ata_bmdma_irq_clear(struct ata_port *ap)
2997 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3002 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
3004 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
3007 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3008 * @qc: Info associated with this ATA transaction.
3011 * spin_lock_irqsave(host lock)
3013 void ata_bmdma_setup(struct ata_queued_cmd *qc)
3015 struct ata_port *ap = qc->ap;
3016 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3019 /* load PRD table addr. */
3020 mb(); /* make sure PRD table writes are visible to controller */
3021 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3023 /* specify data direction, triple-check start bit is clear */
3024 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3025 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3027 dmactl |= ATA_DMA_WR;
3028 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3030 /* issue r/w command */
3031 ap->ops->sff_exec_command(ap, &qc->tf);
3033 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
3036 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3037 * @qc: Info associated with this ATA transaction.
3040 * spin_lock_irqsave(host lock)
3042 void ata_bmdma_start(struct ata_queued_cmd *qc)
3044 struct ata_port *ap = qc->ap;
3047 /* start host DMA transaction */
3048 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3049 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3051 /* Strictly, one may wish to issue an ioread8() here, to
3052 * flush the mmio write. However, control also passes
3053 * to the hardware at this point, and it will interrupt
3054 * us when we are to resume control. So, in effect,
3055 * we don't care when the mmio write flushes.
3056 * Further, a read of the DMA status register _immediately_
3057 * following the write may not be what certain flaky hardware
3058 * is expected, so I think it is best to not add a readb()
3059 * without first all the MMIO ATA cards/mobos.
3060 * Or maybe I'm just being paranoid.
3062 * FIXME: The posting of this write means I/O starts are
3063 * unnecessarily delayed for MMIO
3066 EXPORT_SYMBOL_GPL(ata_bmdma_start);
3069 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3070 * @qc: Command we are ending DMA for
3072 * Clears the ATA_DMA_START flag in the dma control register
3074 * May be used as the bmdma_stop() entry in ata_port_operations.
3077 * spin_lock_irqsave(host lock)
3079 void ata_bmdma_stop(struct ata_queued_cmd *qc)
3081 struct ata_port *ap = qc->ap;
3082 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3084 /* clear start/stop bit */
3085 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3086 mmio + ATA_DMA_CMD);
3088 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3089 ata_sff_dma_pause(ap);
3091 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3094 * ata_bmdma_status - Read PCI IDE BMDMA status
3095 * @ap: Port associated with this ATA transaction.
3097 * Read and return BMDMA status register.
3099 * May be used as the bmdma_status() entry in ata_port_operations.
3102 * spin_lock_irqsave(host lock)
3104 u8 ata_bmdma_status(struct ata_port *ap)
3106 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3108 EXPORT_SYMBOL_GPL(ata_bmdma_status);
3112 * ata_bmdma_port_start - Set port up for bmdma.
3113 * @ap: Port to initialize
3115 * Called just after data structures for each port are
3116 * initialized. Allocates space for PRD table.
3118 * May be used as the port_start() entry in ata_port_operations.
3121 * Inherited from caller.
3123 int ata_bmdma_port_start(struct ata_port *ap)
3125 if (ap->mwdma_mask || ap->udma_mask) {
3127 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3128 &ap->bmdma_prd_dma, GFP_KERNEL);
3135 EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3138 * ata_bmdma_port_start32 - Set port up for dma.
3139 * @ap: Port to initialize
3141 * Called just after data structures for each port are
3142 * initialized. Enables 32bit PIO and allocates space for PRD
3145 * May be used as the port_start() entry in ata_port_operations for
3146 * devices that are capable of 32bit PIO.
3149 * Inherited from caller.
3151 int ata_bmdma_port_start32(struct ata_port *ap)
3153 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3154 return ata_bmdma_port_start(ap);
3156 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3161 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3164 * Some PCI ATA devices report simplex mode but in fact can be told to
3165 * enter non simplex mode. This implements the necessary logic to
3166 * perform the task on such devices. Calling it on other devices will
3167 * have -undefined- behaviour.
3169 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3171 unsigned long bmdma = pci_resource_start(pdev, 4);
3177 simplex = inb(bmdma + 0x02);
3178 outb(simplex & 0x60, bmdma + 0x02);
3179 simplex = inb(bmdma + 0x02);
3184 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3186 static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3190 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3192 for (i = 0; i < 2; i++) {
3193 host->ports[i]->mwdma_mask = 0;
3194 host->ports[i]->udma_mask = 0;
3199 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3200 * @host: target ATA host
3202 * Acquire PCI BMDMA resources and initialize @host accordingly.
3205 * Inherited from calling layer (may sleep).
3207 void ata_pci_bmdma_init(struct ata_host *host)
3209 struct device *gdev = host->dev;
3210 struct pci_dev *pdev = to_pci_dev(gdev);
3213 /* No BAR4 allocation: No DMA */
3214 if (pci_resource_start(pdev, 4) == 0) {
3215 ata_bmdma_nodma(host, "BAR4 is zero");
3220 * Some controllers require BMDMA region to be initialized
3221 * even if DMA is not in use to clear IRQ status via
3222 * ->sff_irq_clear method. Try to initialize bmdma_addr
3223 * regardless of dma masks.
3225 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
3227 ata_bmdma_nodma(host, "failed to set dma mask");
3229 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
3231 ata_bmdma_nodma(host,
3232 "failed to set consistent dma mask");
3235 /* request and iomap DMA region */
3236 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3238 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3241 host->iomap = pcim_iomap_table(pdev);
3243 for (i = 0; i < 2; i++) {
3244 struct ata_port *ap = host->ports[i];
3245 void __iomem *bmdma = host->iomap[4] + 8 * i;
3247 if (ata_port_is_dummy(ap))
3250 ap->ioaddr.bmdma_addr = bmdma;
3251 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3252 (ioread8(bmdma + 2) & 0x80))
3253 host->flags |= ATA_HOST_SIMPLEX;
3255 ata_port_desc(ap, "bmdma 0x%llx",
3256 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3259 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3262 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3263 * @pdev: target PCI device
3264 * @ppi: array of port_info, must be enough for two ports
3265 * @r_host: out argument for the initialized ATA host
3267 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3268 * resources and initialize it accordingly in one go.
3271 * Inherited from calling layer (may sleep).
3274 * 0 on success, -errno otherwise.
3276 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3277 const struct ata_port_info * const * ppi,
3278 struct ata_host **r_host)
3282 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3286 ata_pci_bmdma_init(*r_host);
3289 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3292 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3293 * @pdev: Controller to be initialized
3294 * @ppi: array of port_info, must be enough for two ports
3295 * @sht: scsi_host_template to use when registering the host
3296 * @host_priv: host private_data
3297 * @hflags: host flags
3299 * This function is similar to ata_pci_sff_init_one() but also
3300 * takes care of BMDMA initialization.
3303 * Inherited from PCI layer (may sleep).
3306 * Zero on success, negative on errno-based value on error.
3308 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3309 const struct ata_port_info * const * ppi,
3310 struct scsi_host_template *sht, void *host_priv,
3313 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3315 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3317 #endif /* CONFIG_PCI */
3318 #endif /* CONFIG_ATA_BMDMA */
3321 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3322 * @ap: Port to initialize
3324 * Called on port allocation to initialize SFF/BMDMA specific
3330 void ata_sff_port_init(struct ata_port *ap)
3332 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3333 ap->ctl = ATA_DEVCTL_OBS;
3334 ap->last_ctl = 0xFF;
3337 int __init ata_sff_init(void)
3339 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3346 void ata_sff_exit(void)
3348 destroy_workqueue(ata_sff_wq);