1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libata-sff.c - helper library for PCI IDE BMDMA
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
10 * Copyright 2003-2006 Jeff Garzik
12 * libata documentation is available via 'make {ps|pdf}docs',
13 * as Documentation/driver-api/libata.rst
15 * Hardware documentation available from http://www.t13.org/ and
16 * http://www.sata-io.org/
19 #include <linux/kernel.h>
20 #include <linux/gfp.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/libata.h>
24 #include <linux/highmem.h>
28 static struct workqueue_struct *ata_sff_wq;
30 const struct ata_port_operations ata_sff_port_ops = {
31 .inherits = &ata_base_port_ops,
33 .qc_prep = ata_noop_qc_prep,
34 .qc_issue = ata_sff_qc_issue,
35 .qc_fill_rtf = ata_sff_qc_fill_rtf,
37 .freeze = ata_sff_freeze,
39 .prereset = ata_sff_prereset,
40 .softreset = ata_sff_softreset,
41 .hardreset = sata_sff_hardreset,
42 .postreset = ata_sff_postreset,
43 .error_handler = ata_sff_error_handler,
45 .sff_dev_select = ata_sff_dev_select,
46 .sff_check_status = ata_sff_check_status,
47 .sff_tf_load = ata_sff_tf_load,
48 .sff_tf_read = ata_sff_tf_read,
49 .sff_exec_command = ata_sff_exec_command,
50 .sff_data_xfer = ata_sff_data_xfer,
51 .sff_drain_fifo = ata_sff_drain_fifo,
53 .lost_interrupt = ata_sff_lost_interrupt,
55 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
58 * ata_sff_check_status - Read device status reg & clear interrupt
59 * @ap: port where the device is
61 * Reads ATA taskfile status register for currently-selected device
62 * and return its value. This also clears pending interrupts
66 * Inherited from caller.
68 u8 ata_sff_check_status(struct ata_port *ap)
70 return ioread8(ap->ioaddr.status_addr);
72 EXPORT_SYMBOL_GPL(ata_sff_check_status);
75 * ata_sff_altstatus - Read device alternate status reg
76 * @ap: port where the device is
78 * Reads ATA taskfile alternate status register for
79 * currently-selected device and return its value.
81 * Note: may NOT be used as the check_altstatus() entry in
82 * ata_port_operations.
85 * Inherited from caller.
87 static u8 ata_sff_altstatus(struct ata_port *ap)
89 if (ap->ops->sff_check_altstatus)
90 return ap->ops->sff_check_altstatus(ap);
92 return ioread8(ap->ioaddr.altstatus_addr);
96 * ata_sff_irq_status - Check if the device is busy
97 * @ap: port where the device is
99 * Determine if the port is currently busy. Uses altstatus
100 * if available in order to avoid clearing shared IRQ status
101 * when finding an IRQ source. Non ctl capable devices don't
102 * share interrupt lines fortunately for us.
105 * Inherited from caller.
107 static u8 ata_sff_irq_status(struct ata_port *ap)
111 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
112 status = ata_sff_altstatus(ap);
113 /* Not us: We are busy */
114 if (status & ATA_BUSY)
117 /* Clear INTRQ latch */
118 status = ap->ops->sff_check_status(ap);
123 * ata_sff_sync - Flush writes
124 * @ap: Port to wait for.
127 * If we have an mmio device with no ctl and no altstatus
128 * method this will fail. No such devices are known to exist.
131 * Inherited from caller.
134 static void ata_sff_sync(struct ata_port *ap)
136 if (ap->ops->sff_check_altstatus)
137 ap->ops->sff_check_altstatus(ap);
138 else if (ap->ioaddr.altstatus_addr)
139 ioread8(ap->ioaddr.altstatus_addr);
143 * ata_sff_pause - Flush writes and wait 400nS
144 * @ap: Port to pause for.
147 * If we have an mmio device with no ctl and no altstatus
148 * method this will fail. No such devices are known to exist.
151 * Inherited from caller.
154 void ata_sff_pause(struct ata_port *ap)
159 EXPORT_SYMBOL_GPL(ata_sff_pause);
162 * ata_sff_dma_pause - Pause before commencing DMA
163 * @ap: Port to pause for.
165 * Perform I/O fencing and ensure sufficient cycle delays occur
166 * for the HDMA1:0 transition
169 void ata_sff_dma_pause(struct ata_port *ap)
171 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
172 /* An altstatus read will cause the needed delay without
173 messing up the IRQ status */
174 ata_sff_altstatus(ap);
177 /* There are no DMA controllers without ctl. BUG here to ensure
178 we never violate the HDMA1:0 transition timing and risk
182 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
185 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
186 * @ap: port containing status register to be polled
187 * @tmout_pat: impatience timeout in msecs
188 * @tmout: overall timeout in msecs
190 * Sleep until ATA Status register bit BSY clears,
191 * or a timeout occurs.
194 * Kernel thread context (may sleep).
197 * 0 on success, -errno otherwise.
199 int ata_sff_busy_sleep(struct ata_port *ap,
200 unsigned long tmout_pat, unsigned long tmout)
202 unsigned long timer_start, timeout;
205 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
206 timer_start = jiffies;
207 timeout = ata_deadline(timer_start, tmout_pat);
208 while (status != 0xff && (status & ATA_BUSY) &&
209 time_before(jiffies, timeout)) {
211 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
214 if (status != 0xff && (status & ATA_BUSY))
216 "port is slow to respond, please be patient (Status 0x%x)\n",
219 timeout = ata_deadline(timer_start, tmout);
220 while (status != 0xff && (status & ATA_BUSY) &&
221 time_before(jiffies, timeout)) {
223 status = ap->ops->sff_check_status(ap);
229 if (status & ATA_BUSY) {
231 "port failed to respond (%lu secs, Status 0x%x)\n",
232 DIV_ROUND_UP(tmout, 1000), status);
238 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
240 static int ata_sff_check_ready(struct ata_link *link)
242 u8 status = link->ap->ops->sff_check_status(link->ap);
244 return ata_check_ready(status);
248 * ata_sff_wait_ready - sleep until BSY clears, or timeout
249 * @link: SFF link to wait ready status for
250 * @deadline: deadline jiffies for the operation
252 * Sleep until ATA Status register bit BSY clears, or timeout
256 * Kernel thread context (may sleep).
259 * 0 on success, -errno otherwise.
261 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
263 return ata_wait_ready(link, deadline, ata_sff_check_ready);
265 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
268 * ata_sff_set_devctl - Write device control reg
269 * @ap: port where the device is
270 * @ctl: value to write
272 * Writes ATA taskfile device control register.
274 * Note: may NOT be used as the sff_set_devctl() entry in
275 * ata_port_operations.
278 * Inherited from caller.
280 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
282 if (ap->ops->sff_set_devctl)
283 ap->ops->sff_set_devctl(ap, ctl);
285 iowrite8(ctl, ap->ioaddr.ctl_addr);
289 * ata_sff_dev_select - Select device 0/1 on ATA bus
290 * @ap: ATA channel to manipulate
291 * @device: ATA device (numbered from zero) to select
293 * Use the method defined in the ATA specification to
294 * make either device 0, or device 1, active on the
295 * ATA channel. Works with both PIO and MMIO.
297 * May be used as the dev_select() entry in ata_port_operations.
302 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
307 tmp = ATA_DEVICE_OBS;
309 tmp = ATA_DEVICE_OBS | ATA_DEV1;
311 iowrite8(tmp, ap->ioaddr.device_addr);
312 ata_sff_pause(ap); /* needed; also flushes, for mmio */
314 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
317 * ata_dev_select - Select device 0/1 on ATA bus
318 * @ap: ATA channel to manipulate
319 * @device: ATA device (numbered from zero) to select
320 * @wait: non-zero to wait for Status register BSY bit to clear
321 * @can_sleep: non-zero if context allows sleeping
323 * Use the method defined in the ATA specification to
324 * make either device 0, or device 1, active on the
327 * This is a high-level version of ata_sff_dev_select(), which
328 * additionally provides the services of inserting the proper
329 * pauses and status polling, where needed.
334 static void ata_dev_select(struct ata_port *ap, unsigned int device,
335 unsigned int wait, unsigned int can_sleep)
337 if (ata_msg_probe(ap))
338 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
344 ap->ops->sff_dev_select(ap, device);
347 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
354 * ata_sff_irq_on - Enable interrupts on a port.
355 * @ap: Port on which interrupts are enabled.
357 * Enable interrupts on a legacy IDE device using MMIO or PIO,
358 * wait for idle, clear any pending interrupts.
360 * Note: may NOT be used as the sff_irq_on() entry in
361 * ata_port_operations.
364 * Inherited from caller.
366 void ata_sff_irq_on(struct ata_port *ap)
368 struct ata_ioports *ioaddr = &ap->ioaddr;
370 if (ap->ops->sff_irq_on) {
371 ap->ops->sff_irq_on(ap);
375 ap->ctl &= ~ATA_NIEN;
376 ap->last_ctl = ap->ctl;
378 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
379 ata_sff_set_devctl(ap, ap->ctl);
382 if (ap->ops->sff_irq_clear)
383 ap->ops->sff_irq_clear(ap);
385 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
388 * ata_sff_tf_load - send taskfile registers to host controller
389 * @ap: Port to which output is sent
390 * @tf: ATA taskfile register set
392 * Outputs ATA taskfile to standard ATA host controller.
395 * Inherited from caller.
397 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
399 struct ata_ioports *ioaddr = &ap->ioaddr;
400 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
402 if (tf->ctl != ap->last_ctl) {
403 if (ioaddr->ctl_addr)
404 iowrite8(tf->ctl, ioaddr->ctl_addr);
405 ap->last_ctl = tf->ctl;
409 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
410 WARN_ON_ONCE(!ioaddr->ctl_addr);
411 iowrite8(tf->hob_feature, ioaddr->feature_addr);
412 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
413 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
414 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
415 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
416 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
425 iowrite8(tf->feature, ioaddr->feature_addr);
426 iowrite8(tf->nsect, ioaddr->nsect_addr);
427 iowrite8(tf->lbal, ioaddr->lbal_addr);
428 iowrite8(tf->lbam, ioaddr->lbam_addr);
429 iowrite8(tf->lbah, ioaddr->lbah_addr);
430 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
438 if (tf->flags & ATA_TFLAG_DEVICE) {
439 iowrite8(tf->device, ioaddr->device_addr);
440 VPRINTK("device 0x%X\n", tf->device);
445 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
448 * ata_sff_tf_read - input device's ATA taskfile shadow registers
449 * @ap: Port from which input is read
450 * @tf: ATA taskfile register set for storing input
452 * Reads ATA taskfile registers for currently-selected device
453 * into @tf. Assumes the device has a fully SFF compliant task file
454 * layout and behaviour. If you device does not (eg has a different
455 * status method) then you will need to provide a replacement tf_read
458 * Inherited from caller.
460 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
462 struct ata_ioports *ioaddr = &ap->ioaddr;
464 tf->command = ata_sff_check_status(ap);
465 tf->feature = ioread8(ioaddr->error_addr);
466 tf->nsect = ioread8(ioaddr->nsect_addr);
467 tf->lbal = ioread8(ioaddr->lbal_addr);
468 tf->lbam = ioread8(ioaddr->lbam_addr);
469 tf->lbah = ioread8(ioaddr->lbah_addr);
470 tf->device = ioread8(ioaddr->device_addr);
472 if (tf->flags & ATA_TFLAG_LBA48) {
473 if (likely(ioaddr->ctl_addr)) {
474 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
475 tf->hob_feature = ioread8(ioaddr->error_addr);
476 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
477 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
478 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
479 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
480 iowrite8(tf->ctl, ioaddr->ctl_addr);
481 ap->last_ctl = tf->ctl;
486 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
489 * ata_sff_exec_command - issue ATA command to host controller
490 * @ap: port to which command is being issued
491 * @tf: ATA taskfile register set
493 * Issues ATA command, with proper synchronization with interrupt
494 * handler / other threads.
497 * spin_lock_irqsave(host lock)
499 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
501 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
503 iowrite8(tf->command, ap->ioaddr.command_addr);
506 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
509 * ata_tf_to_host - issue ATA taskfile to host controller
510 * @ap: port to which command is being issued
511 * @tf: ATA taskfile register set
513 * Issues ATA taskfile register set to ATA host controller,
514 * with proper synchronization with interrupt handler and
518 * spin_lock_irqsave(host lock)
520 static inline void ata_tf_to_host(struct ata_port *ap,
521 const struct ata_taskfile *tf)
523 ap->ops->sff_tf_load(ap, tf);
524 ap->ops->sff_exec_command(ap, tf);
528 * ata_sff_data_xfer - Transfer data by PIO
529 * @qc: queued command
531 * @buflen: buffer length
534 * Transfer data from/to the device data register by PIO.
537 * Inherited from caller.
542 unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf,
543 unsigned int buflen, int rw)
545 struct ata_port *ap = qc->dev->link->ap;
546 void __iomem *data_addr = ap->ioaddr.data_addr;
547 unsigned int words = buflen >> 1;
549 /* Transfer multiple of 2 bytes */
551 ioread16_rep(data_addr, buf, words);
553 iowrite16_rep(data_addr, buf, words);
555 /* Transfer trailing byte, if any. */
556 if (unlikely(buflen & 0x01)) {
557 unsigned char pad[2] = { };
559 /* Point buf to the tail of buffer */
563 * Use io*16_rep() accessors here as well to avoid pointlessly
564 * swapping bytes to and from on the big endian machines...
567 ioread16_rep(data_addr, pad, 1);
571 iowrite16_rep(data_addr, pad, 1);
578 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
581 * ata_sff_data_xfer32 - Transfer data by PIO
582 * @qc: queued command
584 * @buflen: buffer length
587 * Transfer data from/to the device data register by PIO using 32bit
591 * Inherited from caller.
597 unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
598 unsigned int buflen, int rw)
600 struct ata_device *dev = qc->dev;
601 struct ata_port *ap = dev->link->ap;
602 void __iomem *data_addr = ap->ioaddr.data_addr;
603 unsigned int words = buflen >> 2;
604 int slop = buflen & 3;
606 if (!(ap->pflags & ATA_PFLAG_PIO32))
607 return ata_sff_data_xfer(qc, buf, buflen, rw);
609 /* Transfer multiple of 4 bytes */
611 ioread32_rep(data_addr, buf, words);
613 iowrite32_rep(data_addr, buf, words);
615 /* Transfer trailing bytes, if any */
616 if (unlikely(slop)) {
617 unsigned char pad[4] = { };
619 /* Point buf to the tail of buffer */
620 buf += buflen - slop;
623 * Use io*_rep() accessors here as well to avoid pointlessly
624 * swapping bytes to and from on the big endian machines...
628 ioread16_rep(data_addr, pad, 1);
630 ioread32_rep(data_addr, pad, 1);
631 memcpy(buf, pad, slop);
633 memcpy(pad, buf, slop);
635 iowrite16_rep(data_addr, pad, 1);
637 iowrite32_rep(data_addr, pad, 1);
640 return (buflen + 1) & ~1;
642 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
644 static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
645 unsigned int offset, size_t xfer_size)
647 bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
650 buf = kmap_atomic(page);
651 qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
654 if (!do_write && !PageSlab(page))
655 flush_dcache_page(page);
659 * ata_pio_sector - Transfer a sector of data.
660 * @qc: Command on going
662 * Transfer qc->sect_size bytes of data from/to the ATA device.
665 * Inherited from caller.
667 static void ata_pio_sector(struct ata_queued_cmd *qc)
669 struct ata_port *ap = qc->ap;
674 qc->curbytes = qc->nbytes;
677 if (qc->curbytes == qc->nbytes - qc->sect_size)
678 ap->hsm_task_state = HSM_ST_LAST;
680 page = sg_page(qc->cursg);
681 offset = qc->cursg->offset + qc->cursg_ofs;
683 /* get the current page and offset */
684 page = nth_page(page, (offset >> PAGE_SHIFT));
687 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
690 * Split the transfer when it splits a page boundary. Note that the
691 * split still has to be dword aligned like all ATA data transfers.
693 WARN_ON_ONCE(offset % 4);
694 if (offset + qc->sect_size > PAGE_SIZE) {
695 unsigned int split_len = PAGE_SIZE - offset;
697 ata_pio_xfer(qc, page, offset, split_len);
698 ata_pio_xfer(qc, nth_page(page, 1), 0,
699 qc->sect_size - split_len);
701 ata_pio_xfer(qc, page, offset, qc->sect_size);
704 qc->curbytes += qc->sect_size;
705 qc->cursg_ofs += qc->sect_size;
707 if (qc->cursg_ofs == qc->cursg->length) {
708 qc->cursg = sg_next(qc->cursg);
710 ap->hsm_task_state = HSM_ST_LAST;
716 * ata_pio_sectors - Transfer one or many sectors.
717 * @qc: Command on going
719 * Transfer one or many sectors of data from/to the
720 * ATA device for the DRQ request.
723 * Inherited from caller.
725 static void ata_pio_sectors(struct ata_queued_cmd *qc)
727 if (is_multi_taskfile(&qc->tf)) {
728 /* READ/WRITE MULTIPLE */
731 WARN_ON_ONCE(qc->dev->multi_count == 0);
733 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
734 qc->dev->multi_count);
740 ata_sff_sync(qc->ap); /* flush */
744 * atapi_send_cdb - Write CDB bytes to hardware
745 * @ap: Port to which ATAPI device is attached.
746 * @qc: Taskfile currently active
748 * When device has indicated its readiness to accept
749 * a CDB, this function is called. Send the CDB.
754 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
757 DPRINTK("send cdb\n");
758 WARN_ON_ONCE(qc->dev->cdb_len < 12);
760 ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
762 /* FIXME: If the CDB is for DMA do we need to do the transition delay
763 or is bmdma_start guaranteed to do it ? */
764 switch (qc->tf.protocol) {
766 ap->hsm_task_state = HSM_ST;
768 case ATAPI_PROT_NODATA:
769 ap->hsm_task_state = HSM_ST_LAST;
771 #ifdef CONFIG_ATA_BMDMA
773 ap->hsm_task_state = HSM_ST_LAST;
775 ap->ops->bmdma_start(qc);
777 #endif /* CONFIG_ATA_BMDMA */
784 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
785 * @qc: Command on going
786 * @bytes: number of bytes
788 * Transfer Transfer data from/to the ATAPI device.
791 * Inherited from caller.
794 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
796 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
797 struct ata_port *ap = qc->ap;
798 struct ata_device *dev = qc->dev;
799 struct ata_eh_info *ehi = &dev->link->eh_info;
800 struct scatterlist *sg;
803 unsigned int offset, count, consumed;
808 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
809 "buf=%u cur=%u bytes=%u",
810 qc->nbytes, qc->curbytes, bytes);
815 offset = sg->offset + qc->cursg_ofs;
817 /* get the current page and offset */
818 page = nth_page(page, (offset >> PAGE_SHIFT));
821 /* don't overrun current sg */
822 count = min(sg->length - qc->cursg_ofs, bytes);
824 /* don't cross page boundaries */
825 count = min(count, (unsigned int)PAGE_SIZE - offset);
827 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
829 /* do the actual data transfer */
830 buf = kmap_atomic(page);
831 consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw);
834 bytes -= min(bytes, consumed);
835 qc->curbytes += count;
836 qc->cursg_ofs += count;
838 if (qc->cursg_ofs == sg->length) {
839 qc->cursg = sg_next(qc->cursg);
844 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
845 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
846 * check correctly as it doesn't know if it is the last request being
847 * made. Somebody should implement a proper sanity check.
855 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
856 * @qc: Command on going
858 * Transfer Transfer data from/to the ATAPI device.
861 * Inherited from caller.
863 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
865 struct ata_port *ap = qc->ap;
866 struct ata_device *dev = qc->dev;
867 struct ata_eh_info *ehi = &dev->link->eh_info;
868 unsigned int ireason, bc_lo, bc_hi, bytes;
869 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
871 /* Abuse qc->result_tf for temp storage of intermediate TF
872 * here to save some kernel stack usage.
873 * For normal completion, qc->result_tf is not relevant. For
874 * error, qc->result_tf is later overwritten by ata_qc_complete().
875 * So, the correctness of qc->result_tf is not affected.
877 ap->ops->sff_tf_read(ap, &qc->result_tf);
878 ireason = qc->result_tf.nsect;
879 bc_lo = qc->result_tf.lbam;
880 bc_hi = qc->result_tf.lbah;
881 bytes = (bc_hi << 8) | bc_lo;
883 /* shall be cleared to zero, indicating xfer of data */
884 if (unlikely(ireason & ATAPI_COD))
887 /* make sure transfer direction matches expected */
888 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
889 if (unlikely(do_write != i_write))
892 if (unlikely(!bytes))
895 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
897 if (unlikely(__atapi_pio_bytes(qc, bytes)))
899 ata_sff_sync(ap); /* flush */
904 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
907 qc->err_mask |= AC_ERR_HSM;
908 ap->hsm_task_state = HSM_ST_ERR;
912 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
913 * @ap: the target ata_port
917 * 1 if ok in workqueue, 0 otherwise.
919 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
920 struct ata_queued_cmd *qc)
922 if (qc->tf.flags & ATA_TFLAG_POLLING)
925 if (ap->hsm_task_state == HSM_ST_FIRST) {
926 if (qc->tf.protocol == ATA_PROT_PIO &&
927 (qc->tf.flags & ATA_TFLAG_WRITE))
930 if (ata_is_atapi(qc->tf.protocol) &&
931 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
939 * ata_hsm_qc_complete - finish a qc running on standard HSM
940 * @qc: Command to complete
941 * @in_wq: 1 if called from workqueue, 0 otherwise
943 * Finish @qc which is running on standard HSM.
946 * If @in_wq is zero, spin_lock_irqsave(host lock).
947 * Otherwise, none on entry and grabs host lock.
949 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
951 struct ata_port *ap = qc->ap;
953 if (ap->ops->error_handler) {
955 /* EH might have kicked in while host lock is
958 qc = ata_qc_from_tag(ap, qc->tag);
960 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
967 if (likely(!(qc->err_mask & AC_ERR_HSM)))
982 * ata_sff_hsm_move - move the HSM to the next state.
983 * @ap: the target ata_port
985 * @status: current device status
986 * @in_wq: 1 if called from workqueue, 0 otherwise
989 * 1 when poll next status needed, 0 otherwise.
991 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
992 u8 status, int in_wq)
994 struct ata_link *link = qc->dev->link;
995 struct ata_eh_info *ehi = &link->eh_info;
998 lockdep_assert_held(ap->lock);
1000 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1002 /* Make sure ata_sff_qc_issue() does not throw things
1003 * like DMA polling into the workqueue. Notice that
1004 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1006 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1009 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1010 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1012 switch (ap->hsm_task_state) {
1014 /* Send first data block or PACKET CDB */
1016 /* If polling, we will stay in the work queue after
1017 * sending the data. Otherwise, interrupt handler
1018 * takes over after sending the data.
1020 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1022 /* check device status */
1023 if (unlikely((status & ATA_DRQ) == 0)) {
1024 /* handle BSY=0, DRQ=0 as error */
1025 if (likely(status & (ATA_ERR | ATA_DF)))
1026 /* device stops HSM for abort/error */
1027 qc->err_mask |= AC_ERR_DEV;
1029 /* HSM violation. Let EH handle this */
1030 ata_ehi_push_desc(ehi,
1031 "ST_FIRST: !(DRQ|ERR|DF)");
1032 qc->err_mask |= AC_ERR_HSM;
1035 ap->hsm_task_state = HSM_ST_ERR;
1039 /* Device should not ask for data transfer (DRQ=1)
1040 * when it finds something wrong.
1041 * We ignore DRQ here and stop the HSM by
1042 * changing hsm_task_state to HSM_ST_ERR and
1043 * let the EH abort the command or reset the device.
1045 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1046 /* Some ATAPI tape drives forget to clear the ERR bit
1047 * when doing the next command (mostly request sense).
1048 * We ignore ERR here to workaround and proceed sending
1051 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1052 ata_ehi_push_desc(ehi, "ST_FIRST: "
1053 "DRQ=1 with device error, "
1054 "dev_stat 0x%X", status);
1055 qc->err_mask |= AC_ERR_HSM;
1056 ap->hsm_task_state = HSM_ST_ERR;
1061 if (qc->tf.protocol == ATA_PROT_PIO) {
1062 /* PIO data out protocol.
1063 * send first data block.
1066 /* ata_pio_sectors() might change the state
1067 * to HSM_ST_LAST. so, the state is changed here
1068 * before ata_pio_sectors().
1070 ap->hsm_task_state = HSM_ST;
1071 ata_pio_sectors(qc);
1074 atapi_send_cdb(ap, qc);
1076 /* if polling, ata_sff_pio_task() handles the rest.
1077 * otherwise, interrupt handler takes over from here.
1082 /* complete command or read/write the data register */
1083 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1084 /* ATAPI PIO protocol */
1085 if ((status & ATA_DRQ) == 0) {
1086 /* No more data to transfer or device error.
1087 * Device error will be tagged in HSM_ST_LAST.
1089 ap->hsm_task_state = HSM_ST_LAST;
1093 /* Device should not ask for data transfer (DRQ=1)
1094 * when it finds something wrong.
1095 * We ignore DRQ here and stop the HSM by
1096 * changing hsm_task_state to HSM_ST_ERR and
1097 * let the EH abort the command or reset the device.
1099 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1100 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1101 "DRQ=1 with device error, "
1102 "dev_stat 0x%X", status);
1103 qc->err_mask |= AC_ERR_HSM;
1104 ap->hsm_task_state = HSM_ST_ERR;
1108 atapi_pio_bytes(qc);
1110 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1111 /* bad ireason reported by device */
1115 /* ATA PIO protocol */
1116 if (unlikely((status & ATA_DRQ) == 0)) {
1117 /* handle BSY=0, DRQ=0 as error */
1118 if (likely(status & (ATA_ERR | ATA_DF))) {
1119 /* device stops HSM for abort/error */
1120 qc->err_mask |= AC_ERR_DEV;
1122 /* If diagnostic failed and this is
1123 * IDENTIFY, it's likely a phantom
1124 * device. Mark hint.
1126 if (qc->dev->horkage &
1127 ATA_HORKAGE_DIAGNOSTIC)
1131 /* HSM violation. Let EH handle this.
1132 * Phantom devices also trigger this
1133 * condition. Mark hint.
1135 ata_ehi_push_desc(ehi, "ST-ATA: "
1136 "DRQ=0 without device error, "
1137 "dev_stat 0x%X", status);
1138 qc->err_mask |= AC_ERR_HSM |
1142 ap->hsm_task_state = HSM_ST_ERR;
1146 /* For PIO reads, some devices may ask for
1147 * data transfer (DRQ=1) alone with ERR=1.
1148 * We respect DRQ here and transfer one
1149 * block of junk data before changing the
1150 * hsm_task_state to HSM_ST_ERR.
1152 * For PIO writes, ERR=1 DRQ=1 doesn't make
1153 * sense since the data block has been
1154 * transferred to the device.
1156 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1157 /* data might be corrputed */
1158 qc->err_mask |= AC_ERR_DEV;
1160 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1161 ata_pio_sectors(qc);
1162 status = ata_wait_idle(ap);
1165 if (status & (ATA_BUSY | ATA_DRQ)) {
1166 ata_ehi_push_desc(ehi, "ST-ATA: "
1167 "BUSY|DRQ persists on ERR|DF, "
1168 "dev_stat 0x%X", status);
1169 qc->err_mask |= AC_ERR_HSM;
1172 /* There are oddball controllers with
1173 * status register stuck at 0x7f and
1174 * lbal/m/h at zero which makes it
1175 * pass all other presence detection
1176 * mechanisms we have. Set NODEV_HINT
1177 * for it. Kernel bz#7241.
1180 qc->err_mask |= AC_ERR_NODEV_HINT;
1182 /* ata_pio_sectors() might change the
1183 * state to HSM_ST_LAST. so, the state
1184 * is changed after ata_pio_sectors().
1186 ap->hsm_task_state = HSM_ST_ERR;
1190 ata_pio_sectors(qc);
1192 if (ap->hsm_task_state == HSM_ST_LAST &&
1193 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1195 status = ata_wait_idle(ap);
1204 if (unlikely(!ata_ok(status))) {
1205 qc->err_mask |= __ac_err_mask(status);
1206 ap->hsm_task_state = HSM_ST_ERR;
1210 /* no more data to transfer */
1211 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1212 ap->print_id, qc->dev->devno, status);
1214 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1216 ap->hsm_task_state = HSM_ST_IDLE;
1218 /* complete taskfile transaction */
1219 ata_hsm_qc_complete(qc, in_wq);
1225 ap->hsm_task_state = HSM_ST_IDLE;
1227 /* complete taskfile transaction */
1228 ata_hsm_qc_complete(qc, in_wq);
1234 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1235 ap->print_id, ap->hsm_task_state);
1240 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1242 void ata_sff_queue_work(struct work_struct *work)
1244 queue_work(ata_sff_wq, work);
1246 EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1248 void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1250 queue_delayed_work(ata_sff_wq, dwork, delay);
1252 EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1254 void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1256 struct ata_port *ap = link->ap;
1258 WARN_ON((ap->sff_pio_task_link != NULL) &&
1259 (ap->sff_pio_task_link != link));
1260 ap->sff_pio_task_link = link;
1262 /* may fail if ata_sff_flush_pio_task() in progress */
1263 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1265 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1267 void ata_sff_flush_pio_task(struct ata_port *ap)
1271 cancel_delayed_work_sync(&ap->sff_pio_task);
1274 * We wanna reset the HSM state to IDLE. If we do so without
1275 * grabbing the port lock, critical sections protected by it which
1276 * expect the HSM state to stay stable may get surprised. For
1277 * example, we may set IDLE in between the time
1278 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1279 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1281 spin_lock_irq(ap->lock);
1282 ap->hsm_task_state = HSM_ST_IDLE;
1283 spin_unlock_irq(ap->lock);
1285 ap->sff_pio_task_link = NULL;
1287 if (ata_msg_ctl(ap))
1288 ata_port_dbg(ap, "%s: EXIT\n", __func__);
1291 static void ata_sff_pio_task(struct work_struct *work)
1293 struct ata_port *ap =
1294 container_of(work, struct ata_port, sff_pio_task.work);
1295 struct ata_link *link = ap->sff_pio_task_link;
1296 struct ata_queued_cmd *qc;
1300 spin_lock_irq(ap->lock);
1302 BUG_ON(ap->sff_pio_task_link == NULL);
1303 /* qc can be NULL if timeout occurred */
1304 qc = ata_qc_from_tag(ap, link->active_tag);
1306 ap->sff_pio_task_link = NULL;
1311 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1314 * This is purely heuristic. This is a fast path.
1315 * Sometimes when we enter, BSY will be cleared in
1316 * a chk-status or two. If not, the drive is probably seeking
1317 * or something. Snooze for a couple msecs, then
1318 * chk-status again. If still busy, queue delayed work.
1320 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1321 if (status & ATA_BUSY) {
1322 spin_unlock_irq(ap->lock);
1324 spin_lock_irq(ap->lock);
1326 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1327 if (status & ATA_BUSY) {
1328 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1334 * hsm_move() may trigger another command to be processed.
1335 * clean the link beforehand.
1337 ap->sff_pio_task_link = NULL;
1339 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1341 /* another command or interrupt handler
1342 * may be running at this point.
1347 spin_unlock_irq(ap->lock);
1351 * ata_sff_qc_issue - issue taskfile to a SFF controller
1352 * @qc: command to issue to device
1354 * This function issues a PIO or NODATA command to a SFF
1358 * spin_lock_irqsave(host lock)
1361 * Zero on success, AC_ERR_* mask on failure
1363 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1365 struct ata_port *ap = qc->ap;
1366 struct ata_link *link = qc->dev->link;
1368 /* Use polling pio if the LLD doesn't handle
1369 * interrupt driven pio and atapi CDB interrupt.
1371 if (ap->flags & ATA_FLAG_PIO_POLLING)
1372 qc->tf.flags |= ATA_TFLAG_POLLING;
1374 /* select the device */
1375 ata_dev_select(ap, qc->dev->devno, 1, 0);
1377 /* start the command */
1378 switch (qc->tf.protocol) {
1379 case ATA_PROT_NODATA:
1380 if (qc->tf.flags & ATA_TFLAG_POLLING)
1381 ata_qc_set_polling(qc);
1383 ata_tf_to_host(ap, &qc->tf);
1384 ap->hsm_task_state = HSM_ST_LAST;
1386 if (qc->tf.flags & ATA_TFLAG_POLLING)
1387 ata_sff_queue_pio_task(link, 0);
1392 if (qc->tf.flags & ATA_TFLAG_POLLING)
1393 ata_qc_set_polling(qc);
1395 ata_tf_to_host(ap, &qc->tf);
1397 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1398 /* PIO data out protocol */
1399 ap->hsm_task_state = HSM_ST_FIRST;
1400 ata_sff_queue_pio_task(link, 0);
1402 /* always send first data block using the
1403 * ata_sff_pio_task() codepath.
1406 /* PIO data in protocol */
1407 ap->hsm_task_state = HSM_ST;
1409 if (qc->tf.flags & ATA_TFLAG_POLLING)
1410 ata_sff_queue_pio_task(link, 0);
1412 /* if polling, ata_sff_pio_task() handles the
1413 * rest. otherwise, interrupt handler takes
1420 case ATAPI_PROT_PIO:
1421 case ATAPI_PROT_NODATA:
1422 if (qc->tf.flags & ATA_TFLAG_POLLING)
1423 ata_qc_set_polling(qc);
1425 ata_tf_to_host(ap, &qc->tf);
1427 ap->hsm_task_state = HSM_ST_FIRST;
1429 /* send cdb by polling if no cdb interrupt */
1430 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1431 (qc->tf.flags & ATA_TFLAG_POLLING))
1432 ata_sff_queue_pio_task(link, 0);
1436 return AC_ERR_SYSTEM;
1441 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1444 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1445 * @qc: qc to fill result TF for
1447 * @qc is finished and result TF needs to be filled. Fill it
1448 * using ->sff_tf_read.
1451 * spin_lock_irqsave(host lock)
1454 * true indicating that result TF is successfully filled.
1456 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1458 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1461 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1463 static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1465 ap->stats.idle_irq++;
1468 if ((ap->stats.idle_irq % 1000) == 0) {
1469 ap->ops->sff_check_status(ap);
1470 if (ap->ops->sff_irq_clear)
1471 ap->ops->sff_irq_clear(ap);
1472 ata_port_warn(ap, "irq trap\n");
1476 return 0; /* irq not handled */
1479 static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1480 struct ata_queued_cmd *qc,
1485 VPRINTK("ata%u: protocol %d task_state %d\n",
1486 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1488 /* Check whether we are expecting interrupt in this state */
1489 switch (ap->hsm_task_state) {
1491 /* Some pre-ATAPI-4 devices assert INTRQ
1492 * at this state when ready to receive CDB.
1495 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1496 * The flag was turned on only for atapi devices. No
1497 * need to check ata_is_atapi(qc->tf.protocol) again.
1499 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1500 return ata_sff_idle_irq(ap);
1503 return ata_sff_idle_irq(ap);
1508 /* check main status, clearing INTRQ if needed */
1509 status = ata_sff_irq_status(ap);
1510 if (status & ATA_BUSY) {
1512 /* BMDMA engine is already stopped, we're screwed */
1513 qc->err_mask |= AC_ERR_HSM;
1514 ap->hsm_task_state = HSM_ST_ERR;
1516 return ata_sff_idle_irq(ap);
1519 /* clear irq events */
1520 if (ap->ops->sff_irq_clear)
1521 ap->ops->sff_irq_clear(ap);
1523 ata_sff_hsm_move(ap, qc, status, 0);
1525 return 1; /* irq handled */
1529 * ata_sff_port_intr - Handle SFF port interrupt
1530 * @ap: Port on which interrupt arrived (possibly...)
1531 * @qc: Taskfile currently active in engine
1533 * Handle port interrupt for given queued command.
1536 * spin_lock_irqsave(host lock)
1539 * One if interrupt was handled, zero if not (shared irq).
1541 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1543 return __ata_sff_port_intr(ap, qc, false);
1545 EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1547 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1548 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1550 struct ata_host *host = dev_instance;
1551 bool retried = false;
1553 unsigned int handled, idle, polling;
1554 unsigned long flags;
1556 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1557 spin_lock_irqsave(&host->lock, flags);
1560 handled = idle = polling = 0;
1561 for (i = 0; i < host->n_ports; i++) {
1562 struct ata_port *ap = host->ports[i];
1563 struct ata_queued_cmd *qc;
1565 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1567 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1568 handled |= port_intr(ap, qc);
1576 * If no port was expecting IRQ but the controller is actually
1577 * asserting IRQ line, nobody cared will ensue. Check IRQ
1578 * pending status if available and clear spurious IRQ.
1580 if (!handled && !retried) {
1583 for (i = 0; i < host->n_ports; i++) {
1584 struct ata_port *ap = host->ports[i];
1586 if (polling & (1 << i))
1589 if (!ap->ops->sff_irq_check ||
1590 !ap->ops->sff_irq_check(ap))
1593 if (idle & (1 << i)) {
1594 ap->ops->sff_check_status(ap);
1595 if (ap->ops->sff_irq_clear)
1596 ap->ops->sff_irq_clear(ap);
1598 /* clear INTRQ and check if BUSY cleared */
1599 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1602 * With command in flight, we can't do
1603 * sff_irq_clear() w/o racing with completion.
1614 spin_unlock_irqrestore(&host->lock, flags);
1616 return IRQ_RETVAL(handled);
1620 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1621 * @irq: irq line (unused)
1622 * @dev_instance: pointer to our ata_host information structure
1624 * Default interrupt handler for PCI IDE devices. Calls
1625 * ata_sff_port_intr() for each port that is not disabled.
1628 * Obtains host lock during operation.
1631 * IRQ_NONE or IRQ_HANDLED.
1633 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1635 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1637 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1640 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1641 * @ap: port that appears to have timed out
1643 * Called from the libata error handlers when the core code suspects
1644 * an interrupt has been lost. If it has complete anything we can and
1645 * then return. Interface must support altstatus for this faster
1646 * recovery to occur.
1649 * Caller holds host lock
1652 void ata_sff_lost_interrupt(struct ata_port *ap)
1655 struct ata_queued_cmd *qc;
1657 /* Only one outstanding command per SFF channel */
1658 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1659 /* We cannot lose an interrupt on a non-existent or polled command */
1660 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1662 /* See if the controller thinks it is still busy - if so the command
1663 isn't a lost IRQ but is still in progress */
1664 status = ata_sff_altstatus(ap);
1665 if (status & ATA_BUSY)
1668 /* There was a command running, we are no longer busy and we have
1670 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
1672 /* Run the host interrupt logic as if the interrupt had not been
1674 ata_sff_port_intr(ap, qc);
1676 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1679 * ata_sff_freeze - Freeze SFF controller port
1680 * @ap: port to freeze
1682 * Freeze SFF controller port.
1685 * Inherited from caller.
1687 void ata_sff_freeze(struct ata_port *ap)
1689 ap->ctl |= ATA_NIEN;
1690 ap->last_ctl = ap->ctl;
1692 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1693 ata_sff_set_devctl(ap, ap->ctl);
1695 /* Under certain circumstances, some controllers raise IRQ on
1696 * ATA_NIEN manipulation. Also, many controllers fail to mask
1697 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1699 ap->ops->sff_check_status(ap);
1701 if (ap->ops->sff_irq_clear)
1702 ap->ops->sff_irq_clear(ap);
1704 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1707 * ata_sff_thaw - Thaw SFF controller port
1710 * Thaw SFF controller port.
1713 * Inherited from caller.
1715 void ata_sff_thaw(struct ata_port *ap)
1717 /* clear & re-enable interrupts */
1718 ap->ops->sff_check_status(ap);
1719 if (ap->ops->sff_irq_clear)
1720 ap->ops->sff_irq_clear(ap);
1723 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1726 * ata_sff_prereset - prepare SFF link for reset
1727 * @link: SFF link to be reset
1728 * @deadline: deadline jiffies for the operation
1730 * SFF link @link is about to be reset. Initialize it. It first
1731 * calls ata_std_prereset() and wait for !BSY if the port is
1735 * Kernel thread context (may sleep)
1738 * 0 on success, -errno otherwise.
1740 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1742 struct ata_eh_context *ehc = &link->eh_context;
1745 rc = ata_std_prereset(link, deadline);
1749 /* if we're about to do hardreset, nothing more to do */
1750 if (ehc->i.action & ATA_EH_HARDRESET)
1753 /* wait for !BSY if we don't know that no device is attached */
1754 if (!ata_link_offline(link)) {
1755 rc = ata_sff_wait_ready(link, deadline);
1756 if (rc && rc != -ENODEV) {
1758 "device not ready (errno=%d), forcing hardreset\n",
1760 ehc->i.action |= ATA_EH_HARDRESET;
1766 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1769 * ata_devchk - PATA device presence detection
1770 * @ap: ATA channel to examine
1771 * @device: Device to examine (starting at zero)
1773 * This technique was originally described in
1774 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1775 * later found its way into the ATA/ATAPI spec.
1777 * Write a pattern to the ATA shadow registers,
1778 * and if a device is present, it will respond by
1779 * correctly storing and echoing back the
1780 * ATA shadow register contents.
1785 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1787 struct ata_ioports *ioaddr = &ap->ioaddr;
1790 ap->ops->sff_dev_select(ap, device);
1792 iowrite8(0x55, ioaddr->nsect_addr);
1793 iowrite8(0xaa, ioaddr->lbal_addr);
1795 iowrite8(0xaa, ioaddr->nsect_addr);
1796 iowrite8(0x55, ioaddr->lbal_addr);
1798 iowrite8(0x55, ioaddr->nsect_addr);
1799 iowrite8(0xaa, ioaddr->lbal_addr);
1801 nsect = ioread8(ioaddr->nsect_addr);
1802 lbal = ioread8(ioaddr->lbal_addr);
1804 if ((nsect == 0x55) && (lbal == 0xaa))
1805 return 1; /* we found a device */
1807 return 0; /* nothing found */
1811 * ata_sff_dev_classify - Parse returned ATA device signature
1812 * @dev: ATA device to classify (starting at zero)
1813 * @present: device seems present
1814 * @r_err: Value of error register on completion
1816 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1817 * an ATA/ATAPI-defined set of values is placed in the ATA
1818 * shadow registers, indicating the results of device detection
1821 * Select the ATA device, and read the values from the ATA shadow
1822 * registers. Then parse according to the Error register value,
1823 * and the spec-defined values examined by ata_dev_classify().
1829 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1831 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1834 struct ata_port *ap = dev->link->ap;
1835 struct ata_taskfile tf;
1839 ap->ops->sff_dev_select(ap, dev->devno);
1841 memset(&tf, 0, sizeof(tf));
1843 ap->ops->sff_tf_read(ap, &tf);
1848 /* see if device passed diags: continue and warn later */
1850 /* diagnostic fail : do nothing _YET_ */
1851 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1854 else if ((dev->devno == 0) && (err == 0x81))
1857 return ATA_DEV_NONE;
1859 /* determine if device is ATA or ATAPI */
1860 class = ata_dev_classify(&tf);
1862 if (class == ATA_DEV_UNKNOWN) {
1863 /* If the device failed diagnostic, it's likely to
1864 * have reported incorrect device signature too.
1865 * Assume ATA device if the device seems present but
1866 * device signature is invalid with diagnostic
1869 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1870 class = ATA_DEV_ATA;
1872 class = ATA_DEV_NONE;
1873 } else if ((class == ATA_DEV_ATA) &&
1874 (ap->ops->sff_check_status(ap) == 0))
1875 class = ATA_DEV_NONE;
1879 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1882 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1883 * @link: SFF link which is just reset
1884 * @devmask: mask of present devices
1885 * @deadline: deadline jiffies for the operation
1887 * Wait devices attached to SFF @link to become ready after
1888 * reset. It contains preceding 150ms wait to avoid accessing TF
1889 * status register too early.
1892 * Kernel thread context (may sleep).
1895 * 0 on success, -ENODEV if some or all of devices in @devmask
1896 * don't seem to exist. -errno on other errors.
1898 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1899 unsigned long deadline)
1901 struct ata_port *ap = link->ap;
1902 struct ata_ioports *ioaddr = &ap->ioaddr;
1903 unsigned int dev0 = devmask & (1 << 0);
1904 unsigned int dev1 = devmask & (1 << 1);
1907 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1909 /* always check readiness of the master device */
1910 rc = ata_sff_wait_ready(link, deadline);
1911 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1912 * and TF status is 0xff, bail out on it too.
1917 /* if device 1 was found in ata_devchk, wait for register
1918 * access briefly, then wait for BSY to clear.
1923 ap->ops->sff_dev_select(ap, 1);
1925 /* Wait for register access. Some ATAPI devices fail
1926 * to set nsect/lbal after reset, so don't waste too
1927 * much time on it. We're gonna wait for !BSY anyway.
1929 for (i = 0; i < 2; i++) {
1932 nsect = ioread8(ioaddr->nsect_addr);
1933 lbal = ioread8(ioaddr->lbal_addr);
1934 if ((nsect == 1) && (lbal == 1))
1936 ata_msleep(ap, 50); /* give drive a breather */
1939 rc = ata_sff_wait_ready(link, deadline);
1947 /* is all this really necessary? */
1948 ap->ops->sff_dev_select(ap, 0);
1950 ap->ops->sff_dev_select(ap, 1);
1952 ap->ops->sff_dev_select(ap, 0);
1956 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
1958 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1959 unsigned long deadline)
1961 struct ata_ioports *ioaddr = &ap->ioaddr;
1963 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1965 if (ap->ioaddr.ctl_addr) {
1966 /* software reset. causes dev0 to be selected */
1967 iowrite8(ap->ctl, ioaddr->ctl_addr);
1968 udelay(20); /* FIXME: flush */
1969 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1970 udelay(20); /* FIXME: flush */
1971 iowrite8(ap->ctl, ioaddr->ctl_addr);
1972 ap->last_ctl = ap->ctl;
1975 /* wait the port to become ready */
1976 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1980 * ata_sff_softreset - reset host port via ATA SRST
1981 * @link: ATA link to reset
1982 * @classes: resulting classes of attached devices
1983 * @deadline: deadline jiffies for the operation
1985 * Reset host port using ATA SRST.
1988 * Kernel thread context (may sleep)
1991 * 0 on success, -errno otherwise.
1993 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1994 unsigned long deadline)
1996 struct ata_port *ap = link->ap;
1997 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1998 unsigned int devmask = 0;
2004 /* determine if device 0/1 are present */
2005 if (ata_devchk(ap, 0))
2006 devmask |= (1 << 0);
2007 if (slave_possible && ata_devchk(ap, 1))
2008 devmask |= (1 << 1);
2010 /* select device 0 again */
2011 ap->ops->sff_dev_select(ap, 0);
2013 /* issue bus reset */
2014 DPRINTK("about to softreset, devmask=%x\n", devmask);
2015 rc = ata_bus_softreset(ap, devmask, deadline);
2016 /* if link is occupied, -ENODEV too is an error */
2017 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2018 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
2022 /* determine by signature whether we have ATA or ATAPI devices */
2023 classes[0] = ata_sff_dev_classify(&link->device[0],
2024 devmask & (1 << 0), &err);
2025 if (slave_possible && err != 0x81)
2026 classes[1] = ata_sff_dev_classify(&link->device[1],
2027 devmask & (1 << 1), &err);
2029 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2032 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2035 * sata_sff_hardreset - reset host port via SATA phy reset
2036 * @link: link to reset
2037 * @class: resulting class of attached device
2038 * @deadline: deadline jiffies for the operation
2040 * SATA phy-reset host port using DET bits of SControl register,
2041 * wait for !BSY and classify the attached device.
2044 * Kernel thread context (may sleep)
2047 * 0 on success, -errno otherwise.
2049 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2050 unsigned long deadline)
2052 struct ata_eh_context *ehc = &link->eh_context;
2053 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2057 rc = sata_link_hardreset(link, timing, deadline, &online,
2058 ata_sff_check_ready);
2060 *class = ata_sff_dev_classify(link->device, 1, NULL);
2062 DPRINTK("EXIT, class=%u\n", *class);
2065 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2068 * ata_sff_postreset - SFF postreset callback
2069 * @link: the target SFF ata_link
2070 * @classes: classes of attached devices
2072 * This function is invoked after a successful reset. It first
2073 * calls ata_std_postreset() and performs SFF specific postreset
2077 * Kernel thread context (may sleep)
2079 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2081 struct ata_port *ap = link->ap;
2083 ata_std_postreset(link, classes);
2085 /* is double-select really necessary? */
2086 if (classes[0] != ATA_DEV_NONE)
2087 ap->ops->sff_dev_select(ap, 1);
2088 if (classes[1] != ATA_DEV_NONE)
2089 ap->ops->sff_dev_select(ap, 0);
2091 /* bail out if no device is present */
2092 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2093 DPRINTK("EXIT, no device\n");
2097 /* set up device control */
2098 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2099 ata_sff_set_devctl(ap, ap->ctl);
2100 ap->last_ctl = ap->ctl;
2103 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2106 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2109 * Drain the FIFO and device of any stuck data following a command
2110 * failing to complete. In some cases this is necessary before a
2111 * reset will recover the device.
2115 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2118 struct ata_port *ap;
2120 /* We only need to flush incoming data when a command was running */
2121 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2125 /* Drain up to 64K of data before we give up this recovery method */
2126 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2127 && count < 65536; count += 2)
2128 ioread16(ap->ioaddr.data_addr);
2130 /* Can become DEBUG later */
2132 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2135 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2138 * ata_sff_error_handler - Stock error handler for SFF controller
2139 * @ap: port to handle error for
2141 * Stock error handler for SFF controller. It can handle both
2142 * PATA and SATA controllers. Many controllers should be able to
2143 * use this EH as-is or with some added handling before and
2147 * Kernel thread context (may sleep)
2149 void ata_sff_error_handler(struct ata_port *ap)
2151 ata_reset_fn_t softreset = ap->ops->softreset;
2152 ata_reset_fn_t hardreset = ap->ops->hardreset;
2153 struct ata_queued_cmd *qc;
2154 unsigned long flags;
2156 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2157 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2160 spin_lock_irqsave(ap->lock, flags);
2163 * We *MUST* do FIFO draining before we issue a reset as
2164 * several devices helpfully clear their internal state and
2165 * will lock solid if we touch the data port post reset. Pass
2166 * qc in case anyone wants to do different PIO/DMA recovery or
2167 * has per command fixups
2169 if (ap->ops->sff_drain_fifo)
2170 ap->ops->sff_drain_fifo(qc);
2172 spin_unlock_irqrestore(ap->lock, flags);
2174 /* ignore built-in hardresets if SCR access is not available */
2175 if ((hardreset == sata_std_hardreset ||
2176 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2179 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2180 ap->ops->postreset);
2182 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2185 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2186 * @ioaddr: IO address structure to be initialized
2188 * Utility function which initializes data_addr, error_addr,
2189 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2190 * device_addr, status_addr, and command_addr to standard offsets
2191 * relative to cmd_addr.
2193 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2195 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2197 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2198 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2199 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2200 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2201 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2202 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2203 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2204 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2205 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2206 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2208 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2212 static int ata_resources_present(struct pci_dev *pdev, int port)
2216 /* Check the PCI resources for this channel are enabled */
2218 for (i = 0; i < 2; i++) {
2219 if (pci_resource_start(pdev, port + i) == 0 ||
2220 pci_resource_len(pdev, port + i) == 0)
2227 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2228 * @host: target ATA host
2230 * Acquire native PCI ATA resources for @host and initialize the
2231 * first two ports of @host accordingly. Ports marked dummy are
2232 * skipped and allocation failure makes the port dummy.
2234 * Note that native PCI resources are valid even for legacy hosts
2235 * as we fix up pdev resources array early in boot, so this
2236 * function can be used for both native and legacy SFF hosts.
2239 * Inherited from calling layer (may sleep).
2242 * 0 if at least one port is initialized, -ENODEV if no port is
2245 int ata_pci_sff_init_host(struct ata_host *host)
2247 struct device *gdev = host->dev;
2248 struct pci_dev *pdev = to_pci_dev(gdev);
2249 unsigned int mask = 0;
2252 /* request, iomap BARs and init port addresses accordingly */
2253 for (i = 0; i < 2; i++) {
2254 struct ata_port *ap = host->ports[i];
2256 void __iomem * const *iomap;
2258 if (ata_port_is_dummy(ap))
2261 /* Discard disabled ports. Some controllers show
2262 * their unused channels this way. Disabled ports are
2265 if (!ata_resources_present(pdev, i)) {
2266 ap->ops = &ata_dummy_port_ops;
2270 rc = pcim_iomap_regions(pdev, 0x3 << base,
2271 dev_driver_string(gdev));
2274 "failed to request/iomap BARs for port %d (errno=%d)\n",
2277 pcim_pin_device(pdev);
2278 ap->ops = &ata_dummy_port_ops;
2281 host->iomap = iomap = pcim_iomap_table(pdev);
2283 ap->ioaddr.cmd_addr = iomap[base];
2284 ap->ioaddr.altstatus_addr =
2285 ap->ioaddr.ctl_addr = (void __iomem *)
2286 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2287 ata_sff_std_ports(&ap->ioaddr);
2289 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2290 (unsigned long long)pci_resource_start(pdev, base),
2291 (unsigned long long)pci_resource_start(pdev, base + 1));
2297 dev_err(gdev, "no available native port\n");
2303 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2306 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2307 * @pdev: target PCI device
2308 * @ppi: array of port_info, must be enough for two ports
2309 * @r_host: out argument for the initialized ATA host
2311 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2312 * all PCI resources and initialize it accordingly in one go.
2315 * Inherited from calling layer (may sleep).
2318 * 0 on success, -errno otherwise.
2320 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2321 const struct ata_port_info * const *ppi,
2322 struct ata_host **r_host)
2324 struct ata_host *host;
2327 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2330 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2332 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2337 rc = ata_pci_sff_init_host(host);
2341 devres_remove_group(&pdev->dev, NULL);
2346 devres_release_group(&pdev->dev, NULL);
2349 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2352 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2353 * @host: target SFF ATA host
2354 * @irq_handler: irq_handler used when requesting IRQ(s)
2355 * @sht: scsi_host_template to use when registering the host
2357 * This is the counterpart of ata_host_activate() for SFF ATA
2358 * hosts. This separate helper is necessary because SFF hosts
2359 * use two separate interrupts in legacy mode.
2362 * Inherited from calling layer (may sleep).
2365 * 0 on success, -errno otherwise.
2367 int ata_pci_sff_activate_host(struct ata_host *host,
2368 irq_handler_t irq_handler,
2369 struct scsi_host_template *sht)
2371 struct device *dev = host->dev;
2372 struct pci_dev *pdev = to_pci_dev(dev);
2373 const char *drv_name = dev_driver_string(host->dev);
2374 int legacy_mode = 0, rc;
2376 rc = ata_host_start(host);
2380 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2384 * ATA spec says we should use legacy mode when one
2385 * port is in legacy mode, but disabled ports on some
2386 * PCI hosts appear as fixed legacy ports, e.g SB600/700
2387 * on which the secondary port is not wired, so
2388 * ignore ports that are marked as 'dummy' during
2391 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2392 if (!ata_port_is_dummy(host->ports[0]))
2394 if (!ata_port_is_dummy(host->ports[1]))
2396 if ((tmp8 & mask) != mask)
2400 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2403 if (!legacy_mode && pdev->irq) {
2406 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2407 IRQF_SHARED, drv_name, host);
2411 for (i = 0; i < 2; i++) {
2412 if (ata_port_is_dummy(host->ports[i]))
2414 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2416 } else if (legacy_mode) {
2417 if (!ata_port_is_dummy(host->ports[0])) {
2418 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2419 irq_handler, IRQF_SHARED,
2424 ata_port_desc(host->ports[0], "irq %d",
2425 ATA_PRIMARY_IRQ(pdev));
2428 if (!ata_port_is_dummy(host->ports[1])) {
2429 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2430 irq_handler, IRQF_SHARED,
2435 ata_port_desc(host->ports[1], "irq %d",
2436 ATA_SECONDARY_IRQ(pdev));
2440 rc = ata_host_register(host, sht);
2443 devres_remove_group(dev, NULL);
2445 devres_release_group(dev, NULL);
2449 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2451 static const struct ata_port_info *ata_sff_find_valid_pi(
2452 const struct ata_port_info * const *ppi)
2456 /* look up the first valid port_info */
2457 for (i = 0; i < 2 && ppi[i]; i++)
2458 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2464 static int ata_pci_init_one(struct pci_dev *pdev,
2465 const struct ata_port_info * const *ppi,
2466 struct scsi_host_template *sht, void *host_priv,
2467 int hflags, bool bmdma)
2469 struct device *dev = &pdev->dev;
2470 const struct ata_port_info *pi;
2471 struct ata_host *host = NULL;
2476 pi = ata_sff_find_valid_pi(ppi);
2478 dev_err(&pdev->dev, "no valid port_info specified\n");
2482 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2485 rc = pcim_enable_device(pdev);
2489 #ifdef CONFIG_ATA_BMDMA
2491 /* prepare and activate BMDMA host */
2492 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2495 /* prepare and activate SFF host */
2496 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2499 host->private_data = host_priv;
2500 host->flags |= hflags;
2502 #ifdef CONFIG_ATA_BMDMA
2504 pci_set_master(pdev);
2505 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2508 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2511 devres_remove_group(&pdev->dev, NULL);
2513 devres_release_group(&pdev->dev, NULL);
2519 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2520 * @pdev: Controller to be initialized
2521 * @ppi: array of port_info, must be enough for two ports
2522 * @sht: scsi_host_template to use when registering the host
2523 * @host_priv: host private_data
2524 * @hflag: host flags
2526 * This is a helper function which can be called from a driver's
2527 * xxx_init_one() probe function if the hardware uses traditional
2528 * IDE taskfile registers and is PIO only.
2531 * Nobody makes a single channel controller that appears solely as
2532 * the secondary legacy port on PCI.
2535 * Inherited from PCI layer (may sleep).
2538 * Zero on success, negative on errno-based value on error.
2540 int ata_pci_sff_init_one(struct pci_dev *pdev,
2541 const struct ata_port_info * const *ppi,
2542 struct scsi_host_template *sht, void *host_priv, int hflag)
2544 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2546 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2548 #endif /* CONFIG_PCI */
2554 #ifdef CONFIG_ATA_BMDMA
2556 const struct ata_port_operations ata_bmdma_port_ops = {
2557 .inherits = &ata_sff_port_ops,
2559 .error_handler = ata_bmdma_error_handler,
2560 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2562 .qc_prep = ata_bmdma_qc_prep,
2563 .qc_issue = ata_bmdma_qc_issue,
2565 .sff_irq_clear = ata_bmdma_irq_clear,
2566 .bmdma_setup = ata_bmdma_setup,
2567 .bmdma_start = ata_bmdma_start,
2568 .bmdma_stop = ata_bmdma_stop,
2569 .bmdma_status = ata_bmdma_status,
2571 .port_start = ata_bmdma_port_start,
2573 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2575 const struct ata_port_operations ata_bmdma32_port_ops = {
2576 .inherits = &ata_bmdma_port_ops,
2578 .sff_data_xfer = ata_sff_data_xfer32,
2579 .port_start = ata_bmdma_port_start32,
2581 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2584 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2585 * @qc: Metadata associated with taskfile to be transferred
2587 * Fill PCI IDE PRD (scatter-gather) table with segments
2588 * associated with the current disk command.
2591 * spin_lock_irqsave(host lock)
2594 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2596 struct ata_port *ap = qc->ap;
2597 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2598 struct scatterlist *sg;
2599 unsigned int si, pi;
2602 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2606 /* determine if physical DMA addr spans 64K boundary.
2607 * Note h/w doesn't support 64-bit, so we unconditionally
2608 * truncate dma_addr_t to u32.
2610 addr = (u32) sg_dma_address(sg);
2611 sg_len = sg_dma_len(sg);
2614 offset = addr & 0xffff;
2616 if ((offset + sg_len) > 0x10000)
2617 len = 0x10000 - offset;
2619 prd[pi].addr = cpu_to_le32(addr);
2620 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2621 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2629 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2633 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2634 * @qc: Metadata associated with taskfile to be transferred
2636 * Fill PCI IDE PRD (scatter-gather) table with segments
2637 * associated with the current disk command. Perform the fill
2638 * so that we avoid writing any length 64K records for
2639 * controllers that don't follow the spec.
2642 * spin_lock_irqsave(host lock)
2645 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2647 struct ata_port *ap = qc->ap;
2648 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2649 struct scatterlist *sg;
2650 unsigned int si, pi;
2653 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2655 u32 sg_len, len, blen;
2657 /* determine if physical DMA addr spans 64K boundary.
2658 * Note h/w doesn't support 64-bit, so we unconditionally
2659 * truncate dma_addr_t to u32.
2661 addr = (u32) sg_dma_address(sg);
2662 sg_len = sg_dma_len(sg);
2665 offset = addr & 0xffff;
2667 if ((offset + sg_len) > 0x10000)
2668 len = 0x10000 - offset;
2670 blen = len & 0xffff;
2671 prd[pi].addr = cpu_to_le32(addr);
2673 /* Some PATA chipsets like the CS5530 can't
2674 cope with 0x0000 meaning 64K as the spec
2676 prd[pi].flags_len = cpu_to_le32(0x8000);
2678 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2680 prd[pi].flags_len = cpu_to_le32(blen);
2681 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2689 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2693 * ata_bmdma_qc_prep - Prepare taskfile for submission
2694 * @qc: Metadata associated with taskfile to be prepared
2696 * Prepare ATA taskfile for submission.
2699 * spin_lock_irqsave(host lock)
2701 enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2703 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2706 ata_bmdma_fill_sg(qc);
2710 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2713 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2714 * @qc: Metadata associated with taskfile to be prepared
2716 * Prepare ATA taskfile for submission.
2719 * spin_lock_irqsave(host lock)
2721 enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2723 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2726 ata_bmdma_fill_sg_dumb(qc);
2730 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2733 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2734 * @qc: command to issue to device
2736 * This function issues a PIO, NODATA or DMA command to a
2737 * SFF/BMDMA controller. PIO and NODATA are handled by
2738 * ata_sff_qc_issue().
2741 * spin_lock_irqsave(host lock)
2744 * Zero on success, AC_ERR_* mask on failure
2746 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2748 struct ata_port *ap = qc->ap;
2749 struct ata_link *link = qc->dev->link;
2751 /* defer PIO handling to sff_qc_issue */
2752 if (!ata_is_dma(qc->tf.protocol))
2753 return ata_sff_qc_issue(qc);
2755 /* select the device */
2756 ata_dev_select(ap, qc->dev->devno, 1, 0);
2758 /* start the command */
2759 switch (qc->tf.protocol) {
2761 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2763 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2764 ap->ops->bmdma_setup(qc); /* set up bmdma */
2765 ap->ops->bmdma_start(qc); /* initiate bmdma */
2766 ap->hsm_task_state = HSM_ST_LAST;
2769 case ATAPI_PROT_DMA:
2770 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2772 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2773 ap->ops->bmdma_setup(qc); /* set up bmdma */
2774 ap->hsm_task_state = HSM_ST_FIRST;
2776 /* send cdb by polling if no cdb interrupt */
2777 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2778 ata_sff_queue_pio_task(link, 0);
2783 return AC_ERR_SYSTEM;
2788 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2791 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2792 * @ap: Port on which interrupt arrived (possibly...)
2793 * @qc: Taskfile currently active in engine
2795 * Handle port interrupt for given queued command.
2798 * spin_lock_irqsave(host lock)
2801 * One if interrupt was handled, zero if not (shared irq).
2803 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2805 struct ata_eh_info *ehi = &ap->link.eh_info;
2807 bool bmdma_stopped = false;
2808 unsigned int handled;
2810 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2811 /* check status of DMA engine */
2812 host_stat = ap->ops->bmdma_status(ap);
2813 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2815 /* if it's not our irq... */
2816 if (!(host_stat & ATA_DMA_INTR))
2817 return ata_sff_idle_irq(ap);
2819 /* before we do anything else, clear DMA-Start bit */
2820 ap->ops->bmdma_stop(qc);
2821 bmdma_stopped = true;
2823 if (unlikely(host_stat & ATA_DMA_ERR)) {
2824 /* error when transferring data to/from memory */
2825 qc->err_mask |= AC_ERR_HOST_BUS;
2826 ap->hsm_task_state = HSM_ST_ERR;
2830 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2832 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2833 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2837 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2840 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2841 * @irq: irq line (unused)
2842 * @dev_instance: pointer to our ata_host information structure
2844 * Default interrupt handler for PCI IDE devices. Calls
2845 * ata_bmdma_port_intr() for each port that is not disabled.
2848 * Obtains host lock during operation.
2851 * IRQ_NONE or IRQ_HANDLED.
2853 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2855 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2857 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2860 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2861 * @ap: port to handle error for
2863 * Stock error handler for BMDMA controller. It can handle both
2864 * PATA and SATA controllers. Most BMDMA controllers should be
2865 * able to use this EH as-is or with some added handling before
2869 * Kernel thread context (may sleep)
2871 void ata_bmdma_error_handler(struct ata_port *ap)
2873 struct ata_queued_cmd *qc;
2874 unsigned long flags;
2877 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2878 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2881 /* reset PIO HSM and stop DMA engine */
2882 spin_lock_irqsave(ap->lock, flags);
2884 if (qc && ata_is_dma(qc->tf.protocol)) {
2887 host_stat = ap->ops->bmdma_status(ap);
2889 /* BMDMA controllers indicate host bus error by
2890 * setting DMA_ERR bit and timing out. As it wasn't
2891 * really a timeout event, adjust error mask and
2892 * cancel frozen state.
2894 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2895 qc->err_mask = AC_ERR_HOST_BUS;
2899 ap->ops->bmdma_stop(qc);
2901 /* if we're gonna thaw, make sure IRQ is clear */
2903 ap->ops->sff_check_status(ap);
2904 if (ap->ops->sff_irq_clear)
2905 ap->ops->sff_irq_clear(ap);
2909 spin_unlock_irqrestore(ap->lock, flags);
2912 ata_eh_thaw_port(ap);
2914 ata_sff_error_handler(ap);
2916 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2919 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2920 * @qc: internal command to clean up
2923 * Kernel thread context (may sleep)
2925 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2927 struct ata_port *ap = qc->ap;
2928 unsigned long flags;
2930 if (ata_is_dma(qc->tf.protocol)) {
2931 spin_lock_irqsave(ap->lock, flags);
2932 ap->ops->bmdma_stop(qc);
2933 spin_unlock_irqrestore(ap->lock, flags);
2936 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2939 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2940 * @ap: Port associated with this ATA transaction.
2942 * Clear interrupt and error flags in DMA status register.
2944 * May be used as the irq_clear() entry in ata_port_operations.
2947 * spin_lock_irqsave(host lock)
2949 void ata_bmdma_irq_clear(struct ata_port *ap)
2951 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2956 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2958 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2961 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2962 * @qc: Info associated with this ATA transaction.
2965 * spin_lock_irqsave(host lock)
2967 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2969 struct ata_port *ap = qc->ap;
2970 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2973 /* load PRD table addr. */
2974 mb(); /* make sure PRD table writes are visible to controller */
2975 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2977 /* specify data direction, triple-check start bit is clear */
2978 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2979 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2981 dmactl |= ATA_DMA_WR;
2982 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2984 /* issue r/w command */
2985 ap->ops->sff_exec_command(ap, &qc->tf);
2987 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2990 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2991 * @qc: Info associated with this ATA transaction.
2994 * spin_lock_irqsave(host lock)
2996 void ata_bmdma_start(struct ata_queued_cmd *qc)
2998 struct ata_port *ap = qc->ap;
3001 /* start host DMA transaction */
3002 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3003 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3005 /* Strictly, one may wish to issue an ioread8() here, to
3006 * flush the mmio write. However, control also passes
3007 * to the hardware at this point, and it will interrupt
3008 * us when we are to resume control. So, in effect,
3009 * we don't care when the mmio write flushes.
3010 * Further, a read of the DMA status register _immediately_
3011 * following the write may not be what certain flaky hardware
3012 * is expected, so I think it is best to not add a readb()
3013 * without first all the MMIO ATA cards/mobos.
3014 * Or maybe I'm just being paranoid.
3016 * FIXME: The posting of this write means I/O starts are
3017 * unnecessarily delayed for MMIO
3020 EXPORT_SYMBOL_GPL(ata_bmdma_start);
3023 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3024 * @qc: Command we are ending DMA for
3026 * Clears the ATA_DMA_START flag in the dma control register
3028 * May be used as the bmdma_stop() entry in ata_port_operations.
3031 * spin_lock_irqsave(host lock)
3033 void ata_bmdma_stop(struct ata_queued_cmd *qc)
3035 struct ata_port *ap = qc->ap;
3036 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3038 /* clear start/stop bit */
3039 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3040 mmio + ATA_DMA_CMD);
3042 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3043 ata_sff_dma_pause(ap);
3045 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3048 * ata_bmdma_status - Read PCI IDE BMDMA status
3049 * @ap: Port associated with this ATA transaction.
3051 * Read and return BMDMA status register.
3053 * May be used as the bmdma_status() entry in ata_port_operations.
3056 * spin_lock_irqsave(host lock)
3058 u8 ata_bmdma_status(struct ata_port *ap)
3060 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3062 EXPORT_SYMBOL_GPL(ata_bmdma_status);
3066 * ata_bmdma_port_start - Set port up for bmdma.
3067 * @ap: Port to initialize
3069 * Called just after data structures for each port are
3070 * initialized. Allocates space for PRD table.
3072 * May be used as the port_start() entry in ata_port_operations.
3075 * Inherited from caller.
3077 int ata_bmdma_port_start(struct ata_port *ap)
3079 if (ap->mwdma_mask || ap->udma_mask) {
3081 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3082 &ap->bmdma_prd_dma, GFP_KERNEL);
3089 EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3092 * ata_bmdma_port_start32 - Set port up for dma.
3093 * @ap: Port to initialize
3095 * Called just after data structures for each port are
3096 * initialized. Enables 32bit PIO and allocates space for PRD
3099 * May be used as the port_start() entry in ata_port_operations for
3100 * devices that are capable of 32bit PIO.
3103 * Inherited from caller.
3105 int ata_bmdma_port_start32(struct ata_port *ap)
3107 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3108 return ata_bmdma_port_start(ap);
3110 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3115 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3118 * Some PCI ATA devices report simplex mode but in fact can be told to
3119 * enter non simplex mode. This implements the necessary logic to
3120 * perform the task on such devices. Calling it on other devices will
3121 * have -undefined- behaviour.
3123 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3125 unsigned long bmdma = pci_resource_start(pdev, 4);
3131 simplex = inb(bmdma + 0x02);
3132 outb(simplex & 0x60, bmdma + 0x02);
3133 simplex = inb(bmdma + 0x02);
3138 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3140 static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3144 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3146 for (i = 0; i < 2; i++) {
3147 host->ports[i]->mwdma_mask = 0;
3148 host->ports[i]->udma_mask = 0;
3153 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3154 * @host: target ATA host
3156 * Acquire PCI BMDMA resources and initialize @host accordingly.
3159 * Inherited from calling layer (may sleep).
3161 void ata_pci_bmdma_init(struct ata_host *host)
3163 struct device *gdev = host->dev;
3164 struct pci_dev *pdev = to_pci_dev(gdev);
3167 /* No BAR4 allocation: No DMA */
3168 if (pci_resource_start(pdev, 4) == 0) {
3169 ata_bmdma_nodma(host, "BAR4 is zero");
3174 * Some controllers require BMDMA region to be initialized
3175 * even if DMA is not in use to clear IRQ status via
3176 * ->sff_irq_clear method. Try to initialize bmdma_addr
3177 * regardless of dma masks.
3179 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
3181 ata_bmdma_nodma(host, "failed to set dma mask");
3183 /* request and iomap DMA region */
3184 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3186 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3189 host->iomap = pcim_iomap_table(pdev);
3191 for (i = 0; i < 2; i++) {
3192 struct ata_port *ap = host->ports[i];
3193 void __iomem *bmdma = host->iomap[4] + 8 * i;
3195 if (ata_port_is_dummy(ap))
3198 ap->ioaddr.bmdma_addr = bmdma;
3199 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3200 (ioread8(bmdma + 2) & 0x80))
3201 host->flags |= ATA_HOST_SIMPLEX;
3203 ata_port_desc(ap, "bmdma 0x%llx",
3204 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3207 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3210 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3211 * @pdev: target PCI device
3212 * @ppi: array of port_info, must be enough for two ports
3213 * @r_host: out argument for the initialized ATA host
3215 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3216 * resources and initialize it accordingly in one go.
3219 * Inherited from calling layer (may sleep).
3222 * 0 on success, -errno otherwise.
3224 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3225 const struct ata_port_info * const * ppi,
3226 struct ata_host **r_host)
3230 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3234 ata_pci_bmdma_init(*r_host);
3237 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3240 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3241 * @pdev: Controller to be initialized
3242 * @ppi: array of port_info, must be enough for two ports
3243 * @sht: scsi_host_template to use when registering the host
3244 * @host_priv: host private_data
3245 * @hflags: host flags
3247 * This function is similar to ata_pci_sff_init_one() but also
3248 * takes care of BMDMA initialization.
3251 * Inherited from PCI layer (may sleep).
3254 * Zero on success, negative on errno-based value on error.
3256 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3257 const struct ata_port_info * const * ppi,
3258 struct scsi_host_template *sht, void *host_priv,
3261 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3263 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3265 #endif /* CONFIG_PCI */
3266 #endif /* CONFIG_ATA_BMDMA */
3269 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3270 * @ap: Port to initialize
3272 * Called on port allocation to initialize SFF/BMDMA specific
3278 void ata_sff_port_init(struct ata_port *ap)
3280 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3281 ap->ctl = ATA_DEVCTL_OBS;
3282 ap->last_ctl = 0xFF;
3285 int __init ata_sff_init(void)
3287 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3294 void ata_sff_exit(void)
3296 destroy_workqueue(ata_sff_wq);