2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/pci.h>
38 #include <linux/module.h>
39 #include <linux/libata.h>
40 #include <linux/highmem.h>
44 static struct workqueue_struct *ata_sff_wq;
46 const struct ata_port_operations ata_sff_port_ops = {
47 .inherits = &ata_base_port_ops,
49 .qc_prep = ata_noop_qc_prep,
50 .qc_issue = ata_sff_qc_issue,
51 .qc_fill_rtf = ata_sff_qc_fill_rtf,
53 .freeze = ata_sff_freeze,
55 .prereset = ata_sff_prereset,
56 .softreset = ata_sff_softreset,
57 .hardreset = sata_sff_hardreset,
58 .postreset = ata_sff_postreset,
59 .error_handler = ata_sff_error_handler,
61 .sff_dev_select = ata_sff_dev_select,
62 .sff_check_status = ata_sff_check_status,
63 .sff_tf_load = ata_sff_tf_load,
64 .sff_tf_read = ata_sff_tf_read,
65 .sff_exec_command = ata_sff_exec_command,
66 .sff_data_xfer = ata_sff_data_xfer,
67 .sff_drain_fifo = ata_sff_drain_fifo,
69 .lost_interrupt = ata_sff_lost_interrupt,
71 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
74 * ata_sff_check_status - Read device status reg & clear interrupt
75 * @ap: port where the device is
77 * Reads ATA taskfile status register for currently-selected device
78 * and return its value. This also clears pending interrupts
82 * Inherited from caller.
84 u8 ata_sff_check_status(struct ata_port *ap)
86 return ioread8(ap->ioaddr.status_addr);
88 EXPORT_SYMBOL_GPL(ata_sff_check_status);
91 * ata_sff_altstatus - Read device alternate status reg
92 * @ap: port where the device is
94 * Reads ATA taskfile alternate status register for
95 * currently-selected device and return its value.
97 * Note: may NOT be used as the check_altstatus() entry in
98 * ata_port_operations.
101 * Inherited from caller.
103 static u8 ata_sff_altstatus(struct ata_port *ap)
105 if (ap->ops->sff_check_altstatus)
106 return ap->ops->sff_check_altstatus(ap);
108 return ioread8(ap->ioaddr.altstatus_addr);
112 * ata_sff_irq_status - Check if the device is busy
113 * @ap: port where the device is
115 * Determine if the port is currently busy. Uses altstatus
116 * if available in order to avoid clearing shared IRQ status
117 * when finding an IRQ source. Non ctl capable devices don't
118 * share interrupt lines fortunately for us.
121 * Inherited from caller.
123 static u8 ata_sff_irq_status(struct ata_port *ap)
127 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
128 status = ata_sff_altstatus(ap);
129 /* Not us: We are busy */
130 if (status & ATA_BUSY)
133 /* Clear INTRQ latch */
134 status = ap->ops->sff_check_status(ap);
139 * ata_sff_sync - Flush writes
140 * @ap: Port to wait for.
143 * If we have an mmio device with no ctl and no altstatus
144 * method this will fail. No such devices are known to exist.
147 * Inherited from caller.
150 static void ata_sff_sync(struct ata_port *ap)
152 if (ap->ops->sff_check_altstatus)
153 ap->ops->sff_check_altstatus(ap);
154 else if (ap->ioaddr.altstatus_addr)
155 ioread8(ap->ioaddr.altstatus_addr);
159 * ata_sff_pause - Flush writes and wait 400nS
160 * @ap: Port to pause for.
163 * If we have an mmio device with no ctl and no altstatus
164 * method this will fail. No such devices are known to exist.
167 * Inherited from caller.
170 void ata_sff_pause(struct ata_port *ap)
175 EXPORT_SYMBOL_GPL(ata_sff_pause);
178 * ata_sff_dma_pause - Pause before commencing DMA
179 * @ap: Port to pause for.
181 * Perform I/O fencing and ensure sufficient cycle delays occur
182 * for the HDMA1:0 transition
185 void ata_sff_dma_pause(struct ata_port *ap)
187 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
188 /* An altstatus read will cause the needed delay without
189 messing up the IRQ status */
190 ata_sff_altstatus(ap);
193 /* There are no DMA controllers without ctl. BUG here to ensure
194 we never violate the HDMA1:0 transition timing and risk
198 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
201 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
202 * @ap: port containing status register to be polled
203 * @tmout_pat: impatience timeout in msecs
204 * @tmout: overall timeout in msecs
206 * Sleep until ATA Status register bit BSY clears,
207 * or a timeout occurs.
210 * Kernel thread context (may sleep).
213 * 0 on success, -errno otherwise.
215 int ata_sff_busy_sleep(struct ata_port *ap,
216 unsigned long tmout_pat, unsigned long tmout)
218 unsigned long timer_start, timeout;
221 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
222 timer_start = jiffies;
223 timeout = ata_deadline(timer_start, tmout_pat);
224 while (status != 0xff && (status & ATA_BUSY) &&
225 time_before(jiffies, timeout)) {
227 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
230 if (status != 0xff && (status & ATA_BUSY))
232 "port is slow to respond, please be patient (Status 0x%x)\n",
235 timeout = ata_deadline(timer_start, tmout);
236 while (status != 0xff && (status & ATA_BUSY) &&
237 time_before(jiffies, timeout)) {
239 status = ap->ops->sff_check_status(ap);
245 if (status & ATA_BUSY) {
247 "port failed to respond (%lu secs, Status 0x%x)\n",
248 DIV_ROUND_UP(tmout, 1000), status);
254 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
256 static int ata_sff_check_ready(struct ata_link *link)
258 u8 status = link->ap->ops->sff_check_status(link->ap);
260 return ata_check_ready(status);
264 * ata_sff_wait_ready - sleep until BSY clears, or timeout
265 * @link: SFF link to wait ready status for
266 * @deadline: deadline jiffies for the operation
268 * Sleep until ATA Status register bit BSY clears, or timeout
272 * Kernel thread context (may sleep).
275 * 0 on success, -errno otherwise.
277 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
279 return ata_wait_ready(link, deadline, ata_sff_check_ready);
281 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
284 * ata_sff_set_devctl - Write device control reg
285 * @ap: port where the device is
286 * @ctl: value to write
288 * Writes ATA taskfile device control register.
290 * Note: may NOT be used as the sff_set_devctl() entry in
291 * ata_port_operations.
294 * Inherited from caller.
296 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
298 if (ap->ops->sff_set_devctl)
299 ap->ops->sff_set_devctl(ap, ctl);
301 iowrite8(ctl, ap->ioaddr.ctl_addr);
305 * ata_sff_dev_select - Select device 0/1 on ATA bus
306 * @ap: ATA channel to manipulate
307 * @device: ATA device (numbered from zero) to select
309 * Use the method defined in the ATA specification to
310 * make either device 0, or device 1, active on the
311 * ATA channel. Works with both PIO and MMIO.
313 * May be used as the dev_select() entry in ata_port_operations.
318 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
323 tmp = ATA_DEVICE_OBS;
325 tmp = ATA_DEVICE_OBS | ATA_DEV1;
327 iowrite8(tmp, ap->ioaddr.device_addr);
328 ata_sff_pause(ap); /* needed; also flushes, for mmio */
330 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
333 * ata_dev_select - Select device 0/1 on ATA bus
334 * @ap: ATA channel to manipulate
335 * @device: ATA device (numbered from zero) to select
336 * @wait: non-zero to wait for Status register BSY bit to clear
337 * @can_sleep: non-zero if context allows sleeping
339 * Use the method defined in the ATA specification to
340 * make either device 0, or device 1, active on the
343 * This is a high-level version of ata_sff_dev_select(), which
344 * additionally provides the services of inserting the proper
345 * pauses and status polling, where needed.
350 static void ata_dev_select(struct ata_port *ap, unsigned int device,
351 unsigned int wait, unsigned int can_sleep)
353 if (ata_msg_probe(ap))
354 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
360 ap->ops->sff_dev_select(ap, device);
363 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
370 * ata_sff_irq_on - Enable interrupts on a port.
371 * @ap: Port on which interrupts are enabled.
373 * Enable interrupts on a legacy IDE device using MMIO or PIO,
374 * wait for idle, clear any pending interrupts.
376 * Note: may NOT be used as the sff_irq_on() entry in
377 * ata_port_operations.
380 * Inherited from caller.
382 void ata_sff_irq_on(struct ata_port *ap)
384 struct ata_ioports *ioaddr = &ap->ioaddr;
386 if (ap->ops->sff_irq_on) {
387 ap->ops->sff_irq_on(ap);
391 ap->ctl &= ~ATA_NIEN;
392 ap->last_ctl = ap->ctl;
394 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
395 ata_sff_set_devctl(ap, ap->ctl);
398 if (ap->ops->sff_irq_clear)
399 ap->ops->sff_irq_clear(ap);
401 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
404 * ata_sff_tf_load - send taskfile registers to host controller
405 * @ap: Port to which output is sent
406 * @tf: ATA taskfile register set
408 * Outputs ATA taskfile to standard ATA host controller.
411 * Inherited from caller.
413 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
415 struct ata_ioports *ioaddr = &ap->ioaddr;
416 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
418 if (tf->ctl != ap->last_ctl) {
419 if (ioaddr->ctl_addr)
420 iowrite8(tf->ctl, ioaddr->ctl_addr);
421 ap->last_ctl = tf->ctl;
425 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
426 WARN_ON_ONCE(!ioaddr->ctl_addr);
427 iowrite8(tf->hob_feature, ioaddr->feature_addr);
428 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
429 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
430 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
431 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
432 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
441 iowrite8(tf->feature, ioaddr->feature_addr);
442 iowrite8(tf->nsect, ioaddr->nsect_addr);
443 iowrite8(tf->lbal, ioaddr->lbal_addr);
444 iowrite8(tf->lbam, ioaddr->lbam_addr);
445 iowrite8(tf->lbah, ioaddr->lbah_addr);
446 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
454 if (tf->flags & ATA_TFLAG_DEVICE) {
455 iowrite8(tf->device, ioaddr->device_addr);
456 VPRINTK("device 0x%X\n", tf->device);
461 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
464 * ata_sff_tf_read - input device's ATA taskfile shadow registers
465 * @ap: Port from which input is read
466 * @tf: ATA taskfile register set for storing input
468 * Reads ATA taskfile registers for currently-selected device
469 * into @tf. Assumes the device has a fully SFF compliant task file
470 * layout and behaviour. If you device does not (eg has a different
471 * status method) then you will need to provide a replacement tf_read
474 * Inherited from caller.
476 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
478 struct ata_ioports *ioaddr = &ap->ioaddr;
480 tf->command = ata_sff_check_status(ap);
481 tf->feature = ioread8(ioaddr->error_addr);
482 tf->nsect = ioread8(ioaddr->nsect_addr);
483 tf->lbal = ioread8(ioaddr->lbal_addr);
484 tf->lbam = ioread8(ioaddr->lbam_addr);
485 tf->lbah = ioread8(ioaddr->lbah_addr);
486 tf->device = ioread8(ioaddr->device_addr);
488 if (tf->flags & ATA_TFLAG_LBA48) {
489 if (likely(ioaddr->ctl_addr)) {
490 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
491 tf->hob_feature = ioread8(ioaddr->error_addr);
492 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
493 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
494 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
495 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
496 iowrite8(tf->ctl, ioaddr->ctl_addr);
497 ap->last_ctl = tf->ctl;
502 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
505 * ata_sff_exec_command - issue ATA command to host controller
506 * @ap: port to which command is being issued
507 * @tf: ATA taskfile register set
509 * Issues ATA command, with proper synchronization with interrupt
510 * handler / other threads.
513 * spin_lock_irqsave(host lock)
515 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
517 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
519 iowrite8(tf->command, ap->ioaddr.command_addr);
522 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
525 * ata_tf_to_host - issue ATA taskfile to host controller
526 * @ap: port to which command is being issued
527 * @tf: ATA taskfile register set
529 * Issues ATA taskfile register set to ATA host controller,
530 * with proper synchronization with interrupt handler and
534 * spin_lock_irqsave(host lock)
536 static inline void ata_tf_to_host(struct ata_port *ap,
537 const struct ata_taskfile *tf)
539 ap->ops->sff_tf_load(ap, tf);
540 ap->ops->sff_exec_command(ap, tf);
544 * ata_sff_data_xfer - Transfer data by PIO
545 * @dev: device to target
547 * @buflen: buffer length
550 * Transfer data from/to the device data register by PIO.
553 * Inherited from caller.
558 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
559 unsigned int buflen, int rw)
561 struct ata_port *ap = dev->link->ap;
562 void __iomem *data_addr = ap->ioaddr.data_addr;
563 unsigned int words = buflen >> 1;
565 /* Transfer multiple of 2 bytes */
567 ioread16_rep(data_addr, buf, words);
569 iowrite16_rep(data_addr, buf, words);
571 /* Transfer trailing byte, if any. */
572 if (unlikely(buflen & 0x01)) {
573 unsigned char pad[2] = { };
575 /* Point buf to the tail of buffer */
579 * Use io*16_rep() accessors here as well to avoid pointlessly
580 * swapping bytes to and from on the big endian machines...
583 ioread16_rep(data_addr, pad, 1);
587 iowrite16_rep(data_addr, pad, 1);
594 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
597 * ata_sff_data_xfer32 - Transfer data by PIO
598 * @dev: device to target
600 * @buflen: buffer length
603 * Transfer data from/to the device data register by PIO using 32bit
607 * Inherited from caller.
613 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
614 unsigned int buflen, int rw)
616 struct ata_port *ap = dev->link->ap;
617 void __iomem *data_addr = ap->ioaddr.data_addr;
618 unsigned int words = buflen >> 2;
619 int slop = buflen & 3;
621 if (!(ap->pflags & ATA_PFLAG_PIO32))
622 return ata_sff_data_xfer(dev, buf, buflen, rw);
624 /* Transfer multiple of 4 bytes */
626 ioread32_rep(data_addr, buf, words);
628 iowrite32_rep(data_addr, buf, words);
630 /* Transfer trailing bytes, if any */
631 if (unlikely(slop)) {
632 unsigned char pad[4] = { };
634 /* Point buf to the tail of buffer */
635 buf += buflen - slop;
638 * Use io*_rep() accessors here as well to avoid pointlessly
639 * swapping bytes to and from on the big endian machines...
643 ioread16_rep(data_addr, pad, 1);
645 ioread32_rep(data_addr, pad, 1);
646 memcpy(buf, pad, slop);
648 memcpy(pad, buf, slop);
650 iowrite16_rep(data_addr, pad, 1);
652 iowrite32_rep(data_addr, pad, 1);
655 return (buflen + 1) & ~1;
657 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
660 * ata_sff_data_xfer_noirq - Transfer data by PIO
661 * @dev: device to target
663 * @buflen: buffer length
666 * Transfer data from/to the device data register by PIO. Do the
667 * transfer with interrupts disabled.
670 * Inherited from caller.
675 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
676 unsigned int buflen, int rw)
679 unsigned int consumed;
681 local_irq_save(flags);
682 consumed = ata_sff_data_xfer32(dev, buf, buflen, rw);
683 local_irq_restore(flags);
687 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
690 * ata_pio_sector - Transfer a sector of data.
691 * @qc: Command on going
693 * Transfer qc->sect_size bytes of data from/to the ATA device.
696 * Inherited from caller.
698 static void ata_pio_sector(struct ata_queued_cmd *qc)
700 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
701 struct ata_port *ap = qc->ap;
707 qc->curbytes = qc->nbytes;
710 if (qc->curbytes == qc->nbytes - qc->sect_size)
711 ap->hsm_task_state = HSM_ST_LAST;
713 page = sg_page(qc->cursg);
714 offset = qc->cursg->offset + qc->cursg_ofs;
716 /* get the current page and offset */
717 page = nth_page(page, (offset >> PAGE_SHIFT));
720 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
722 if (PageHighMem(page)) {
725 /* FIXME: use a bounce buffer */
726 local_irq_save(flags);
727 buf = kmap_atomic(page);
729 /* do the actual data transfer */
730 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
734 local_irq_restore(flags);
736 buf = page_address(page);
737 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
741 if (!do_write && !PageSlab(page))
742 flush_dcache_page(page);
744 qc->curbytes += qc->sect_size;
745 qc->cursg_ofs += qc->sect_size;
747 if (qc->cursg_ofs == qc->cursg->length) {
748 qc->cursg = sg_next(qc->cursg);
750 ap->hsm_task_state = HSM_ST_LAST;
756 * ata_pio_sectors - Transfer one or many sectors.
757 * @qc: Command on going
759 * Transfer one or many sectors of data from/to the
760 * ATA device for the DRQ request.
763 * Inherited from caller.
765 static void ata_pio_sectors(struct ata_queued_cmd *qc)
767 if (is_multi_taskfile(&qc->tf)) {
768 /* READ/WRITE MULTIPLE */
771 WARN_ON_ONCE(qc->dev->multi_count == 0);
773 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
774 qc->dev->multi_count);
780 ata_sff_sync(qc->ap); /* flush */
784 * atapi_send_cdb - Write CDB bytes to hardware
785 * @ap: Port to which ATAPI device is attached.
786 * @qc: Taskfile currently active
788 * When device has indicated its readiness to accept
789 * a CDB, this function is called. Send the CDB.
794 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
797 DPRINTK("send cdb\n");
798 WARN_ON_ONCE(qc->dev->cdb_len < 12);
800 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
802 /* FIXME: If the CDB is for DMA do we need to do the transition delay
803 or is bmdma_start guaranteed to do it ? */
804 switch (qc->tf.protocol) {
806 ap->hsm_task_state = HSM_ST;
808 case ATAPI_PROT_NODATA:
809 ap->hsm_task_state = HSM_ST_LAST;
811 #ifdef CONFIG_ATA_BMDMA
813 ap->hsm_task_state = HSM_ST_LAST;
815 ap->ops->bmdma_start(qc);
817 #endif /* CONFIG_ATA_BMDMA */
824 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
825 * @qc: Command on going
826 * @bytes: number of bytes
828 * Transfer Transfer data from/to the ATAPI device.
831 * Inherited from caller.
834 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
836 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
837 struct ata_port *ap = qc->ap;
838 struct ata_device *dev = qc->dev;
839 struct ata_eh_info *ehi = &dev->link->eh_info;
840 struct scatterlist *sg;
843 unsigned int offset, count, consumed;
848 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
849 "buf=%u cur=%u bytes=%u",
850 qc->nbytes, qc->curbytes, bytes);
855 offset = sg->offset + qc->cursg_ofs;
857 /* get the current page and offset */
858 page = nth_page(page, (offset >> PAGE_SHIFT));
861 /* don't overrun current sg */
862 count = min(sg->length - qc->cursg_ofs, bytes);
864 /* don't cross page boundaries */
865 count = min(count, (unsigned int)PAGE_SIZE - offset);
867 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
869 if (PageHighMem(page)) {
872 /* FIXME: use bounce buffer */
873 local_irq_save(flags);
874 buf = kmap_atomic(page);
876 /* do the actual data transfer */
877 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
881 local_irq_restore(flags);
883 buf = page_address(page);
884 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
888 bytes -= min(bytes, consumed);
889 qc->curbytes += count;
890 qc->cursg_ofs += count;
892 if (qc->cursg_ofs == sg->length) {
893 qc->cursg = sg_next(qc->cursg);
898 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
899 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
900 * check correctly as it doesn't know if it is the last request being
901 * made. Somebody should implement a proper sanity check.
909 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
910 * @qc: Command on going
912 * Transfer Transfer data from/to the ATAPI device.
915 * Inherited from caller.
917 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
919 struct ata_port *ap = qc->ap;
920 struct ata_device *dev = qc->dev;
921 struct ata_eh_info *ehi = &dev->link->eh_info;
922 unsigned int ireason, bc_lo, bc_hi, bytes;
923 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
925 /* Abuse qc->result_tf for temp storage of intermediate TF
926 * here to save some kernel stack usage.
927 * For normal completion, qc->result_tf is not relevant. For
928 * error, qc->result_tf is later overwritten by ata_qc_complete().
929 * So, the correctness of qc->result_tf is not affected.
931 ap->ops->sff_tf_read(ap, &qc->result_tf);
932 ireason = qc->result_tf.nsect;
933 bc_lo = qc->result_tf.lbam;
934 bc_hi = qc->result_tf.lbah;
935 bytes = (bc_hi << 8) | bc_lo;
937 /* shall be cleared to zero, indicating xfer of data */
938 if (unlikely(ireason & ATAPI_COD))
941 /* make sure transfer direction matches expected */
942 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
943 if (unlikely(do_write != i_write))
946 if (unlikely(!bytes))
949 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
951 if (unlikely(__atapi_pio_bytes(qc, bytes)))
953 ata_sff_sync(ap); /* flush */
958 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
961 qc->err_mask |= AC_ERR_HSM;
962 ap->hsm_task_state = HSM_ST_ERR;
966 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
967 * @ap: the target ata_port
971 * 1 if ok in workqueue, 0 otherwise.
973 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
974 struct ata_queued_cmd *qc)
976 if (qc->tf.flags & ATA_TFLAG_POLLING)
979 if (ap->hsm_task_state == HSM_ST_FIRST) {
980 if (qc->tf.protocol == ATA_PROT_PIO &&
981 (qc->tf.flags & ATA_TFLAG_WRITE))
984 if (ata_is_atapi(qc->tf.protocol) &&
985 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
993 * ata_hsm_qc_complete - finish a qc running on standard HSM
994 * @qc: Command to complete
995 * @in_wq: 1 if called from workqueue, 0 otherwise
997 * Finish @qc which is running on standard HSM.
1000 * If @in_wq is zero, spin_lock_irqsave(host lock).
1001 * Otherwise, none on entry and grabs host lock.
1003 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1005 struct ata_port *ap = qc->ap;
1007 if (ap->ops->error_handler) {
1009 /* EH might have kicked in while host lock is
1012 qc = ata_qc_from_tag(ap, qc->tag);
1014 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1016 ata_qc_complete(qc);
1018 ata_port_freeze(ap);
1021 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1022 ata_qc_complete(qc);
1024 ata_port_freeze(ap);
1029 ata_qc_complete(qc);
1031 ata_qc_complete(qc);
1036 * ata_sff_hsm_move - move the HSM to the next state.
1037 * @ap: the target ata_port
1039 * @status: current device status
1040 * @in_wq: 1 if called from workqueue, 0 otherwise
1043 * 1 when poll next status needed, 0 otherwise.
1045 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1046 u8 status, int in_wq)
1048 struct ata_link *link = qc->dev->link;
1049 struct ata_eh_info *ehi = &link->eh_info;
1052 lockdep_assert_held(ap->lock);
1054 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1056 /* Make sure ata_sff_qc_issue() does not throw things
1057 * like DMA polling into the workqueue. Notice that
1058 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1060 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1063 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1064 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1066 switch (ap->hsm_task_state) {
1068 /* Send first data block or PACKET CDB */
1070 /* If polling, we will stay in the work queue after
1071 * sending the data. Otherwise, interrupt handler
1072 * takes over after sending the data.
1074 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1076 /* check device status */
1077 if (unlikely((status & ATA_DRQ) == 0)) {
1078 /* handle BSY=0, DRQ=0 as error */
1079 if (likely(status & (ATA_ERR | ATA_DF)))
1080 /* device stops HSM for abort/error */
1081 qc->err_mask |= AC_ERR_DEV;
1083 /* HSM violation. Let EH handle this */
1084 ata_ehi_push_desc(ehi,
1085 "ST_FIRST: !(DRQ|ERR|DF)");
1086 qc->err_mask |= AC_ERR_HSM;
1089 ap->hsm_task_state = HSM_ST_ERR;
1093 /* Device should not ask for data transfer (DRQ=1)
1094 * when it finds something wrong.
1095 * We ignore DRQ here and stop the HSM by
1096 * changing hsm_task_state to HSM_ST_ERR and
1097 * let the EH abort the command or reset the device.
1099 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1100 /* Some ATAPI tape drives forget to clear the ERR bit
1101 * when doing the next command (mostly request sense).
1102 * We ignore ERR here to workaround and proceed sending
1105 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1106 ata_ehi_push_desc(ehi, "ST_FIRST: "
1107 "DRQ=1 with device error, "
1108 "dev_stat 0x%X", status);
1109 qc->err_mask |= AC_ERR_HSM;
1110 ap->hsm_task_state = HSM_ST_ERR;
1115 if (qc->tf.protocol == ATA_PROT_PIO) {
1116 /* PIO data out protocol.
1117 * send first data block.
1120 /* ata_pio_sectors() might change the state
1121 * to HSM_ST_LAST. so, the state is changed here
1122 * before ata_pio_sectors().
1124 ap->hsm_task_state = HSM_ST;
1125 ata_pio_sectors(qc);
1128 atapi_send_cdb(ap, qc);
1130 /* if polling, ata_sff_pio_task() handles the rest.
1131 * otherwise, interrupt handler takes over from here.
1136 /* complete command or read/write the data register */
1137 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1138 /* ATAPI PIO protocol */
1139 if ((status & ATA_DRQ) == 0) {
1140 /* No more data to transfer or device error.
1141 * Device error will be tagged in HSM_ST_LAST.
1143 ap->hsm_task_state = HSM_ST_LAST;
1147 /* Device should not ask for data transfer (DRQ=1)
1148 * when it finds something wrong.
1149 * We ignore DRQ here and stop the HSM by
1150 * changing hsm_task_state to HSM_ST_ERR and
1151 * let the EH abort the command or reset the device.
1153 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1154 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1155 "DRQ=1 with device error, "
1156 "dev_stat 0x%X", status);
1157 qc->err_mask |= AC_ERR_HSM;
1158 ap->hsm_task_state = HSM_ST_ERR;
1162 atapi_pio_bytes(qc);
1164 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1165 /* bad ireason reported by device */
1169 /* ATA PIO protocol */
1170 if (unlikely((status & ATA_DRQ) == 0)) {
1171 /* handle BSY=0, DRQ=0 as error */
1172 if (likely(status & (ATA_ERR | ATA_DF))) {
1173 /* device stops HSM for abort/error */
1174 qc->err_mask |= AC_ERR_DEV;
1176 /* If diagnostic failed and this is
1177 * IDENTIFY, it's likely a phantom
1178 * device. Mark hint.
1180 if (qc->dev->horkage &
1181 ATA_HORKAGE_DIAGNOSTIC)
1185 /* HSM violation. Let EH handle this.
1186 * Phantom devices also trigger this
1187 * condition. Mark hint.
1189 ata_ehi_push_desc(ehi, "ST-ATA: "
1190 "DRQ=0 without device error, "
1191 "dev_stat 0x%X", status);
1192 qc->err_mask |= AC_ERR_HSM |
1196 ap->hsm_task_state = HSM_ST_ERR;
1200 /* For PIO reads, some devices may ask for
1201 * data transfer (DRQ=1) alone with ERR=1.
1202 * We respect DRQ here and transfer one
1203 * block of junk data before changing the
1204 * hsm_task_state to HSM_ST_ERR.
1206 * For PIO writes, ERR=1 DRQ=1 doesn't make
1207 * sense since the data block has been
1208 * transferred to the device.
1210 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1211 /* data might be corrputed */
1212 qc->err_mask |= AC_ERR_DEV;
1214 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1215 ata_pio_sectors(qc);
1216 status = ata_wait_idle(ap);
1219 if (status & (ATA_BUSY | ATA_DRQ)) {
1220 ata_ehi_push_desc(ehi, "ST-ATA: "
1221 "BUSY|DRQ persists on ERR|DF, "
1222 "dev_stat 0x%X", status);
1223 qc->err_mask |= AC_ERR_HSM;
1226 /* There are oddball controllers with
1227 * status register stuck at 0x7f and
1228 * lbal/m/h at zero which makes it
1229 * pass all other presence detection
1230 * mechanisms we have. Set NODEV_HINT
1231 * for it. Kernel bz#7241.
1234 qc->err_mask |= AC_ERR_NODEV_HINT;
1236 /* ata_pio_sectors() might change the
1237 * state to HSM_ST_LAST. so, the state
1238 * is changed after ata_pio_sectors().
1240 ap->hsm_task_state = HSM_ST_ERR;
1244 ata_pio_sectors(qc);
1246 if (ap->hsm_task_state == HSM_ST_LAST &&
1247 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1249 status = ata_wait_idle(ap);
1258 if (unlikely(!ata_ok(status))) {
1259 qc->err_mask |= __ac_err_mask(status);
1260 ap->hsm_task_state = HSM_ST_ERR;
1264 /* no more data to transfer */
1265 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1266 ap->print_id, qc->dev->devno, status);
1268 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1270 ap->hsm_task_state = HSM_ST_IDLE;
1272 /* complete taskfile transaction */
1273 ata_hsm_qc_complete(qc, in_wq);
1279 ap->hsm_task_state = HSM_ST_IDLE;
1281 /* complete taskfile transaction */
1282 ata_hsm_qc_complete(qc, in_wq);
1293 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1295 void ata_sff_queue_work(struct work_struct *work)
1297 queue_work(ata_sff_wq, work);
1299 EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1301 void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1303 queue_delayed_work(ata_sff_wq, dwork, delay);
1305 EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1307 void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1309 struct ata_port *ap = link->ap;
1311 WARN_ON((ap->sff_pio_task_link != NULL) &&
1312 (ap->sff_pio_task_link != link));
1313 ap->sff_pio_task_link = link;
1315 /* may fail if ata_sff_flush_pio_task() in progress */
1316 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1318 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1320 void ata_sff_flush_pio_task(struct ata_port *ap)
1324 cancel_delayed_work_sync(&ap->sff_pio_task);
1327 * We wanna reset the HSM state to IDLE. If we do so without
1328 * grabbing the port lock, critical sections protected by it which
1329 * expect the HSM state to stay stable may get surprised. For
1330 * example, we may set IDLE in between the time
1331 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1332 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1334 spin_lock_irq(ap->lock);
1335 ap->hsm_task_state = HSM_ST_IDLE;
1336 spin_unlock_irq(ap->lock);
1338 ap->sff_pio_task_link = NULL;
1340 if (ata_msg_ctl(ap))
1341 ata_port_dbg(ap, "%s: EXIT\n", __func__);
1344 static void ata_sff_pio_task(struct work_struct *work)
1346 struct ata_port *ap =
1347 container_of(work, struct ata_port, sff_pio_task.work);
1348 struct ata_link *link = ap->sff_pio_task_link;
1349 struct ata_queued_cmd *qc;
1353 spin_lock_irq(ap->lock);
1355 BUG_ON(ap->sff_pio_task_link == NULL);
1356 /* qc can be NULL if timeout occurred */
1357 qc = ata_qc_from_tag(ap, link->active_tag);
1359 ap->sff_pio_task_link = NULL;
1364 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1367 * This is purely heuristic. This is a fast path.
1368 * Sometimes when we enter, BSY will be cleared in
1369 * a chk-status or two. If not, the drive is probably seeking
1370 * or something. Snooze for a couple msecs, then
1371 * chk-status again. If still busy, queue delayed work.
1373 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1374 if (status & ATA_BUSY) {
1375 spin_unlock_irq(ap->lock);
1377 spin_lock_irq(ap->lock);
1379 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1380 if (status & ATA_BUSY) {
1381 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1387 * hsm_move() may trigger another command to be processed.
1388 * clean the link beforehand.
1390 ap->sff_pio_task_link = NULL;
1392 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1394 /* another command or interrupt handler
1395 * may be running at this point.
1400 spin_unlock_irq(ap->lock);
1404 * ata_sff_qc_issue - issue taskfile to a SFF controller
1405 * @qc: command to issue to device
1407 * This function issues a PIO or NODATA command to a SFF
1411 * spin_lock_irqsave(host lock)
1414 * Zero on success, AC_ERR_* mask on failure
1416 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1418 struct ata_port *ap = qc->ap;
1419 struct ata_link *link = qc->dev->link;
1421 /* Use polling pio if the LLD doesn't handle
1422 * interrupt driven pio and atapi CDB interrupt.
1424 if (ap->flags & ATA_FLAG_PIO_POLLING)
1425 qc->tf.flags |= ATA_TFLAG_POLLING;
1427 /* select the device */
1428 ata_dev_select(ap, qc->dev->devno, 1, 0);
1430 /* start the command */
1431 switch (qc->tf.protocol) {
1432 case ATA_PROT_NODATA:
1433 if (qc->tf.flags & ATA_TFLAG_POLLING)
1434 ata_qc_set_polling(qc);
1436 ata_tf_to_host(ap, &qc->tf);
1437 ap->hsm_task_state = HSM_ST_LAST;
1439 if (qc->tf.flags & ATA_TFLAG_POLLING)
1440 ata_sff_queue_pio_task(link, 0);
1445 if (qc->tf.flags & ATA_TFLAG_POLLING)
1446 ata_qc_set_polling(qc);
1448 ata_tf_to_host(ap, &qc->tf);
1450 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1451 /* PIO data out protocol */
1452 ap->hsm_task_state = HSM_ST_FIRST;
1453 ata_sff_queue_pio_task(link, 0);
1455 /* always send first data block using the
1456 * ata_sff_pio_task() codepath.
1459 /* PIO data in protocol */
1460 ap->hsm_task_state = HSM_ST;
1462 if (qc->tf.flags & ATA_TFLAG_POLLING)
1463 ata_sff_queue_pio_task(link, 0);
1465 /* if polling, ata_sff_pio_task() handles the
1466 * rest. otherwise, interrupt handler takes
1473 case ATAPI_PROT_PIO:
1474 case ATAPI_PROT_NODATA:
1475 if (qc->tf.flags & ATA_TFLAG_POLLING)
1476 ata_qc_set_polling(qc);
1478 ata_tf_to_host(ap, &qc->tf);
1480 ap->hsm_task_state = HSM_ST_FIRST;
1482 /* send cdb by polling if no cdb interrupt */
1483 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1484 (qc->tf.flags & ATA_TFLAG_POLLING))
1485 ata_sff_queue_pio_task(link, 0);
1489 return AC_ERR_SYSTEM;
1494 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1497 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1498 * @qc: qc to fill result TF for
1500 * @qc is finished and result TF needs to be filled. Fill it
1501 * using ->sff_tf_read.
1504 * spin_lock_irqsave(host lock)
1507 * true indicating that result TF is successfully filled.
1509 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1511 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1514 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1516 static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1518 ap->stats.idle_irq++;
1521 if ((ap->stats.idle_irq % 1000) == 0) {
1522 ap->ops->sff_check_status(ap);
1523 if (ap->ops->sff_irq_clear)
1524 ap->ops->sff_irq_clear(ap);
1525 ata_port_warn(ap, "irq trap\n");
1529 return 0; /* irq not handled */
1532 static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1533 struct ata_queued_cmd *qc,
1538 VPRINTK("ata%u: protocol %d task_state %d\n",
1539 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1541 /* Check whether we are expecting interrupt in this state */
1542 switch (ap->hsm_task_state) {
1544 /* Some pre-ATAPI-4 devices assert INTRQ
1545 * at this state when ready to receive CDB.
1548 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1549 * The flag was turned on only for atapi devices. No
1550 * need to check ata_is_atapi(qc->tf.protocol) again.
1552 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1553 return ata_sff_idle_irq(ap);
1556 return ata_sff_idle_irq(ap);
1561 /* check main status, clearing INTRQ if needed */
1562 status = ata_sff_irq_status(ap);
1563 if (status & ATA_BUSY) {
1565 /* BMDMA engine is already stopped, we're screwed */
1566 qc->err_mask |= AC_ERR_HSM;
1567 ap->hsm_task_state = HSM_ST_ERR;
1569 return ata_sff_idle_irq(ap);
1572 /* clear irq events */
1573 if (ap->ops->sff_irq_clear)
1574 ap->ops->sff_irq_clear(ap);
1576 ata_sff_hsm_move(ap, qc, status, 0);
1578 return 1; /* irq handled */
1582 * ata_sff_port_intr - Handle SFF port interrupt
1583 * @ap: Port on which interrupt arrived (possibly...)
1584 * @qc: Taskfile currently active in engine
1586 * Handle port interrupt for given queued command.
1589 * spin_lock_irqsave(host lock)
1592 * One if interrupt was handled, zero if not (shared irq).
1594 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1596 return __ata_sff_port_intr(ap, qc, false);
1598 EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1600 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1601 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1603 struct ata_host *host = dev_instance;
1604 bool retried = false;
1606 unsigned int handled, idle, polling;
1607 unsigned long flags;
1609 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1610 spin_lock_irqsave(&host->lock, flags);
1613 handled = idle = polling = 0;
1614 for (i = 0; i < host->n_ports; i++) {
1615 struct ata_port *ap = host->ports[i];
1616 struct ata_queued_cmd *qc;
1618 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1620 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1621 handled |= port_intr(ap, qc);
1629 * If no port was expecting IRQ but the controller is actually
1630 * asserting IRQ line, nobody cared will ensue. Check IRQ
1631 * pending status if available and clear spurious IRQ.
1633 if (!handled && !retried) {
1636 for (i = 0; i < host->n_ports; i++) {
1637 struct ata_port *ap = host->ports[i];
1639 if (polling & (1 << i))
1642 if (!ap->ops->sff_irq_check ||
1643 !ap->ops->sff_irq_check(ap))
1646 if (idle & (1 << i)) {
1647 ap->ops->sff_check_status(ap);
1648 if (ap->ops->sff_irq_clear)
1649 ap->ops->sff_irq_clear(ap);
1651 /* clear INTRQ and check if BUSY cleared */
1652 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1655 * With command in flight, we can't do
1656 * sff_irq_clear() w/o racing with completion.
1667 spin_unlock_irqrestore(&host->lock, flags);
1669 return IRQ_RETVAL(handled);
1673 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1674 * @irq: irq line (unused)
1675 * @dev_instance: pointer to our ata_host information structure
1677 * Default interrupt handler for PCI IDE devices. Calls
1678 * ata_sff_port_intr() for each port that is not disabled.
1681 * Obtains host lock during operation.
1684 * IRQ_NONE or IRQ_HANDLED.
1686 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1688 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1690 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1693 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1694 * @ap: port that appears to have timed out
1696 * Called from the libata error handlers when the core code suspects
1697 * an interrupt has been lost. If it has complete anything we can and
1698 * then return. Interface must support altstatus for this faster
1699 * recovery to occur.
1702 * Caller holds host lock
1705 void ata_sff_lost_interrupt(struct ata_port *ap)
1708 struct ata_queued_cmd *qc;
1710 /* Only one outstanding command per SFF channel */
1711 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1712 /* We cannot lose an interrupt on a non-existent or polled command */
1713 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1715 /* See if the controller thinks it is still busy - if so the command
1716 isn't a lost IRQ but is still in progress */
1717 status = ata_sff_altstatus(ap);
1718 if (status & ATA_BUSY)
1721 /* There was a command running, we are no longer busy and we have
1723 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
1725 /* Run the host interrupt logic as if the interrupt had not been
1727 ata_sff_port_intr(ap, qc);
1729 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1732 * ata_sff_freeze - Freeze SFF controller port
1733 * @ap: port to freeze
1735 * Freeze SFF controller port.
1738 * Inherited from caller.
1740 void ata_sff_freeze(struct ata_port *ap)
1742 ap->ctl |= ATA_NIEN;
1743 ap->last_ctl = ap->ctl;
1745 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1746 ata_sff_set_devctl(ap, ap->ctl);
1748 /* Under certain circumstances, some controllers raise IRQ on
1749 * ATA_NIEN manipulation. Also, many controllers fail to mask
1750 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1752 ap->ops->sff_check_status(ap);
1754 if (ap->ops->sff_irq_clear)
1755 ap->ops->sff_irq_clear(ap);
1757 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1760 * ata_sff_thaw - Thaw SFF controller port
1763 * Thaw SFF controller port.
1766 * Inherited from caller.
1768 void ata_sff_thaw(struct ata_port *ap)
1770 /* clear & re-enable interrupts */
1771 ap->ops->sff_check_status(ap);
1772 if (ap->ops->sff_irq_clear)
1773 ap->ops->sff_irq_clear(ap);
1776 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1779 * ata_sff_prereset - prepare SFF link for reset
1780 * @link: SFF link to be reset
1781 * @deadline: deadline jiffies for the operation
1783 * SFF link @link is about to be reset. Initialize it. It first
1784 * calls ata_std_prereset() and wait for !BSY if the port is
1788 * Kernel thread context (may sleep)
1791 * 0 on success, -errno otherwise.
1793 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1795 struct ata_eh_context *ehc = &link->eh_context;
1798 rc = ata_std_prereset(link, deadline);
1802 /* if we're about to do hardreset, nothing more to do */
1803 if (ehc->i.action & ATA_EH_HARDRESET)
1806 /* wait for !BSY if we don't know that no device is attached */
1807 if (!ata_link_offline(link)) {
1808 rc = ata_sff_wait_ready(link, deadline);
1809 if (rc && rc != -ENODEV) {
1811 "device not ready (errno=%d), forcing hardreset\n",
1813 ehc->i.action |= ATA_EH_HARDRESET;
1819 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1822 * ata_devchk - PATA device presence detection
1823 * @ap: ATA channel to examine
1824 * @device: Device to examine (starting at zero)
1826 * This technique was originally described in
1827 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1828 * later found its way into the ATA/ATAPI spec.
1830 * Write a pattern to the ATA shadow registers,
1831 * and if a device is present, it will respond by
1832 * correctly storing and echoing back the
1833 * ATA shadow register contents.
1838 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1840 struct ata_ioports *ioaddr = &ap->ioaddr;
1843 ap->ops->sff_dev_select(ap, device);
1845 iowrite8(0x55, ioaddr->nsect_addr);
1846 iowrite8(0xaa, ioaddr->lbal_addr);
1848 iowrite8(0xaa, ioaddr->nsect_addr);
1849 iowrite8(0x55, ioaddr->lbal_addr);
1851 iowrite8(0x55, ioaddr->nsect_addr);
1852 iowrite8(0xaa, ioaddr->lbal_addr);
1854 nsect = ioread8(ioaddr->nsect_addr);
1855 lbal = ioread8(ioaddr->lbal_addr);
1857 if ((nsect == 0x55) && (lbal == 0xaa))
1858 return 1; /* we found a device */
1860 return 0; /* nothing found */
1864 * ata_sff_dev_classify - Parse returned ATA device signature
1865 * @dev: ATA device to classify (starting at zero)
1866 * @present: device seems present
1867 * @r_err: Value of error register on completion
1869 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1870 * an ATA/ATAPI-defined set of values is placed in the ATA
1871 * shadow registers, indicating the results of device detection
1874 * Select the ATA device, and read the values from the ATA shadow
1875 * registers. Then parse according to the Error register value,
1876 * and the spec-defined values examined by ata_dev_classify().
1882 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1884 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1887 struct ata_port *ap = dev->link->ap;
1888 struct ata_taskfile tf;
1892 ap->ops->sff_dev_select(ap, dev->devno);
1894 memset(&tf, 0, sizeof(tf));
1896 ap->ops->sff_tf_read(ap, &tf);
1901 /* see if device passed diags: continue and warn later */
1903 /* diagnostic fail : do nothing _YET_ */
1904 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1907 else if ((dev->devno == 0) && (err == 0x81))
1910 return ATA_DEV_NONE;
1912 /* determine if device is ATA or ATAPI */
1913 class = ata_dev_classify(&tf);
1915 if (class == ATA_DEV_UNKNOWN) {
1916 /* If the device failed diagnostic, it's likely to
1917 * have reported incorrect device signature too.
1918 * Assume ATA device if the device seems present but
1919 * device signature is invalid with diagnostic
1922 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1923 class = ATA_DEV_ATA;
1925 class = ATA_DEV_NONE;
1926 } else if ((class == ATA_DEV_ATA) &&
1927 (ap->ops->sff_check_status(ap) == 0))
1928 class = ATA_DEV_NONE;
1932 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1935 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1936 * @link: SFF link which is just reset
1937 * @devmask: mask of present devices
1938 * @deadline: deadline jiffies for the operation
1940 * Wait devices attached to SFF @link to become ready after
1941 * reset. It contains preceding 150ms wait to avoid accessing TF
1942 * status register too early.
1945 * Kernel thread context (may sleep).
1948 * 0 on success, -ENODEV if some or all of devices in @devmask
1949 * don't seem to exist. -errno on other errors.
1951 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1952 unsigned long deadline)
1954 struct ata_port *ap = link->ap;
1955 struct ata_ioports *ioaddr = &ap->ioaddr;
1956 unsigned int dev0 = devmask & (1 << 0);
1957 unsigned int dev1 = devmask & (1 << 1);
1960 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1962 /* always check readiness of the master device */
1963 rc = ata_sff_wait_ready(link, deadline);
1964 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1965 * and TF status is 0xff, bail out on it too.
1970 /* if device 1 was found in ata_devchk, wait for register
1971 * access briefly, then wait for BSY to clear.
1976 ap->ops->sff_dev_select(ap, 1);
1978 /* Wait for register access. Some ATAPI devices fail
1979 * to set nsect/lbal after reset, so don't waste too
1980 * much time on it. We're gonna wait for !BSY anyway.
1982 for (i = 0; i < 2; i++) {
1985 nsect = ioread8(ioaddr->nsect_addr);
1986 lbal = ioread8(ioaddr->lbal_addr);
1987 if ((nsect == 1) && (lbal == 1))
1989 ata_msleep(ap, 50); /* give drive a breather */
1992 rc = ata_sff_wait_ready(link, deadline);
2000 /* is all this really necessary? */
2001 ap->ops->sff_dev_select(ap, 0);
2003 ap->ops->sff_dev_select(ap, 1);
2005 ap->ops->sff_dev_select(ap, 0);
2009 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2011 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2012 unsigned long deadline)
2014 struct ata_ioports *ioaddr = &ap->ioaddr;
2016 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2018 if (ap->ioaddr.ctl_addr) {
2019 /* software reset. causes dev0 to be selected */
2020 iowrite8(ap->ctl, ioaddr->ctl_addr);
2021 udelay(20); /* FIXME: flush */
2022 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2023 udelay(20); /* FIXME: flush */
2024 iowrite8(ap->ctl, ioaddr->ctl_addr);
2025 ap->last_ctl = ap->ctl;
2028 /* wait the port to become ready */
2029 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2033 * ata_sff_softreset - reset host port via ATA SRST
2034 * @link: ATA link to reset
2035 * @classes: resulting classes of attached devices
2036 * @deadline: deadline jiffies for the operation
2038 * Reset host port using ATA SRST.
2041 * Kernel thread context (may sleep)
2044 * 0 on success, -errno otherwise.
2046 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2047 unsigned long deadline)
2049 struct ata_port *ap = link->ap;
2050 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2051 unsigned int devmask = 0;
2057 /* determine if device 0/1 are present */
2058 if (ata_devchk(ap, 0))
2059 devmask |= (1 << 0);
2060 if (slave_possible && ata_devchk(ap, 1))
2061 devmask |= (1 << 1);
2063 /* select device 0 again */
2064 ap->ops->sff_dev_select(ap, 0);
2066 /* issue bus reset */
2067 DPRINTK("about to softreset, devmask=%x\n", devmask);
2068 rc = ata_bus_softreset(ap, devmask, deadline);
2069 /* if link is occupied, -ENODEV too is an error */
2070 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2071 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
2075 /* determine by signature whether we have ATA or ATAPI devices */
2076 classes[0] = ata_sff_dev_classify(&link->device[0],
2077 devmask & (1 << 0), &err);
2078 if (slave_possible && err != 0x81)
2079 classes[1] = ata_sff_dev_classify(&link->device[1],
2080 devmask & (1 << 1), &err);
2082 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2085 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2088 * sata_sff_hardreset - reset host port via SATA phy reset
2089 * @link: link to reset
2090 * @class: resulting class of attached device
2091 * @deadline: deadline jiffies for the operation
2093 * SATA phy-reset host port using DET bits of SControl register,
2094 * wait for !BSY and classify the attached device.
2097 * Kernel thread context (may sleep)
2100 * 0 on success, -errno otherwise.
2102 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2103 unsigned long deadline)
2105 struct ata_eh_context *ehc = &link->eh_context;
2106 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2110 rc = sata_link_hardreset(link, timing, deadline, &online,
2111 ata_sff_check_ready);
2113 *class = ata_sff_dev_classify(link->device, 1, NULL);
2115 DPRINTK("EXIT, class=%u\n", *class);
2118 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2121 * ata_sff_postreset - SFF postreset callback
2122 * @link: the target SFF ata_link
2123 * @classes: classes of attached devices
2125 * This function is invoked after a successful reset. It first
2126 * calls ata_std_postreset() and performs SFF specific postreset
2130 * Kernel thread context (may sleep)
2132 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2134 struct ata_port *ap = link->ap;
2136 ata_std_postreset(link, classes);
2138 /* is double-select really necessary? */
2139 if (classes[0] != ATA_DEV_NONE)
2140 ap->ops->sff_dev_select(ap, 1);
2141 if (classes[1] != ATA_DEV_NONE)
2142 ap->ops->sff_dev_select(ap, 0);
2144 /* bail out if no device is present */
2145 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2146 DPRINTK("EXIT, no device\n");
2150 /* set up device control */
2151 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2152 ata_sff_set_devctl(ap, ap->ctl);
2153 ap->last_ctl = ap->ctl;
2156 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2159 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2162 * Drain the FIFO and device of any stuck data following a command
2163 * failing to complete. In some cases this is necessary before a
2164 * reset will recover the device.
2168 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2171 struct ata_port *ap;
2173 /* We only need to flush incoming data when a command was running */
2174 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2178 /* Drain up to 64K of data before we give up this recovery method */
2179 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2180 && count < 65536; count += 2)
2181 ioread16(ap->ioaddr.data_addr);
2183 /* Can become DEBUG later */
2185 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2188 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2191 * ata_sff_error_handler - Stock error handler for SFF controller
2192 * @ap: port to handle error for
2194 * Stock error handler for SFF controller. It can handle both
2195 * PATA and SATA controllers. Many controllers should be able to
2196 * use this EH as-is or with some added handling before and
2200 * Kernel thread context (may sleep)
2202 void ata_sff_error_handler(struct ata_port *ap)
2204 ata_reset_fn_t softreset = ap->ops->softreset;
2205 ata_reset_fn_t hardreset = ap->ops->hardreset;
2206 struct ata_queued_cmd *qc;
2207 unsigned long flags;
2209 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2210 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2213 spin_lock_irqsave(ap->lock, flags);
2216 * We *MUST* do FIFO draining before we issue a reset as
2217 * several devices helpfully clear their internal state and
2218 * will lock solid if we touch the data port post reset. Pass
2219 * qc in case anyone wants to do different PIO/DMA recovery or
2220 * has per command fixups
2222 if (ap->ops->sff_drain_fifo)
2223 ap->ops->sff_drain_fifo(qc);
2225 spin_unlock_irqrestore(ap->lock, flags);
2227 /* ignore built-in hardresets if SCR access is not available */
2228 if ((hardreset == sata_std_hardreset ||
2229 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2232 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2233 ap->ops->postreset);
2235 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2238 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2239 * @ioaddr: IO address structure to be initialized
2241 * Utility function which initializes data_addr, error_addr,
2242 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2243 * device_addr, status_addr, and command_addr to standard offsets
2244 * relative to cmd_addr.
2246 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2248 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2250 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2251 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2252 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2253 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2254 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2255 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2256 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2257 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2258 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2259 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2261 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2265 static int ata_resources_present(struct pci_dev *pdev, int port)
2269 /* Check the PCI resources for this channel are enabled */
2271 for (i = 0; i < 2; i++) {
2272 if (pci_resource_start(pdev, port + i) == 0 ||
2273 pci_resource_len(pdev, port + i) == 0)
2280 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2281 * @host: target ATA host
2283 * Acquire native PCI ATA resources for @host and initialize the
2284 * first two ports of @host accordingly. Ports marked dummy are
2285 * skipped and allocation failure makes the port dummy.
2287 * Note that native PCI resources are valid even for legacy hosts
2288 * as we fix up pdev resources array early in boot, so this
2289 * function can be used for both native and legacy SFF hosts.
2292 * Inherited from calling layer (may sleep).
2295 * 0 if at least one port is initialized, -ENODEV if no port is
2298 int ata_pci_sff_init_host(struct ata_host *host)
2300 struct device *gdev = host->dev;
2301 struct pci_dev *pdev = to_pci_dev(gdev);
2302 unsigned int mask = 0;
2305 /* request, iomap BARs and init port addresses accordingly */
2306 for (i = 0; i < 2; i++) {
2307 struct ata_port *ap = host->ports[i];
2309 void __iomem * const *iomap;
2311 if (ata_port_is_dummy(ap))
2314 /* Discard disabled ports. Some controllers show
2315 * their unused channels this way. Disabled ports are
2318 if (!ata_resources_present(pdev, i)) {
2319 ap->ops = &ata_dummy_port_ops;
2323 rc = pcim_iomap_regions(pdev, 0x3 << base,
2324 dev_driver_string(gdev));
2327 "failed to request/iomap BARs for port %d (errno=%d)\n",
2330 pcim_pin_device(pdev);
2331 ap->ops = &ata_dummy_port_ops;
2334 host->iomap = iomap = pcim_iomap_table(pdev);
2336 ap->ioaddr.cmd_addr = iomap[base];
2337 ap->ioaddr.altstatus_addr =
2338 ap->ioaddr.ctl_addr = (void __iomem *)
2339 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2340 ata_sff_std_ports(&ap->ioaddr);
2342 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2343 (unsigned long long)pci_resource_start(pdev, base),
2344 (unsigned long long)pci_resource_start(pdev, base + 1));
2350 dev_err(gdev, "no available native port\n");
2356 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2359 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2360 * @pdev: target PCI device
2361 * @ppi: array of port_info, must be enough for two ports
2362 * @r_host: out argument for the initialized ATA host
2364 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2365 * all PCI resources and initialize it accordingly in one go.
2368 * Inherited from calling layer (may sleep).
2371 * 0 on success, -errno otherwise.
2373 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2374 const struct ata_port_info * const *ppi,
2375 struct ata_host **r_host)
2377 struct ata_host *host;
2380 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2383 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2385 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2390 rc = ata_pci_sff_init_host(host);
2394 devres_remove_group(&pdev->dev, NULL);
2399 devres_release_group(&pdev->dev, NULL);
2402 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2405 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2406 * @host: target SFF ATA host
2407 * @irq_handler: irq_handler used when requesting IRQ(s)
2408 * @sht: scsi_host_template to use when registering the host
2410 * This is the counterpart of ata_host_activate() for SFF ATA
2411 * hosts. This separate helper is necessary because SFF hosts
2412 * use two separate interrupts in legacy mode.
2415 * Inherited from calling layer (may sleep).
2418 * 0 on success, -errno otherwise.
2420 int ata_pci_sff_activate_host(struct ata_host *host,
2421 irq_handler_t irq_handler,
2422 struct scsi_host_template *sht)
2424 struct device *dev = host->dev;
2425 struct pci_dev *pdev = to_pci_dev(dev);
2426 const char *drv_name = dev_driver_string(host->dev);
2427 int legacy_mode = 0, rc;
2429 rc = ata_host_start(host);
2433 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2436 /* TODO: What if one channel is in native mode ... */
2437 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2438 mask = (1 << 2) | (1 << 0);
2439 if ((tmp8 & mask) != mask)
2443 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2446 if (!legacy_mode && pdev->irq) {
2449 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2450 IRQF_SHARED, drv_name, host);
2454 for (i = 0; i < 2; i++) {
2455 if (ata_port_is_dummy(host->ports[i]))
2457 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2459 } else if (legacy_mode) {
2460 if (!ata_port_is_dummy(host->ports[0])) {
2461 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2462 irq_handler, IRQF_SHARED,
2467 ata_port_desc(host->ports[0], "irq %d",
2468 ATA_PRIMARY_IRQ(pdev));
2471 if (!ata_port_is_dummy(host->ports[1])) {
2472 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2473 irq_handler, IRQF_SHARED,
2478 ata_port_desc(host->ports[1], "irq %d",
2479 ATA_SECONDARY_IRQ(pdev));
2483 rc = ata_host_register(host, sht);
2486 devres_remove_group(dev, NULL);
2488 devres_release_group(dev, NULL);
2492 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2494 static const struct ata_port_info *ata_sff_find_valid_pi(
2495 const struct ata_port_info * const *ppi)
2499 /* look up the first valid port_info */
2500 for (i = 0; i < 2 && ppi[i]; i++)
2501 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2507 static int ata_pci_init_one(struct pci_dev *pdev,
2508 const struct ata_port_info * const *ppi,
2509 struct scsi_host_template *sht, void *host_priv,
2510 int hflags, bool bmdma)
2512 struct device *dev = &pdev->dev;
2513 const struct ata_port_info *pi;
2514 struct ata_host *host = NULL;
2519 pi = ata_sff_find_valid_pi(ppi);
2521 dev_err(&pdev->dev, "no valid port_info specified\n");
2525 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2528 rc = pcim_enable_device(pdev);
2532 #ifdef CONFIG_ATA_BMDMA
2534 /* prepare and activate BMDMA host */
2535 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2538 /* prepare and activate SFF host */
2539 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2542 host->private_data = host_priv;
2543 host->flags |= hflags;
2545 #ifdef CONFIG_ATA_BMDMA
2547 pci_set_master(pdev);
2548 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2551 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2554 devres_remove_group(&pdev->dev, NULL);
2556 devres_release_group(&pdev->dev, NULL);
2562 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2563 * @pdev: Controller to be initialized
2564 * @ppi: array of port_info, must be enough for two ports
2565 * @sht: scsi_host_template to use when registering the host
2566 * @host_priv: host private_data
2567 * @hflag: host flags
2569 * This is a helper function which can be called from a driver's
2570 * xxx_init_one() probe function if the hardware uses traditional
2571 * IDE taskfile registers and is PIO only.
2574 * Nobody makes a single channel controller that appears solely as
2575 * the secondary legacy port on PCI.
2578 * Inherited from PCI layer (may sleep).
2581 * Zero on success, negative on errno-based value on error.
2583 int ata_pci_sff_init_one(struct pci_dev *pdev,
2584 const struct ata_port_info * const *ppi,
2585 struct scsi_host_template *sht, void *host_priv, int hflag)
2587 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2589 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2591 #endif /* CONFIG_PCI */
2597 #ifdef CONFIG_ATA_BMDMA
2599 const struct ata_port_operations ata_bmdma_port_ops = {
2600 .inherits = &ata_sff_port_ops,
2602 .error_handler = ata_bmdma_error_handler,
2603 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2605 .qc_prep = ata_bmdma_qc_prep,
2606 .qc_issue = ata_bmdma_qc_issue,
2608 .sff_irq_clear = ata_bmdma_irq_clear,
2609 .bmdma_setup = ata_bmdma_setup,
2610 .bmdma_start = ata_bmdma_start,
2611 .bmdma_stop = ata_bmdma_stop,
2612 .bmdma_status = ata_bmdma_status,
2614 .port_start = ata_bmdma_port_start,
2616 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2618 const struct ata_port_operations ata_bmdma32_port_ops = {
2619 .inherits = &ata_bmdma_port_ops,
2621 .sff_data_xfer = ata_sff_data_xfer32,
2622 .port_start = ata_bmdma_port_start32,
2624 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2627 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2628 * @qc: Metadata associated with taskfile to be transferred
2630 * Fill PCI IDE PRD (scatter-gather) table with segments
2631 * associated with the current disk command.
2634 * spin_lock_irqsave(host lock)
2637 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2639 struct ata_port *ap = qc->ap;
2640 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2641 struct scatterlist *sg;
2642 unsigned int si, pi;
2645 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2649 /* determine if physical DMA addr spans 64K boundary.
2650 * Note h/w doesn't support 64-bit, so we unconditionally
2651 * truncate dma_addr_t to u32.
2653 addr = (u32) sg_dma_address(sg);
2654 sg_len = sg_dma_len(sg);
2657 offset = addr & 0xffff;
2659 if ((offset + sg_len) > 0x10000)
2660 len = 0x10000 - offset;
2662 prd[pi].addr = cpu_to_le32(addr);
2663 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2664 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2672 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2676 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2677 * @qc: Metadata associated with taskfile to be transferred
2679 * Fill PCI IDE PRD (scatter-gather) table with segments
2680 * associated with the current disk command. Perform the fill
2681 * so that we avoid writing any length 64K records for
2682 * controllers that don't follow the spec.
2685 * spin_lock_irqsave(host lock)
2688 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2690 struct ata_port *ap = qc->ap;
2691 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2692 struct scatterlist *sg;
2693 unsigned int si, pi;
2696 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2698 u32 sg_len, len, blen;
2700 /* determine if physical DMA addr spans 64K boundary.
2701 * Note h/w doesn't support 64-bit, so we unconditionally
2702 * truncate dma_addr_t to u32.
2704 addr = (u32) sg_dma_address(sg);
2705 sg_len = sg_dma_len(sg);
2708 offset = addr & 0xffff;
2710 if ((offset + sg_len) > 0x10000)
2711 len = 0x10000 - offset;
2713 blen = len & 0xffff;
2714 prd[pi].addr = cpu_to_le32(addr);
2716 /* Some PATA chipsets like the CS5530 can't
2717 cope with 0x0000 meaning 64K as the spec
2719 prd[pi].flags_len = cpu_to_le32(0x8000);
2721 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2723 prd[pi].flags_len = cpu_to_le32(blen);
2724 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2732 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2736 * ata_bmdma_qc_prep - Prepare taskfile for submission
2737 * @qc: Metadata associated with taskfile to be prepared
2739 * Prepare ATA taskfile for submission.
2742 * spin_lock_irqsave(host lock)
2744 enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2746 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2749 ata_bmdma_fill_sg(qc);
2753 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2756 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2757 * @qc: Metadata associated with taskfile to be prepared
2759 * Prepare ATA taskfile for submission.
2762 * spin_lock_irqsave(host lock)
2764 enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2766 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2769 ata_bmdma_fill_sg_dumb(qc);
2773 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2776 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2777 * @qc: command to issue to device
2779 * This function issues a PIO, NODATA or DMA command to a
2780 * SFF/BMDMA controller. PIO and NODATA are handled by
2781 * ata_sff_qc_issue().
2784 * spin_lock_irqsave(host lock)
2787 * Zero on success, AC_ERR_* mask on failure
2789 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2791 struct ata_port *ap = qc->ap;
2792 struct ata_link *link = qc->dev->link;
2794 /* defer PIO handling to sff_qc_issue */
2795 if (!ata_is_dma(qc->tf.protocol))
2796 return ata_sff_qc_issue(qc);
2798 /* select the device */
2799 ata_dev_select(ap, qc->dev->devno, 1, 0);
2801 /* start the command */
2802 switch (qc->tf.protocol) {
2804 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2806 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2807 ap->ops->bmdma_setup(qc); /* set up bmdma */
2808 ap->ops->bmdma_start(qc); /* initiate bmdma */
2809 ap->hsm_task_state = HSM_ST_LAST;
2812 case ATAPI_PROT_DMA:
2813 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2815 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2816 ap->ops->bmdma_setup(qc); /* set up bmdma */
2817 ap->hsm_task_state = HSM_ST_FIRST;
2819 /* send cdb by polling if no cdb interrupt */
2820 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2821 ata_sff_queue_pio_task(link, 0);
2826 return AC_ERR_SYSTEM;
2831 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2834 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2835 * @ap: Port on which interrupt arrived (possibly...)
2836 * @qc: Taskfile currently active in engine
2838 * Handle port interrupt for given queued command.
2841 * spin_lock_irqsave(host lock)
2844 * One if interrupt was handled, zero if not (shared irq).
2846 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2848 struct ata_eh_info *ehi = &ap->link.eh_info;
2850 bool bmdma_stopped = false;
2851 unsigned int handled;
2853 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2854 /* check status of DMA engine */
2855 host_stat = ap->ops->bmdma_status(ap);
2856 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2858 /* if it's not our irq... */
2859 if (!(host_stat & ATA_DMA_INTR))
2860 return ata_sff_idle_irq(ap);
2862 /* before we do anything else, clear DMA-Start bit */
2863 ap->ops->bmdma_stop(qc);
2864 bmdma_stopped = true;
2866 if (unlikely(host_stat & ATA_DMA_ERR)) {
2867 /* error when transferring data to/from memory */
2868 qc->err_mask |= AC_ERR_HOST_BUS;
2869 ap->hsm_task_state = HSM_ST_ERR;
2873 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2875 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2876 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2880 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2883 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2884 * @irq: irq line (unused)
2885 * @dev_instance: pointer to our ata_host information structure
2887 * Default interrupt handler for PCI IDE devices. Calls
2888 * ata_bmdma_port_intr() for each port that is not disabled.
2891 * Obtains host lock during operation.
2894 * IRQ_NONE or IRQ_HANDLED.
2896 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2898 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2900 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2903 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2904 * @ap: port to handle error for
2906 * Stock error handler for BMDMA controller. It can handle both
2907 * PATA and SATA controllers. Most BMDMA controllers should be
2908 * able to use this EH as-is or with some added handling before
2912 * Kernel thread context (may sleep)
2914 void ata_bmdma_error_handler(struct ata_port *ap)
2916 struct ata_queued_cmd *qc;
2917 unsigned long flags;
2920 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2921 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2924 /* reset PIO HSM and stop DMA engine */
2925 spin_lock_irqsave(ap->lock, flags);
2927 if (qc && ata_is_dma(qc->tf.protocol)) {
2930 host_stat = ap->ops->bmdma_status(ap);
2932 /* BMDMA controllers indicate host bus error by
2933 * setting DMA_ERR bit and timing out. As it wasn't
2934 * really a timeout event, adjust error mask and
2935 * cancel frozen state.
2937 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2938 qc->err_mask = AC_ERR_HOST_BUS;
2942 ap->ops->bmdma_stop(qc);
2944 /* if we're gonna thaw, make sure IRQ is clear */
2946 ap->ops->sff_check_status(ap);
2947 if (ap->ops->sff_irq_clear)
2948 ap->ops->sff_irq_clear(ap);
2952 spin_unlock_irqrestore(ap->lock, flags);
2955 ata_eh_thaw_port(ap);
2957 ata_sff_error_handler(ap);
2959 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2962 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2963 * @qc: internal command to clean up
2966 * Kernel thread context (may sleep)
2968 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2970 struct ata_port *ap = qc->ap;
2971 unsigned long flags;
2973 if (ata_is_dma(qc->tf.protocol)) {
2974 spin_lock_irqsave(ap->lock, flags);
2975 ap->ops->bmdma_stop(qc);
2976 spin_unlock_irqrestore(ap->lock, flags);
2979 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2982 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2983 * @ap: Port associated with this ATA transaction.
2985 * Clear interrupt and error flags in DMA status register.
2987 * May be used as the irq_clear() entry in ata_port_operations.
2990 * spin_lock_irqsave(host lock)
2992 void ata_bmdma_irq_clear(struct ata_port *ap)
2994 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2999 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
3001 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
3004 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3005 * @qc: Info associated with this ATA transaction.
3008 * spin_lock_irqsave(host lock)
3010 void ata_bmdma_setup(struct ata_queued_cmd *qc)
3012 struct ata_port *ap = qc->ap;
3013 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3016 /* load PRD table addr. */
3017 mb(); /* make sure PRD table writes are visible to controller */
3018 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3020 /* specify data direction, triple-check start bit is clear */
3021 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3022 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3024 dmactl |= ATA_DMA_WR;
3025 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3027 /* issue r/w command */
3028 ap->ops->sff_exec_command(ap, &qc->tf);
3030 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
3033 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3034 * @qc: Info associated with this ATA transaction.
3037 * spin_lock_irqsave(host lock)
3039 void ata_bmdma_start(struct ata_queued_cmd *qc)
3041 struct ata_port *ap = qc->ap;
3044 /* start host DMA transaction */
3045 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3046 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3048 /* Strictly, one may wish to issue an ioread8() here, to
3049 * flush the mmio write. However, control also passes
3050 * to the hardware at this point, and it will interrupt
3051 * us when we are to resume control. So, in effect,
3052 * we don't care when the mmio write flushes.
3053 * Further, a read of the DMA status register _immediately_
3054 * following the write may not be what certain flaky hardware
3055 * is expected, so I think it is best to not add a readb()
3056 * without first all the MMIO ATA cards/mobos.
3057 * Or maybe I'm just being paranoid.
3059 * FIXME: The posting of this write means I/O starts are
3060 * unnecessarily delayed for MMIO
3063 EXPORT_SYMBOL_GPL(ata_bmdma_start);
3066 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3067 * @qc: Command we are ending DMA for
3069 * Clears the ATA_DMA_START flag in the dma control register
3071 * May be used as the bmdma_stop() entry in ata_port_operations.
3074 * spin_lock_irqsave(host lock)
3076 void ata_bmdma_stop(struct ata_queued_cmd *qc)
3078 struct ata_port *ap = qc->ap;
3079 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3081 /* clear start/stop bit */
3082 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3083 mmio + ATA_DMA_CMD);
3085 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3086 ata_sff_dma_pause(ap);
3088 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3091 * ata_bmdma_status - Read PCI IDE BMDMA status
3092 * @ap: Port associated with this ATA transaction.
3094 * Read and return BMDMA status register.
3096 * May be used as the bmdma_status() entry in ata_port_operations.
3099 * spin_lock_irqsave(host lock)
3101 u8 ata_bmdma_status(struct ata_port *ap)
3103 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3105 EXPORT_SYMBOL_GPL(ata_bmdma_status);
3109 * ata_bmdma_port_start - Set port up for bmdma.
3110 * @ap: Port to initialize
3112 * Called just after data structures for each port are
3113 * initialized. Allocates space for PRD table.
3115 * May be used as the port_start() entry in ata_port_operations.
3118 * Inherited from caller.
3120 int ata_bmdma_port_start(struct ata_port *ap)
3122 if (ap->mwdma_mask || ap->udma_mask) {
3124 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3125 &ap->bmdma_prd_dma, GFP_KERNEL);
3132 EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3135 * ata_bmdma_port_start32 - Set port up for dma.
3136 * @ap: Port to initialize
3138 * Called just after data structures for each port are
3139 * initialized. Enables 32bit PIO and allocates space for PRD
3142 * May be used as the port_start() entry in ata_port_operations for
3143 * devices that are capable of 32bit PIO.
3146 * Inherited from caller.
3148 int ata_bmdma_port_start32(struct ata_port *ap)
3150 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3151 return ata_bmdma_port_start(ap);
3153 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3158 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3161 * Some PCI ATA devices report simplex mode but in fact can be told to
3162 * enter non simplex mode. This implements the necessary logic to
3163 * perform the task on such devices. Calling it on other devices will
3164 * have -undefined- behaviour.
3166 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3168 unsigned long bmdma = pci_resource_start(pdev, 4);
3174 simplex = inb(bmdma + 0x02);
3175 outb(simplex & 0x60, bmdma + 0x02);
3176 simplex = inb(bmdma + 0x02);
3181 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3183 static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3187 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3189 for (i = 0; i < 2; i++) {
3190 host->ports[i]->mwdma_mask = 0;
3191 host->ports[i]->udma_mask = 0;
3196 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3197 * @host: target ATA host
3199 * Acquire PCI BMDMA resources and initialize @host accordingly.
3202 * Inherited from calling layer (may sleep).
3204 void ata_pci_bmdma_init(struct ata_host *host)
3206 struct device *gdev = host->dev;
3207 struct pci_dev *pdev = to_pci_dev(gdev);
3210 /* No BAR4 allocation: No DMA */
3211 if (pci_resource_start(pdev, 4) == 0) {
3212 ata_bmdma_nodma(host, "BAR4 is zero");
3217 * Some controllers require BMDMA region to be initialized
3218 * even if DMA is not in use to clear IRQ status via
3219 * ->sff_irq_clear method. Try to initialize bmdma_addr
3220 * regardless of dma masks.
3222 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
3224 ata_bmdma_nodma(host, "failed to set dma mask");
3226 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
3228 ata_bmdma_nodma(host,
3229 "failed to set consistent dma mask");
3232 /* request and iomap DMA region */
3233 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3235 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3238 host->iomap = pcim_iomap_table(pdev);
3240 for (i = 0; i < 2; i++) {
3241 struct ata_port *ap = host->ports[i];
3242 void __iomem *bmdma = host->iomap[4] + 8 * i;
3244 if (ata_port_is_dummy(ap))
3247 ap->ioaddr.bmdma_addr = bmdma;
3248 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3249 (ioread8(bmdma + 2) & 0x80))
3250 host->flags |= ATA_HOST_SIMPLEX;
3252 ata_port_desc(ap, "bmdma 0x%llx",
3253 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3256 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3259 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3260 * @pdev: target PCI device
3261 * @ppi: array of port_info, must be enough for two ports
3262 * @r_host: out argument for the initialized ATA host
3264 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3265 * resources and initialize it accordingly in one go.
3268 * Inherited from calling layer (may sleep).
3271 * 0 on success, -errno otherwise.
3273 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3274 const struct ata_port_info * const * ppi,
3275 struct ata_host **r_host)
3279 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3283 ata_pci_bmdma_init(*r_host);
3286 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3289 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3290 * @pdev: Controller to be initialized
3291 * @ppi: array of port_info, must be enough for two ports
3292 * @sht: scsi_host_template to use when registering the host
3293 * @host_priv: host private_data
3294 * @hflags: host flags
3296 * This function is similar to ata_pci_sff_init_one() but also
3297 * takes care of BMDMA initialization.
3300 * Inherited from PCI layer (may sleep).
3303 * Zero on success, negative on errno-based value on error.
3305 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3306 const struct ata_port_info * const * ppi,
3307 struct scsi_host_template *sht, void *host_priv,
3310 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3312 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3314 #endif /* CONFIG_PCI */
3315 #endif /* CONFIG_ATA_BMDMA */
3318 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3319 * @ap: Port to initialize
3321 * Called on port allocation to initialize SFF/BMDMA specific
3327 void ata_sff_port_init(struct ata_port *ap)
3329 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3330 ap->ctl = ATA_DEVCTL_OBS;
3331 ap->last_ctl = 0xFF;
3334 int __init ata_sff_init(void)
3336 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3343 void ata_sff_exit(void)
3345 destroy_workqueue(ata_sff_wq);