2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/nospec.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include <linux/pci.h>
51 static int ahci_skip_host_reset;
53 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
55 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
58 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
61 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
63 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
66 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
71 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93 static void ahci_dev_config(struct ata_device *dev);
95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98 static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100 static void ahci_init_sw_activity(struct ata_link *link);
102 static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112 static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
115 static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
117 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
127 struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
136 &dev_attr_em_message_supported,
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
141 struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148 struct ata_port_operations ahci_ops = {
149 .inherits = &sata_pmp_port_ops,
151 .qc_defer = ahci_pmp_qc_defer,
152 .qc_prep = ahci_qc_prep,
153 .qc_issue = ahci_qc_issue,
154 .qc_fill_rtf = ahci_qc_fill_rtf,
156 .freeze = ahci_freeze,
158 .softreset = ahci_softreset,
159 .hardreset = ahci_hardreset,
160 .postreset = ahci_postreset,
161 .pmp_softreset = ahci_softreset,
162 .error_handler = ahci_error_handler,
163 .post_internal_cmd = ahci_post_internal_cmd,
164 .dev_config = ahci_dev_config,
166 .scr_read = ahci_scr_read,
167 .scr_write = ahci_scr_write,
168 .pmp_attach = ahci_pmp_attach,
169 .pmp_detach = ahci_pmp_detach,
171 .set_lpm = ahci_set_lpm,
172 .em_show = ahci_led_show,
173 .em_store = ahci_led_store,
174 .sw_activity_show = ahci_activity_show,
175 .sw_activity_store = ahci_activity_store,
176 .transmit_led_message = ahci_transmit_led_message,
178 .port_suspend = ahci_port_suspend,
179 .port_resume = ahci_port_resume,
181 .port_start = ahci_port_start,
182 .port_stop = ahci_port_stop,
184 EXPORT_SYMBOL_GPL(ahci_ops);
186 struct ata_port_operations ahci_pmp_retry_srst_ops = {
187 .inherits = &ahci_ops,
188 .softreset = ahci_pmp_retry_softreset,
190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192 static bool ahci_em_messages __read_mostly = true;
193 module_param(ahci_em_messages, bool, 0444);
194 /* add other LED protocol types when they become supported */
195 MODULE_PARM_DESC(ahci_em_messages,
196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
198 /* device sleep idle timeout in ms */
199 static int devslp_idle_timeout __read_mostly = 1000;
200 module_param(devslp_idle_timeout, int, 0644);
201 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
203 static void ahci_enable_ahci(void __iomem *mmio)
208 /* turn on AHCI_EN */
209 tmp = readl(mmio + HOST_CTL);
210 if (tmp & HOST_AHCI_EN)
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
216 for (i = 0; i < 5; i++) {
218 writel(tmp, mmio + HOST_CTL);
219 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
220 if (tmp & HOST_AHCI_EN)
229 * ahci_rpm_get_port - Make sure the port is powered on
230 * @ap: Port to power on
232 * Whenever there is need to access the AHCI host registers outside of
233 * normal execution paths, call this function to make sure the host is
234 * actually powered on.
236 static int ahci_rpm_get_port(struct ata_port *ap)
238 return pm_runtime_get_sync(ap->dev);
242 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
243 * @ap: Port to power down
245 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
246 * if it has no more active users.
248 static void ahci_rpm_put_port(struct ata_port *ap)
250 pm_runtime_put(ap->dev);
253 static ssize_t ahci_show_host_caps(struct device *dev,
254 struct device_attribute *attr, char *buf)
256 struct Scsi_Host *shost = class_to_shost(dev);
257 struct ata_port *ap = ata_shost_to_port(shost);
258 struct ahci_host_priv *hpriv = ap->host->private_data;
260 return sprintf(buf, "%x\n", hpriv->cap);
263 static ssize_t ahci_show_host_cap2(struct device *dev,
264 struct device_attribute *attr, char *buf)
266 struct Scsi_Host *shost = class_to_shost(dev);
267 struct ata_port *ap = ata_shost_to_port(shost);
268 struct ahci_host_priv *hpriv = ap->host->private_data;
270 return sprintf(buf, "%x\n", hpriv->cap2);
273 static ssize_t ahci_show_host_version(struct device *dev,
274 struct device_attribute *attr, char *buf)
276 struct Scsi_Host *shost = class_to_shost(dev);
277 struct ata_port *ap = ata_shost_to_port(shost);
278 struct ahci_host_priv *hpriv = ap->host->private_data;
280 return sprintf(buf, "%x\n", hpriv->version);
283 static ssize_t ahci_show_port_cmd(struct device *dev,
284 struct device_attribute *attr, char *buf)
286 struct Scsi_Host *shost = class_to_shost(dev);
287 struct ata_port *ap = ata_shost_to_port(shost);
288 void __iomem *port_mmio = ahci_port_base(ap);
291 ahci_rpm_get_port(ap);
292 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
293 ahci_rpm_put_port(ap);
298 static ssize_t ahci_read_em_buffer(struct device *dev,
299 struct device_attribute *attr, char *buf)
301 struct Scsi_Host *shost = class_to_shost(dev);
302 struct ata_port *ap = ata_shost_to_port(shost);
303 struct ahci_host_priv *hpriv = ap->host->private_data;
304 void __iomem *mmio = hpriv->mmio;
305 void __iomem *em_mmio = mmio + hpriv->em_loc;
311 ahci_rpm_get_port(ap);
312 spin_lock_irqsave(ap->lock, flags);
314 em_ctl = readl(mmio + HOST_EM_CTL);
315 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
316 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
317 spin_unlock_irqrestore(ap->lock, flags);
318 ahci_rpm_put_port(ap);
322 if (!(em_ctl & EM_CTL_MR)) {
323 spin_unlock_irqrestore(ap->lock, flags);
324 ahci_rpm_put_port(ap);
328 if (!(em_ctl & EM_CTL_SMB))
329 em_mmio += hpriv->em_buf_sz;
331 count = hpriv->em_buf_sz;
333 /* the count should not be larger than PAGE_SIZE */
334 if (count > PAGE_SIZE) {
335 if (printk_ratelimit())
337 "EM read buffer size too large: "
338 "buffer size %u, page size %lu\n",
339 hpriv->em_buf_sz, PAGE_SIZE);
343 for (i = 0; i < count; i += 4) {
344 msg = readl(em_mmio + i);
346 buf[i + 1] = (msg >> 8) & 0xff;
347 buf[i + 2] = (msg >> 16) & 0xff;
348 buf[i + 3] = (msg >> 24) & 0xff;
351 spin_unlock_irqrestore(ap->lock, flags);
352 ahci_rpm_put_port(ap);
357 static ssize_t ahci_store_em_buffer(struct device *dev,
358 struct device_attribute *attr,
359 const char *buf, size_t size)
361 struct Scsi_Host *shost = class_to_shost(dev);
362 struct ata_port *ap = ata_shost_to_port(shost);
363 struct ahci_host_priv *hpriv = ap->host->private_data;
364 void __iomem *mmio = hpriv->mmio;
365 void __iomem *em_mmio = mmio + hpriv->em_loc;
366 const unsigned char *msg_buf = buf;
371 /* check size validity */
372 if (!(ap->flags & ATA_FLAG_EM) ||
373 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
374 size % 4 || size > hpriv->em_buf_sz)
377 ahci_rpm_get_port(ap);
378 spin_lock_irqsave(ap->lock, flags);
380 em_ctl = readl(mmio + HOST_EM_CTL);
381 if (em_ctl & EM_CTL_TM) {
382 spin_unlock_irqrestore(ap->lock, flags);
383 ahci_rpm_put_port(ap);
387 for (i = 0; i < size; i += 4) {
388 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
389 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
390 writel(msg, em_mmio + i);
393 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
395 spin_unlock_irqrestore(ap->lock, flags);
396 ahci_rpm_put_port(ap);
401 static ssize_t ahci_show_em_supported(struct device *dev,
402 struct device_attribute *attr, char *buf)
404 struct Scsi_Host *shost = class_to_shost(dev);
405 struct ata_port *ap = ata_shost_to_port(shost);
406 struct ahci_host_priv *hpriv = ap->host->private_data;
407 void __iomem *mmio = hpriv->mmio;
410 ahci_rpm_get_port(ap);
411 em_ctl = readl(mmio + HOST_EM_CTL);
412 ahci_rpm_put_port(ap);
414 return sprintf(buf, "%s%s%s%s\n",
415 em_ctl & EM_CTL_LED ? "led " : "",
416 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
417 em_ctl & EM_CTL_SES ? "ses-2 " : "",
418 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
422 * ahci_save_initial_config - Save and fixup initial config values
423 * @dev: target AHCI device
424 * @hpriv: host private area to store config values
426 * Some registers containing configuration info might be setup by
427 * BIOS and might be cleared on reset. This function saves the
428 * initial values of those registers into @hpriv such that they
429 * can be restored after controller reset.
431 * If inconsistent, config values are fixed up by this function.
433 * If it is not set already this function sets hpriv->start_engine to
439 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
441 void __iomem *mmio = hpriv->mmio;
442 u32 cap, cap2, vers, port_map;
445 /* make sure AHCI mode is enabled before accessing CAP */
446 ahci_enable_ahci(mmio);
448 /* Values prefixed with saved_ are written back to host after
449 * reset. Values without are used for driver operation.
451 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
452 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
454 /* CAP2 register is only defined for AHCI 1.2 and later */
455 vers = readl(mmio + HOST_VERSION);
456 if ((vers >> 16) > 1 ||
457 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
458 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
460 hpriv->saved_cap2 = cap2 = 0;
462 /* some chips have errata preventing 64bit use */
463 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
464 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
468 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
469 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
470 cap &= ~HOST_CAP_NCQ;
473 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
474 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
478 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
479 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
480 cap &= ~HOST_CAP_PMP;
483 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
485 "controller can't do SNTF, turning off CAP_SNTF\n");
486 cap &= ~HOST_CAP_SNTF;
489 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
491 "controller can't do DEVSLP, turning off\n");
492 cap2 &= ~HOST_CAP2_SDS;
493 cap2 &= ~HOST_CAP2_SADM;
496 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
497 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
501 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
502 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
503 cap &= ~HOST_CAP_FBS;
506 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
507 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
508 port_map, hpriv->force_port_map);
509 port_map = hpriv->force_port_map;
510 hpriv->saved_port_map = port_map;
513 if (hpriv->mask_port_map) {
514 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
516 port_map & hpriv->mask_port_map);
517 port_map &= hpriv->mask_port_map;
520 /* cross check port_map and cap.n_ports */
524 for (i = 0; i < AHCI_MAX_PORTS; i++)
525 if (port_map & (1 << i))
528 /* If PI has more ports than n_ports, whine, clear
529 * port_map and let it be generated from n_ports.
531 if (map_ports > ahci_nr_ports(cap)) {
533 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
534 port_map, ahci_nr_ports(cap));
539 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
540 if (!port_map && vers < 0x10300) {
541 port_map = (1 << ahci_nr_ports(cap)) - 1;
542 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
544 /* write the fixed up value to the PI register */
545 hpriv->saved_port_map = port_map;
548 /* record values to use during operation */
551 hpriv->version = readl(mmio + HOST_VERSION);
552 hpriv->port_map = port_map;
554 if (!hpriv->start_engine)
555 hpriv->start_engine = ahci_start_engine;
557 if (!hpriv->irq_handler)
558 hpriv->irq_handler = ahci_single_level_irq_intr;
560 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
563 * ahci_restore_initial_config - Restore initial config
564 * @host: target ATA host
566 * Restore initial config stored by ahci_save_initial_config().
571 static void ahci_restore_initial_config(struct ata_host *host)
573 struct ahci_host_priv *hpriv = host->private_data;
574 void __iomem *mmio = hpriv->mmio;
576 writel(hpriv->saved_cap, mmio + HOST_CAP);
577 if (hpriv->saved_cap2)
578 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
579 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
580 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
583 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
585 static const int offset[] = {
586 [SCR_STATUS] = PORT_SCR_STAT,
587 [SCR_CONTROL] = PORT_SCR_CTL,
588 [SCR_ERROR] = PORT_SCR_ERR,
589 [SCR_ACTIVE] = PORT_SCR_ACT,
590 [SCR_NOTIFICATION] = PORT_SCR_NTF,
592 struct ahci_host_priv *hpriv = ap->host->private_data;
594 if (sc_reg < ARRAY_SIZE(offset) &&
595 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
596 return offset[sc_reg];
600 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
602 void __iomem *port_mmio = ahci_port_base(link->ap);
603 int offset = ahci_scr_offset(link->ap, sc_reg);
606 *val = readl(port_mmio + offset);
612 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
614 void __iomem *port_mmio = ahci_port_base(link->ap);
615 int offset = ahci_scr_offset(link->ap, sc_reg);
618 writel(val, port_mmio + offset);
624 void ahci_start_engine(struct ata_port *ap)
626 void __iomem *port_mmio = ahci_port_base(ap);
630 tmp = readl(port_mmio + PORT_CMD);
631 tmp |= PORT_CMD_START;
632 writel(tmp, port_mmio + PORT_CMD);
633 readl(port_mmio + PORT_CMD); /* flush */
635 EXPORT_SYMBOL_GPL(ahci_start_engine);
637 int ahci_stop_engine(struct ata_port *ap)
639 void __iomem *port_mmio = ahci_port_base(ap);
640 struct ahci_host_priv *hpriv = ap->host->private_data;
644 * On some controllers, stopping a port's DMA engine while the port
645 * is in ALPM state (partial or slumber) results in failures on
646 * subsequent DMA engine starts. For those controllers, put the
647 * port back in active state before stopping its DMA engine.
649 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
650 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
651 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
652 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
656 tmp = readl(port_mmio + PORT_CMD);
658 /* check if the HBA is idle */
659 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
662 /* setting HBA to idle */
663 tmp &= ~PORT_CMD_START;
664 writel(tmp, port_mmio + PORT_CMD);
666 /* wait for engine to stop. This could be as long as 500 msec */
667 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
668 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
669 if (tmp & PORT_CMD_LIST_ON)
674 EXPORT_SYMBOL_GPL(ahci_stop_engine);
676 void ahci_start_fis_rx(struct ata_port *ap)
678 void __iomem *port_mmio = ahci_port_base(ap);
679 struct ahci_host_priv *hpriv = ap->host->private_data;
680 struct ahci_port_priv *pp = ap->private_data;
683 /* set FIS registers */
684 if (hpriv->cap & HOST_CAP_64)
685 writel((pp->cmd_slot_dma >> 16) >> 16,
686 port_mmio + PORT_LST_ADDR_HI);
687 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
689 if (hpriv->cap & HOST_CAP_64)
690 writel((pp->rx_fis_dma >> 16) >> 16,
691 port_mmio + PORT_FIS_ADDR_HI);
692 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
694 /* enable FIS reception */
695 tmp = readl(port_mmio + PORT_CMD);
696 tmp |= PORT_CMD_FIS_RX;
697 writel(tmp, port_mmio + PORT_CMD);
700 readl(port_mmio + PORT_CMD);
702 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
704 static int ahci_stop_fis_rx(struct ata_port *ap)
706 void __iomem *port_mmio = ahci_port_base(ap);
709 /* disable FIS reception */
710 tmp = readl(port_mmio + PORT_CMD);
711 tmp &= ~PORT_CMD_FIS_RX;
712 writel(tmp, port_mmio + PORT_CMD);
714 /* wait for completion, spec says 500ms, give it 1000 */
715 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
716 PORT_CMD_FIS_ON, 10, 1000);
717 if (tmp & PORT_CMD_FIS_ON)
723 static void ahci_power_up(struct ata_port *ap)
725 struct ahci_host_priv *hpriv = ap->host->private_data;
726 void __iomem *port_mmio = ahci_port_base(ap);
729 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
732 if (hpriv->cap & HOST_CAP_SSS) {
733 cmd |= PORT_CMD_SPIN_UP;
734 writel(cmd, port_mmio + PORT_CMD);
738 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
741 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
744 struct ata_port *ap = link->ap;
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746 struct ahci_port_priv *pp = ap->private_data;
747 void __iomem *port_mmio = ahci_port_base(ap);
749 if (policy != ATA_LPM_MAX_POWER) {
750 /* wakeup flag only applies to the max power policy */
751 hints &= ~ATA_LPM_WAKE_ONLY;
754 * Disable interrupts on Phy Ready. This keeps us from
755 * getting woken up due to spurious phy ready
758 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
759 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
761 sata_link_scr_lpm(link, policy, false);
764 if (hpriv->cap & HOST_CAP_ALPM) {
765 u32 cmd = readl(port_mmio + PORT_CMD);
767 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
768 if (!(hints & ATA_LPM_WAKE_ONLY))
769 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
770 cmd |= PORT_CMD_ICC_ACTIVE;
772 writel(cmd, port_mmio + PORT_CMD);
773 readl(port_mmio + PORT_CMD);
775 /* wait 10ms to be sure we've come out of LPM state */
778 if (hints & ATA_LPM_WAKE_ONLY)
781 cmd |= PORT_CMD_ALPE;
782 if (policy == ATA_LPM_MIN_POWER)
785 /* write out new cmd value */
786 writel(cmd, port_mmio + PORT_CMD);
790 /* set aggressive device sleep */
791 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
792 (hpriv->cap2 & HOST_CAP2_SADM) &&
793 (link->device->flags & ATA_DFLAG_DEVSLP)) {
794 if (policy == ATA_LPM_MIN_POWER)
795 ahci_set_aggressive_devslp(ap, true);
797 ahci_set_aggressive_devslp(ap, false);
800 if (policy == ATA_LPM_MAX_POWER) {
801 sata_link_scr_lpm(link, policy, false);
803 /* turn PHYRDY IRQ back on */
804 pp->intr_mask |= PORT_IRQ_PHYRDY;
805 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
812 static void ahci_power_down(struct ata_port *ap)
814 struct ahci_host_priv *hpriv = ap->host->private_data;
815 void __iomem *port_mmio = ahci_port_base(ap);
818 if (!(hpriv->cap & HOST_CAP_SSS))
821 /* put device into listen mode, first set PxSCTL.DET to 0 */
822 scontrol = readl(port_mmio + PORT_SCR_CTL);
824 writel(scontrol, port_mmio + PORT_SCR_CTL);
826 /* then set PxCMD.SUD to 0 */
827 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
828 cmd &= ~PORT_CMD_SPIN_UP;
829 writel(cmd, port_mmio + PORT_CMD);
833 static void ahci_start_port(struct ata_port *ap)
835 struct ahci_host_priv *hpriv = ap->host->private_data;
836 struct ahci_port_priv *pp = ap->private_data;
837 struct ata_link *link;
838 struct ahci_em_priv *emp;
842 /* enable FIS reception */
843 ahci_start_fis_rx(ap);
846 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
847 hpriv->start_engine(ap);
850 if (ap->flags & ATA_FLAG_EM) {
851 ata_for_each_link(link, ap, EDGE) {
852 emp = &pp->em_priv[link->pmp];
854 /* EM Transmit bit maybe busy during init */
855 for (i = 0; i < EM_MAX_RETRY; i++) {
856 rc = ap->ops->transmit_led_message(ap,
860 * If busy, give a breather but do not
861 * release EH ownership by using msleep()
862 * instead of ata_msleep(). EM Transmit
863 * bit is busy for the whole host and
864 * releasing ownership will cause other
865 * ports to fail the same way.
875 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
876 ata_for_each_link(link, ap, EDGE)
877 ahci_init_sw_activity(link);
881 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
886 rc = ahci_stop_engine(ap);
888 *emsg = "failed to stop engine";
892 /* disable FIS reception */
893 rc = ahci_stop_fis_rx(ap);
895 *emsg = "failed stop FIS RX";
902 int ahci_reset_controller(struct ata_host *host)
904 struct ahci_host_priv *hpriv = host->private_data;
905 void __iomem *mmio = hpriv->mmio;
908 /* we must be in AHCI mode, before using anything
909 * AHCI-specific, such as HOST_RESET.
911 ahci_enable_ahci(mmio);
913 /* global controller reset */
914 if (!ahci_skip_host_reset) {
915 tmp = readl(mmio + HOST_CTL);
916 if ((tmp & HOST_RESET) == 0) {
917 writel(tmp | HOST_RESET, mmio + HOST_CTL);
918 readl(mmio + HOST_CTL); /* flush */
922 * to perform host reset, OS should set HOST_RESET
923 * and poll until this bit is read to be "0".
924 * reset must complete within 1 second, or
925 * the hardware should be considered fried.
927 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
928 HOST_RESET, 10, 1000);
930 if (tmp & HOST_RESET) {
931 dev_err(host->dev, "controller reset failed (0x%x)\n",
936 /* turn on AHCI mode */
937 ahci_enable_ahci(mmio);
939 /* Some registers might be cleared on reset. Restore
942 ahci_restore_initial_config(host);
944 dev_info(host->dev, "skipping global host reset\n");
948 EXPORT_SYMBOL_GPL(ahci_reset_controller);
950 static void ahci_sw_activity(struct ata_link *link)
952 struct ata_port *ap = link->ap;
953 struct ahci_port_priv *pp = ap->private_data;
954 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
956 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
960 if (!timer_pending(&emp->timer))
961 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
964 static void ahci_sw_activity_blink(unsigned long arg)
966 struct ata_link *link = (struct ata_link *)arg;
967 struct ata_port *ap = link->ap;
968 struct ahci_port_priv *pp = ap->private_data;
969 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
970 unsigned long led_message = emp->led_state;
971 u32 activity_led_state;
974 led_message &= EM_MSG_LED_VALUE;
975 led_message |= ap->port_no | (link->pmp << 8);
977 /* check to see if we've had activity. If so,
978 * toggle state of LED and reset timer. If not,
979 * turn LED to desired idle state.
981 spin_lock_irqsave(ap->lock, flags);
982 if (emp->saved_activity != emp->activity) {
983 emp->saved_activity = emp->activity;
984 /* get the current LED state */
985 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
987 if (activity_led_state)
988 activity_led_state = 0;
990 activity_led_state = 1;
992 /* clear old state */
993 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
996 led_message |= (activity_led_state << 16);
997 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1000 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1001 if (emp->blink_policy == BLINK_OFF)
1002 led_message |= (1 << 16);
1004 spin_unlock_irqrestore(ap->lock, flags);
1005 ap->ops->transmit_led_message(ap, led_message, 4);
1008 static void ahci_init_sw_activity(struct ata_link *link)
1010 struct ata_port *ap = link->ap;
1011 struct ahci_port_priv *pp = ap->private_data;
1012 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1014 /* init activity stats, setup timer */
1015 emp->saved_activity = emp->activity = 0;
1016 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1018 /* check our blink policy and set flag for link if it's enabled */
1019 if (emp->blink_policy)
1020 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1023 int ahci_reset_em(struct ata_host *host)
1025 struct ahci_host_priv *hpriv = host->private_data;
1026 void __iomem *mmio = hpriv->mmio;
1029 em_ctl = readl(mmio + HOST_EM_CTL);
1030 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1033 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1036 EXPORT_SYMBOL_GPL(ahci_reset_em);
1038 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1041 struct ahci_host_priv *hpriv = ap->host->private_data;
1042 struct ahci_port_priv *pp = ap->private_data;
1043 void __iomem *mmio = hpriv->mmio;
1045 u32 message[] = {0, 0};
1046 unsigned long flags;
1048 struct ahci_em_priv *emp;
1050 /* get the slot number from the message */
1051 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1052 if (pmp < EM_MAX_SLOTS)
1053 emp = &pp->em_priv[pmp];
1057 ahci_rpm_get_port(ap);
1058 spin_lock_irqsave(ap->lock, flags);
1061 * if we are still busy transmitting a previous message,
1064 em_ctl = readl(mmio + HOST_EM_CTL);
1065 if (em_ctl & EM_CTL_TM) {
1066 spin_unlock_irqrestore(ap->lock, flags);
1067 ahci_rpm_put_port(ap);
1071 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1073 * create message header - this is all zero except for
1074 * the message size, which is 4 bytes.
1076 message[0] |= (4 << 8);
1078 /* ignore 0:4 of byte zero, fill in port info yourself */
1079 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1081 /* write message to EM_LOC */
1082 writel(message[0], mmio + hpriv->em_loc);
1083 writel(message[1], mmio + hpriv->em_loc+4);
1086 * tell hardware to transmit the message
1088 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1091 /* save off new led state for port/slot */
1092 emp->led_state = state;
1094 spin_unlock_irqrestore(ap->lock, flags);
1095 ahci_rpm_put_port(ap);
1100 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1102 struct ahci_port_priv *pp = ap->private_data;
1103 struct ata_link *link;
1104 struct ahci_em_priv *emp;
1107 ata_for_each_link(link, ap, EDGE) {
1108 emp = &pp->em_priv[link->pmp];
1109 rc += sprintf(buf, "%lx\n", emp->led_state);
1114 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1119 struct ahci_port_priv *pp = ap->private_data;
1120 struct ahci_em_priv *emp;
1122 if (kstrtouint(buf, 0, &state) < 0)
1125 /* get the slot number from the message */
1126 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1127 if (pmp < EM_MAX_SLOTS) {
1128 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1129 emp = &pp->em_priv[pmp];
1134 /* mask off the activity bits if we are in sw_activity
1135 * mode, user should turn off sw_activity before setting
1136 * activity led through em_message
1138 if (emp->blink_policy)
1139 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1141 return ap->ops->transmit_led_message(ap, state, size);
1144 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1146 struct ata_link *link = dev->link;
1147 struct ata_port *ap = link->ap;
1148 struct ahci_port_priv *pp = ap->private_data;
1149 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1150 u32 port_led_state = emp->led_state;
1152 /* save the desired Activity LED behavior */
1155 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1157 /* set the LED to OFF */
1158 port_led_state &= EM_MSG_LED_VALUE_OFF;
1159 port_led_state |= (ap->port_no | (link->pmp << 8));
1160 ap->ops->transmit_led_message(ap, port_led_state, 4);
1162 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1163 if (val == BLINK_OFF) {
1164 /* set LED to ON for idle */
1165 port_led_state &= EM_MSG_LED_VALUE_OFF;
1166 port_led_state |= (ap->port_no | (link->pmp << 8));
1167 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1168 ap->ops->transmit_led_message(ap, port_led_state, 4);
1171 emp->blink_policy = val;
1175 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1177 struct ata_link *link = dev->link;
1178 struct ata_port *ap = link->ap;
1179 struct ahci_port_priv *pp = ap->private_data;
1180 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1182 /* display the saved value of activity behavior for this
1185 return sprintf(buf, "%d\n", emp->blink_policy);
1188 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1189 int port_no, void __iomem *mmio,
1190 void __iomem *port_mmio)
1192 struct ahci_host_priv *hpriv = ap->host->private_data;
1193 const char *emsg = NULL;
1197 /* make sure port is not active */
1198 rc = ahci_deinit_port(ap, &emsg);
1200 dev_warn(dev, "%s (%d)\n", emsg, rc);
1203 tmp = readl(port_mmio + PORT_SCR_ERR);
1204 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1205 writel(tmp, port_mmio + PORT_SCR_ERR);
1207 /* clear port IRQ */
1208 tmp = readl(port_mmio + PORT_IRQ_STAT);
1209 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1211 writel(tmp, port_mmio + PORT_IRQ_STAT);
1213 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1215 /* mark esata ports */
1216 tmp = readl(port_mmio + PORT_CMD);
1217 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1218 ap->pflags |= ATA_PFLAG_EXTERNAL;
1221 void ahci_init_controller(struct ata_host *host)
1223 struct ahci_host_priv *hpriv = host->private_data;
1224 void __iomem *mmio = hpriv->mmio;
1226 void __iomem *port_mmio;
1229 for (i = 0; i < host->n_ports; i++) {
1230 struct ata_port *ap = host->ports[i];
1232 port_mmio = ahci_port_base(ap);
1233 if (ata_port_is_dummy(ap))
1236 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1239 tmp = readl(mmio + HOST_CTL);
1240 VPRINTK("HOST_CTL 0x%x\n", tmp);
1241 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1242 tmp = readl(mmio + HOST_CTL);
1243 VPRINTK("HOST_CTL 0x%x\n", tmp);
1245 EXPORT_SYMBOL_GPL(ahci_init_controller);
1247 static void ahci_dev_config(struct ata_device *dev)
1249 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1251 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1252 dev->max_sectors = 255;
1254 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1258 unsigned int ahci_dev_classify(struct ata_port *ap)
1260 void __iomem *port_mmio = ahci_port_base(ap);
1261 struct ata_taskfile tf;
1264 tmp = readl(port_mmio + PORT_SIG);
1265 tf.lbah = (tmp >> 24) & 0xff;
1266 tf.lbam = (tmp >> 16) & 0xff;
1267 tf.lbal = (tmp >> 8) & 0xff;
1268 tf.nsect = (tmp) & 0xff;
1270 return ata_dev_classify(&tf);
1272 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1274 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1277 dma_addr_t cmd_tbl_dma;
1279 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1281 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1282 pp->cmd_slot[tag].status = 0;
1283 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1284 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1286 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1288 int ahci_kick_engine(struct ata_port *ap)
1290 void __iomem *port_mmio = ahci_port_base(ap);
1291 struct ahci_host_priv *hpriv = ap->host->private_data;
1292 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1297 rc = ahci_stop_engine(ap);
1302 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1304 busy = status & (ATA_BUSY | ATA_DRQ);
1305 if (!busy && !sata_pmp_attached(ap)) {
1310 if (!(hpriv->cap & HOST_CAP_CLO)) {
1316 tmp = readl(port_mmio + PORT_CMD);
1317 tmp |= PORT_CMD_CLO;
1318 writel(tmp, port_mmio + PORT_CMD);
1321 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1322 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1323 if (tmp & PORT_CMD_CLO)
1326 /* restart engine */
1328 hpriv->start_engine(ap);
1331 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1333 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1334 struct ata_taskfile *tf, int is_cmd, u16 flags,
1335 unsigned long timeout_msec)
1337 const u32 cmd_fis_len = 5; /* five dwords */
1338 struct ahci_port_priv *pp = ap->private_data;
1339 void __iomem *port_mmio = ahci_port_base(ap);
1340 u8 *fis = pp->cmd_tbl;
1343 /* prep the command */
1344 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1345 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1347 /* set port value for softreset of Port Multiplier */
1348 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1349 tmp = readl(port_mmio + PORT_FBS);
1350 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1351 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1352 writel(tmp, port_mmio + PORT_FBS);
1353 pp->fbs_last_dev = pmp;
1357 writel(1, port_mmio + PORT_CMD_ISSUE);
1360 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1361 0x1, 0x1, 1, timeout_msec);
1363 ahci_kick_engine(ap);
1367 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1372 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1373 int pmp, unsigned long deadline,
1374 int (*check_ready)(struct ata_link *link))
1376 struct ata_port *ap = link->ap;
1377 struct ahci_host_priv *hpriv = ap->host->private_data;
1378 struct ahci_port_priv *pp = ap->private_data;
1379 const char *reason = NULL;
1380 unsigned long now, msecs;
1381 struct ata_taskfile tf;
1382 bool fbs_disabled = false;
1387 /* prepare for SRST (AHCI-1.1 10.4.1) */
1388 rc = ahci_kick_engine(ap);
1389 if (rc && rc != -EOPNOTSUPP)
1390 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1393 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1394 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1395 * that is attached to port multiplier.
1397 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1398 ahci_disable_fbs(ap);
1399 fbs_disabled = true;
1402 ata_tf_init(link->device, &tf);
1404 /* issue the first D2H Register FIS */
1407 if (time_after(deadline, now))
1408 msecs = jiffies_to_msecs(deadline - now);
1411 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1412 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1414 reason = "1st FIS failed";
1418 /* spec says at least 5us, but be generous and sleep for 1ms */
1421 /* issue the second D2H Register FIS */
1422 tf.ctl &= ~ATA_SRST;
1423 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1425 /* wait for link to become ready */
1426 rc = ata_wait_after_reset(link, deadline, check_ready);
1427 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1429 * Workaround for cases where link online status can't
1430 * be trusted. Treat device readiness timeout as link
1433 ata_link_info(link, "device not ready, treating as offline\n");
1434 *class = ATA_DEV_NONE;
1436 /* link occupied, -ENODEV too is an error */
1437 reason = "device not ready";
1440 *class = ahci_dev_classify(ap);
1442 /* re-enable FBS if disabled before */
1444 ahci_enable_fbs(ap);
1446 DPRINTK("EXIT, class=%u\n", *class);
1450 ata_link_err(link, "softreset failed (%s)\n", reason);
1454 int ahci_check_ready(struct ata_link *link)
1456 void __iomem *port_mmio = ahci_port_base(link->ap);
1457 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1459 return ata_check_ready(status);
1461 EXPORT_SYMBOL_GPL(ahci_check_ready);
1463 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1464 unsigned long deadline)
1466 int pmp = sata_srst_pmp(link);
1470 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1472 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1474 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1476 void __iomem *port_mmio = ahci_port_base(link->ap);
1477 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1478 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1481 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1482 * which can save timeout delay.
1484 if (irq_status & PORT_IRQ_BAD_PMP)
1487 return ata_check_ready(status);
1490 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1491 unsigned long deadline)
1493 struct ata_port *ap = link->ap;
1494 void __iomem *port_mmio = ahci_port_base(ap);
1495 int pmp = sata_srst_pmp(link);
1501 rc = ahci_do_softreset(link, class, pmp, deadline,
1502 ahci_bad_pmp_check_ready);
1505 * Soft reset fails with IPMS set when PMP is enabled but
1506 * SATA HDD/ODD is connected to SATA port, do soft reset
1510 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1511 if (irq_sts & PORT_IRQ_BAD_PMP) {
1513 "applying PMP SRST workaround "
1515 rc = ahci_do_softreset(link, class, 0, deadline,
1523 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1524 unsigned long deadline)
1526 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1527 struct ata_port *ap = link->ap;
1528 struct ahci_port_priv *pp = ap->private_data;
1529 struct ahci_host_priv *hpriv = ap->host->private_data;
1530 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1531 struct ata_taskfile tf;
1537 ahci_stop_engine(ap);
1539 /* clear D2H reception area to properly wait for D2H FIS */
1540 ata_tf_init(link->device, &tf);
1541 tf.command = ATA_BUSY;
1542 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1544 rc = sata_link_hardreset(link, timing, deadline, &online,
1547 hpriv->start_engine(ap);
1550 *class = ahci_dev_classify(ap);
1552 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1556 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1558 struct ata_port *ap = link->ap;
1559 void __iomem *port_mmio = ahci_port_base(ap);
1562 ata_std_postreset(link, class);
1564 /* Make sure port's ATAPI bit is set appropriately */
1565 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1566 if (*class == ATA_DEV_ATAPI)
1567 new_tmp |= PORT_CMD_ATAPI;
1569 new_tmp &= ~PORT_CMD_ATAPI;
1570 if (new_tmp != tmp) {
1571 writel(new_tmp, port_mmio + PORT_CMD);
1572 readl(port_mmio + PORT_CMD); /* flush */
1576 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1578 struct scatterlist *sg;
1579 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1585 * Next, the S/G list.
1587 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1588 dma_addr_t addr = sg_dma_address(sg);
1589 u32 sg_len = sg_dma_len(sg);
1591 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1592 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1593 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1599 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1601 struct ata_port *ap = qc->ap;
1602 struct ahci_port_priv *pp = ap->private_data;
1604 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1605 return ata_std_qc_defer(qc);
1607 return sata_pmp_qc_defer_cmd_switch(qc);
1610 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1612 struct ata_port *ap = qc->ap;
1613 struct ahci_port_priv *pp = ap->private_data;
1614 int is_atapi = ata_is_atapi(qc->tf.protocol);
1617 const u32 cmd_fis_len = 5; /* five dwords */
1618 unsigned int n_elem;
1621 * Fill in command table information. First, the header,
1622 * a SATA Register - Host to Device command FIS.
1624 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1626 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1628 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1629 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1633 if (qc->flags & ATA_QCFLAG_DMAMAP)
1634 n_elem = ahci_fill_sg(qc, cmd_tbl);
1637 * Fill in command slot information.
1639 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1640 if (qc->tf.flags & ATA_TFLAG_WRITE)
1641 opts |= AHCI_CMD_WRITE;
1643 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1645 ahci_fill_cmd_slot(pp, qc->tag, opts);
1650 static void ahci_fbs_dec_intr(struct ata_port *ap)
1652 struct ahci_port_priv *pp = ap->private_data;
1653 void __iomem *port_mmio = ahci_port_base(ap);
1654 u32 fbs = readl(port_mmio + PORT_FBS);
1658 BUG_ON(!pp->fbs_enabled);
1660 /* time to wait for DEC is not specified by AHCI spec,
1661 * add a retry loop for safety.
1663 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1664 fbs = readl(port_mmio + PORT_FBS);
1665 while ((fbs & PORT_FBS_DEC) && retries--) {
1667 fbs = readl(port_mmio + PORT_FBS);
1670 if (fbs & PORT_FBS_DEC)
1671 dev_err(ap->host->dev, "failed to clear device error\n");
1674 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1676 struct ahci_host_priv *hpriv = ap->host->private_data;
1677 struct ahci_port_priv *pp = ap->private_data;
1678 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1679 struct ata_link *link = NULL;
1680 struct ata_queued_cmd *active_qc;
1681 struct ata_eh_info *active_ehi;
1682 bool fbs_need_dec = false;
1685 /* determine active link with error */
1686 if (pp->fbs_enabled) {
1687 void __iomem *port_mmio = ahci_port_base(ap);
1688 u32 fbs = readl(port_mmio + PORT_FBS);
1689 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1691 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1692 link = &ap->pmp_link[pmp];
1693 fbs_need_dec = true;
1697 ata_for_each_link(link, ap, EDGE)
1698 if (ata_link_active(link))
1704 active_qc = ata_qc_from_tag(ap, link->active_tag);
1705 active_ehi = &link->eh_info;
1707 /* record irq stat */
1708 ata_ehi_clear_desc(host_ehi);
1709 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1711 /* AHCI needs SError cleared; otherwise, it might lock up */
1712 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1713 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1714 host_ehi->serror |= serror;
1716 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1717 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1718 irq_stat &= ~PORT_IRQ_IF_ERR;
1720 if (irq_stat & PORT_IRQ_TF_ERR) {
1721 /* If qc is active, charge it; otherwise, the active
1722 * link. There's no active qc on NCQ errors. It will
1723 * be determined by EH by reading log page 10h.
1726 active_qc->err_mask |= AC_ERR_DEV;
1728 active_ehi->err_mask |= AC_ERR_DEV;
1730 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1731 host_ehi->serror &= ~SERR_INTERNAL;
1734 if (irq_stat & PORT_IRQ_UNK_FIS) {
1735 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1737 active_ehi->err_mask |= AC_ERR_HSM;
1738 active_ehi->action |= ATA_EH_RESET;
1739 ata_ehi_push_desc(active_ehi,
1740 "unknown FIS %08x %08x %08x %08x" ,
1741 unk[0], unk[1], unk[2], unk[3]);
1744 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1745 active_ehi->err_mask |= AC_ERR_HSM;
1746 active_ehi->action |= ATA_EH_RESET;
1747 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1750 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1751 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1752 host_ehi->action |= ATA_EH_RESET;
1753 ata_ehi_push_desc(host_ehi, "host bus error");
1756 if (irq_stat & PORT_IRQ_IF_ERR) {
1758 active_ehi->err_mask |= AC_ERR_DEV;
1760 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1761 host_ehi->action |= ATA_EH_RESET;
1764 ata_ehi_push_desc(host_ehi, "interface fatal error");
1767 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1768 ata_ehi_hotplugged(host_ehi);
1769 ata_ehi_push_desc(host_ehi, "%s",
1770 irq_stat & PORT_IRQ_CONNECT ?
1771 "connection status changed" : "PHY RDY changed");
1774 /* okay, let's hand over to EH */
1776 if (irq_stat & PORT_IRQ_FREEZE)
1777 ata_port_freeze(ap);
1778 else if (fbs_need_dec) {
1779 ata_link_abort(link);
1780 ahci_fbs_dec_intr(ap);
1785 static void ahci_handle_port_interrupt(struct ata_port *ap,
1786 void __iomem *port_mmio, u32 status)
1788 struct ata_eh_info *ehi = &ap->link.eh_info;
1789 struct ahci_port_priv *pp = ap->private_data;
1790 struct ahci_host_priv *hpriv = ap->host->private_data;
1791 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1795 /* ignore BAD_PMP while resetting */
1796 if (unlikely(resetting))
1797 status &= ~PORT_IRQ_BAD_PMP;
1799 if (sata_lpm_ignore_phy_events(&ap->link)) {
1800 status &= ~PORT_IRQ_PHYRDY;
1801 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1804 if (unlikely(status & PORT_IRQ_ERROR)) {
1805 ahci_error_intr(ap, status);
1809 if (status & PORT_IRQ_SDB_FIS) {
1810 /* If SNotification is available, leave notification
1811 * handling to sata_async_notification(). If not,
1812 * emulate it by snooping SDB FIS RX area.
1814 * Snooping FIS RX area is probably cheaper than
1815 * poking SNotification but some constrollers which
1816 * implement SNotification, ICH9 for example, don't
1817 * store AN SDB FIS into receive area.
1819 if (hpriv->cap & HOST_CAP_SNTF)
1820 sata_async_notification(ap);
1822 /* If the 'N' bit in word 0 of the FIS is set,
1823 * we just received asynchronous notification.
1824 * Tell libata about it.
1826 * Lack of SNotification should not appear in
1827 * ahci 1.2, so the workaround is unnecessary
1828 * when FBS is enabled.
1830 if (pp->fbs_enabled)
1833 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1834 u32 f0 = le32_to_cpu(f[0]);
1836 sata_async_notification(ap);
1841 /* pp->active_link is not reliable once FBS is enabled, both
1842 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1843 * NCQ and non-NCQ commands may be in flight at the same time.
1845 if (pp->fbs_enabled) {
1846 if (ap->qc_active) {
1847 qc_active = readl(port_mmio + PORT_SCR_ACT);
1848 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1851 /* pp->active_link is valid iff any command is in flight */
1852 if (ap->qc_active && pp->active_link->sactive)
1853 qc_active = readl(port_mmio + PORT_SCR_ACT);
1855 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1859 rc = ata_qc_complete_multiple(ap, qc_active);
1861 /* while resetting, invalid completions are expected */
1862 if (unlikely(rc < 0 && !resetting)) {
1863 ehi->err_mask |= AC_ERR_HSM;
1864 ehi->action |= ATA_EH_RESET;
1865 ata_port_freeze(ap);
1869 static void ahci_port_intr(struct ata_port *ap)
1871 void __iomem *port_mmio = ahci_port_base(ap);
1874 status = readl(port_mmio + PORT_IRQ_STAT);
1875 writel(status, port_mmio + PORT_IRQ_STAT);
1877 ahci_handle_port_interrupt(ap, port_mmio, status);
1880 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1882 struct ata_port *ap = dev_instance;
1883 void __iomem *port_mmio = ahci_port_base(ap);
1888 status = readl(port_mmio + PORT_IRQ_STAT);
1889 writel(status, port_mmio + PORT_IRQ_STAT);
1891 spin_lock(ap->lock);
1892 ahci_handle_port_interrupt(ap, port_mmio, status);
1893 spin_unlock(ap->lock);
1900 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1902 unsigned int i, handled = 0;
1904 for (i = 0; i < host->n_ports; i++) {
1905 struct ata_port *ap;
1907 if (!(irq_masked & (1 << i)))
1910 ap = host->ports[i];
1913 VPRINTK("port %u\n", i);
1915 VPRINTK("port %u (no irq)\n", i);
1916 if (ata_ratelimit())
1918 "interrupt on disabled port %u\n", i);
1926 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1928 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1930 struct ata_host *host = dev_instance;
1931 struct ahci_host_priv *hpriv;
1932 unsigned int rc = 0;
1934 u32 irq_stat, irq_masked;
1938 hpriv = host->private_data;
1941 /* sigh. 0xffffffff is a valid return from h/w */
1942 irq_stat = readl(mmio + HOST_IRQ_STAT);
1946 irq_masked = irq_stat & hpriv->port_map;
1948 spin_lock(&host->lock);
1950 rc = ahci_handle_port_intr(host, irq_masked);
1952 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1953 * it should be cleared after all the port events are cleared;
1954 * otherwise, it will raise a spurious interrupt after each
1955 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1958 * Also, use the unmasked value to clear interrupt as spurious
1959 * pending event on a dummy port might cause screaming IRQ.
1961 writel(irq_stat, mmio + HOST_IRQ_STAT);
1963 spin_unlock(&host->lock);
1967 return IRQ_RETVAL(rc);
1970 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1972 struct ata_port *ap = qc->ap;
1973 void __iomem *port_mmio = ahci_port_base(ap);
1974 struct ahci_port_priv *pp = ap->private_data;
1976 /* Keep track of the currently active link. It will be used
1977 * in completion path to determine whether NCQ phase is in
1980 pp->active_link = qc->dev->link;
1982 if (ata_is_ncq(qc->tf.protocol))
1983 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1985 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1986 u32 fbs = readl(port_mmio + PORT_FBS);
1987 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1988 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1989 writel(fbs, port_mmio + PORT_FBS);
1990 pp->fbs_last_dev = qc->dev->link->pmp;
1993 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1995 ahci_sw_activity(qc->dev->link);
1999 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2001 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2003 struct ahci_port_priv *pp = qc->ap->private_data;
2004 u8 *rx_fis = pp->rx_fis;
2006 if (pp->fbs_enabled)
2007 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2010 * After a successful execution of an ATA PIO data-in command,
2011 * the device doesn't send D2H Reg FIS to update the TF and
2012 * the host should take TF and E_Status from the preceding PIO
2015 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2016 !(qc->flags & ATA_QCFLAG_FAILED)) {
2017 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2018 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2020 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2025 static void ahci_freeze(struct ata_port *ap)
2027 void __iomem *port_mmio = ahci_port_base(ap);
2030 writel(0, port_mmio + PORT_IRQ_MASK);
2033 static void ahci_thaw(struct ata_port *ap)
2035 struct ahci_host_priv *hpriv = ap->host->private_data;
2036 void __iomem *mmio = hpriv->mmio;
2037 void __iomem *port_mmio = ahci_port_base(ap);
2039 struct ahci_port_priv *pp = ap->private_data;
2042 tmp = readl(port_mmio + PORT_IRQ_STAT);
2043 writel(tmp, port_mmio + PORT_IRQ_STAT);
2044 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2046 /* turn IRQ back on */
2047 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2050 void ahci_error_handler(struct ata_port *ap)
2052 struct ahci_host_priv *hpriv = ap->host->private_data;
2054 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2055 /* restart engine */
2056 ahci_stop_engine(ap);
2057 hpriv->start_engine(ap);
2060 sata_pmp_error_handler(ap);
2062 if (!ata_dev_enabled(ap->link.device))
2063 ahci_stop_engine(ap);
2065 EXPORT_SYMBOL_GPL(ahci_error_handler);
2067 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2069 struct ata_port *ap = qc->ap;
2071 /* make DMA engine forget about the failed command */
2072 if (qc->flags & ATA_QCFLAG_FAILED)
2073 ahci_kick_engine(ap);
2076 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2078 struct ahci_host_priv *hpriv = ap->host->private_data;
2079 void __iomem *port_mmio = ahci_port_base(ap);
2080 struct ata_device *dev = ap->link.device;
2081 u32 devslp, dm, dito, mdat, deto;
2083 unsigned int err_mask;
2085 devslp = readl(port_mmio + PORT_DEVSLP);
2086 if (!(devslp & PORT_DEVSLP_DSP)) {
2087 dev_info(ap->host->dev, "port does not support device sleep\n");
2091 /* disable device sleep */
2093 if (devslp & PORT_DEVSLP_ADSE) {
2094 writel(devslp & ~PORT_DEVSLP_ADSE,
2095 port_mmio + PORT_DEVSLP);
2096 err_mask = ata_dev_set_feature(dev,
2097 SETFEATURES_SATA_DISABLE,
2099 if (err_mask && err_mask != AC_ERR_DEV)
2100 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2105 /* device sleep was already enabled */
2106 if (devslp & PORT_DEVSLP_ADSE)
2109 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2110 rc = ahci_stop_engine(ap);
2114 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2115 dito = devslp_idle_timeout / (dm + 1);
2119 /* Use the nominal value 10 ms if the read MDAT is zero,
2120 * the nominal value of DETO is 20 ms.
2122 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2123 ATA_LOG_DEVSLP_VALID_MASK) {
2124 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2125 ATA_LOG_DEVSLP_MDAT_MASK;
2128 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2136 /* Make dito, mdat, deto bits to 0s */
2137 devslp &= ~GENMASK_ULL(24, 2);
2138 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2139 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2140 (deto << PORT_DEVSLP_DETO_OFFSET) |
2142 writel(devslp, port_mmio + PORT_DEVSLP);
2144 hpriv->start_engine(ap);
2146 /* enable device sleep feature for the drive */
2147 err_mask = ata_dev_set_feature(dev,
2148 SETFEATURES_SATA_ENABLE,
2150 if (err_mask && err_mask != AC_ERR_DEV)
2151 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2154 static void ahci_enable_fbs(struct ata_port *ap)
2156 struct ahci_host_priv *hpriv = ap->host->private_data;
2157 struct ahci_port_priv *pp = ap->private_data;
2158 void __iomem *port_mmio = ahci_port_base(ap);
2162 if (!pp->fbs_supported)
2165 fbs = readl(port_mmio + PORT_FBS);
2166 if (fbs & PORT_FBS_EN) {
2167 pp->fbs_enabled = true;
2168 pp->fbs_last_dev = -1; /* initialization */
2172 rc = ahci_stop_engine(ap);
2176 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2177 fbs = readl(port_mmio + PORT_FBS);
2178 if (fbs & PORT_FBS_EN) {
2179 dev_info(ap->host->dev, "FBS is enabled\n");
2180 pp->fbs_enabled = true;
2181 pp->fbs_last_dev = -1; /* initialization */
2183 dev_err(ap->host->dev, "Failed to enable FBS\n");
2185 hpriv->start_engine(ap);
2188 static void ahci_disable_fbs(struct ata_port *ap)
2190 struct ahci_host_priv *hpriv = ap->host->private_data;
2191 struct ahci_port_priv *pp = ap->private_data;
2192 void __iomem *port_mmio = ahci_port_base(ap);
2196 if (!pp->fbs_supported)
2199 fbs = readl(port_mmio + PORT_FBS);
2200 if ((fbs & PORT_FBS_EN) == 0) {
2201 pp->fbs_enabled = false;
2205 rc = ahci_stop_engine(ap);
2209 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2210 fbs = readl(port_mmio + PORT_FBS);
2211 if (fbs & PORT_FBS_EN)
2212 dev_err(ap->host->dev, "Failed to disable FBS\n");
2214 dev_info(ap->host->dev, "FBS is disabled\n");
2215 pp->fbs_enabled = false;
2218 hpriv->start_engine(ap);
2221 static void ahci_pmp_attach(struct ata_port *ap)
2223 void __iomem *port_mmio = ahci_port_base(ap);
2224 struct ahci_port_priv *pp = ap->private_data;
2227 cmd = readl(port_mmio + PORT_CMD);
2228 cmd |= PORT_CMD_PMP;
2229 writel(cmd, port_mmio + PORT_CMD);
2231 ahci_enable_fbs(ap);
2233 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2236 * We must not change the port interrupt mask register if the
2237 * port is marked frozen, the value in pp->intr_mask will be
2238 * restored later when the port is thawed.
2240 * Note that during initialization, the port is marked as
2241 * frozen since the irq handler is not yet registered.
2243 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2244 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2247 static void ahci_pmp_detach(struct ata_port *ap)
2249 void __iomem *port_mmio = ahci_port_base(ap);
2250 struct ahci_port_priv *pp = ap->private_data;
2253 ahci_disable_fbs(ap);
2255 cmd = readl(port_mmio + PORT_CMD);
2256 cmd &= ~PORT_CMD_PMP;
2257 writel(cmd, port_mmio + PORT_CMD);
2259 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2261 /* see comment above in ahci_pmp_attach() */
2262 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2263 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2266 int ahci_port_resume(struct ata_port *ap)
2268 ahci_rpm_get_port(ap);
2271 ahci_start_port(ap);
2273 if (sata_pmp_attached(ap))
2274 ahci_pmp_attach(ap);
2276 ahci_pmp_detach(ap);
2280 EXPORT_SYMBOL_GPL(ahci_port_resume);
2283 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2285 const char *emsg = NULL;
2288 rc = ahci_deinit_port(ap, &emsg);
2290 ahci_power_down(ap);
2292 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2293 ata_port_freeze(ap);
2296 ahci_rpm_put_port(ap);
2301 static int ahci_port_start(struct ata_port *ap)
2303 struct ahci_host_priv *hpriv = ap->host->private_data;
2304 struct device *dev = ap->host->dev;
2305 struct ahci_port_priv *pp;
2308 size_t dma_sz, rx_fis_sz;
2310 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2314 if (ap->host->n_ports > 1) {
2315 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2316 if (!pp->irq_desc) {
2317 devm_kfree(dev, pp);
2320 snprintf(pp->irq_desc, 8,
2321 "%s%d", dev_driver_string(dev), ap->port_no);
2324 /* check FBS capability */
2325 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2326 void __iomem *port_mmio = ahci_port_base(ap);
2327 u32 cmd = readl(port_mmio + PORT_CMD);
2328 if (cmd & PORT_CMD_FBSCP)
2329 pp->fbs_supported = true;
2330 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2331 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2333 pp->fbs_supported = true;
2335 dev_warn(dev, "port %d is not capable of FBS\n",
2339 if (pp->fbs_supported) {
2340 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2341 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2343 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2344 rx_fis_sz = AHCI_RX_FIS_SZ;
2347 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2350 memset(mem, 0, dma_sz);
2353 * First item in chunk of DMA memory: 32-slot command table,
2354 * 32 bytes each in size
2357 pp->cmd_slot_dma = mem_dma;
2359 mem += AHCI_CMD_SLOT_SZ;
2360 mem_dma += AHCI_CMD_SLOT_SZ;
2363 * Second item: Received-FIS area
2366 pp->rx_fis_dma = mem_dma;
2369 mem_dma += rx_fis_sz;
2372 * Third item: data area for storing a single command
2373 * and its scatter-gather table
2376 pp->cmd_tbl_dma = mem_dma;
2379 * Save off initial list of interrupts to be enabled.
2380 * This could be changed later
2382 pp->intr_mask = DEF_PORT_IRQ;
2385 * Switch to per-port locking in case each port has its own MSI vector.
2387 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2388 spin_lock_init(&pp->lock);
2389 ap->lock = &pp->lock;
2392 ap->private_data = pp;
2394 /* engage engines, captain */
2395 return ahci_port_resume(ap);
2398 static void ahci_port_stop(struct ata_port *ap)
2400 const char *emsg = NULL;
2401 struct ahci_host_priv *hpriv = ap->host->private_data;
2402 void __iomem *host_mmio = hpriv->mmio;
2405 /* de-initialize port */
2406 rc = ahci_deinit_port(ap, &emsg);
2408 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2411 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2414 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2417 void ahci_print_info(struct ata_host *host, const char *scc_s)
2419 struct ahci_host_priv *hpriv = host->private_data;
2420 u32 vers, cap, cap2, impl, speed;
2421 const char *speed_s;
2423 vers = hpriv->version;
2426 impl = hpriv->port_map;
2428 speed = (cap >> 20) & 0xf;
2431 else if (speed == 2)
2433 else if (speed == 3)
2439 "AHCI %02x%02x.%02x%02x "
2440 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2443 (vers >> 24) & 0xff,
2444 (vers >> 16) & 0xff,
2448 ((cap >> 8) & 0x1f) + 1,
2462 cap & HOST_CAP_64 ? "64bit " : "",
2463 cap & HOST_CAP_NCQ ? "ncq " : "",
2464 cap & HOST_CAP_SNTF ? "sntf " : "",
2465 cap & HOST_CAP_MPS ? "ilck " : "",
2466 cap & HOST_CAP_SSS ? "stag " : "",
2467 cap & HOST_CAP_ALPM ? "pm " : "",
2468 cap & HOST_CAP_LED ? "led " : "",
2469 cap & HOST_CAP_CLO ? "clo " : "",
2470 cap & HOST_CAP_ONLY ? "only " : "",
2471 cap & HOST_CAP_PMP ? "pmp " : "",
2472 cap & HOST_CAP_FBS ? "fbs " : "",
2473 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2474 cap & HOST_CAP_SSC ? "slum " : "",
2475 cap & HOST_CAP_PART ? "part " : "",
2476 cap & HOST_CAP_CCC ? "ccc " : "",
2477 cap & HOST_CAP_EMS ? "ems " : "",
2478 cap & HOST_CAP_SXS ? "sxs " : "",
2479 cap2 & HOST_CAP2_DESO ? "deso " : "",
2480 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2481 cap2 & HOST_CAP2_SDS ? "sds " : "",
2482 cap2 & HOST_CAP2_APST ? "apst " : "",
2483 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2484 cap2 & HOST_CAP2_BOH ? "boh " : ""
2487 EXPORT_SYMBOL_GPL(ahci_print_info);
2489 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2490 struct ata_port_info *pi)
2493 void __iomem *mmio = hpriv->mmio;
2494 u32 em_loc = readl(mmio + HOST_EM_LOC);
2495 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2497 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2500 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2504 hpriv->em_loc = ((em_loc >> 16) * 4);
2505 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2506 hpriv->em_msg_type = messages;
2507 pi->flags |= ATA_FLAG_EM;
2508 if (!(em_ctl & EM_CTL_ALHD))
2509 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2512 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2514 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2515 struct scsi_host_template *sht)
2517 struct ahci_host_priv *hpriv = host->private_data;
2520 rc = ata_host_start(host);
2524 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2525 * allocated. That is one MSI per port, starting from @irq.
2527 for (i = 0; i < host->n_ports; i++) {
2528 struct ahci_port_priv *pp = host->ports[i]->private_data;
2529 int irq = hpriv->get_irq_vector(host, i);
2531 /* Do not receive interrupts sent by dummy ports */
2537 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2538 0, pp->irq_desc, host->ports[i]);
2542 ata_port_desc(host->ports[i], "irq %d", irq);
2545 return ata_host_register(host, sht);
2549 * ahci_host_activate - start AHCI host, request IRQs and register it
2550 * @host: target ATA host
2551 * @sht: scsi_host_template to use when registering the host
2554 * Inherited from calling layer (may sleep).
2557 * 0 on success, -errno otherwise.
2559 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2561 struct ahci_host_priv *hpriv = host->private_data;
2562 int irq = hpriv->irq;
2565 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2566 if (hpriv->irq_handler)
2568 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2569 if (!hpriv->get_irq_vector) {
2571 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2575 rc = ahci_host_activate_multi_irqs(host, sht);
2577 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2584 EXPORT_SYMBOL_GPL(ahci_host_activate);
2586 MODULE_AUTHOR("Jeff Garzik");
2587 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2588 MODULE_LICENSE("GPL");