2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
49 static int ahci_skip_host_reset;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72 static int ahci_port_start(struct ata_port *ap);
73 static void ahci_port_stop(struct ata_port *ap);
74 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
75 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76 static void ahci_freeze(struct ata_port *ap);
77 static void ahci_thaw(struct ata_port *ap);
78 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
79 static void ahci_enable_fbs(struct ata_port *ap);
80 static void ahci_disable_fbs(struct ata_port *ap);
81 static void ahci_pmp_attach(struct ata_port *ap);
82 static void ahci_pmp_detach(struct ata_port *ap);
83 static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_postreset(struct ata_link *link, unsigned int *class);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static void ahci_dev_config(struct ata_device *dev);
93 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96 static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98 static void ahci_init_sw_activity(struct ata_link *link);
100 static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102 static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
113 static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
116 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
120 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
122 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
124 struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
133 &dev_attr_em_message_supported,
136 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
138 struct device_attribute *ahci_sdev_attrs[] = {
139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
143 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
145 struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
153 .freeze = ahci_freeze,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
168 .set_lpm = ahci_set_lpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173 .transmit_led_message = ahci_transmit_led_message,
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
181 EXPORT_SYMBOL_GPL(ahci_ops);
183 struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
187 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
189 static bool ahci_em_messages __read_mostly = true;
190 module_param(ahci_em_messages, bool, 0444);
191 /* add other LED protocol types when they become supported */
192 MODULE_PARM_DESC(ahci_em_messages,
193 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
195 /* device sleep idle timeout in ms */
196 static int devslp_idle_timeout __read_mostly = 1000;
197 module_param(devslp_idle_timeout, int, 0644);
198 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
200 static void ahci_enable_ahci(void __iomem *mmio)
205 /* turn on AHCI_EN */
206 tmp = readl(mmio + HOST_CTL);
207 if (tmp & HOST_AHCI_EN)
210 /* Some controllers need AHCI_EN to be written multiple times.
211 * Try a few times before giving up.
213 for (i = 0; i < 5; i++) {
215 writel(tmp, mmio + HOST_CTL);
216 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
217 if (tmp & HOST_AHCI_EN)
225 static ssize_t ahci_show_host_caps(struct device *dev,
226 struct device_attribute *attr, char *buf)
228 struct Scsi_Host *shost = class_to_shost(dev);
229 struct ata_port *ap = ata_shost_to_port(shost);
230 struct ahci_host_priv *hpriv = ap->host->private_data;
232 return sprintf(buf, "%x\n", hpriv->cap);
235 static ssize_t ahci_show_host_cap2(struct device *dev,
236 struct device_attribute *attr, char *buf)
238 struct Scsi_Host *shost = class_to_shost(dev);
239 struct ata_port *ap = ata_shost_to_port(shost);
240 struct ahci_host_priv *hpriv = ap->host->private_data;
242 return sprintf(buf, "%x\n", hpriv->cap2);
245 static ssize_t ahci_show_host_version(struct device *dev,
246 struct device_attribute *attr, char *buf)
248 struct Scsi_Host *shost = class_to_shost(dev);
249 struct ata_port *ap = ata_shost_to_port(shost);
250 struct ahci_host_priv *hpriv = ap->host->private_data;
251 void __iomem *mmio = hpriv->mmio;
253 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
256 static ssize_t ahci_show_port_cmd(struct device *dev,
257 struct device_attribute *attr, char *buf)
259 struct Scsi_Host *shost = class_to_shost(dev);
260 struct ata_port *ap = ata_shost_to_port(shost);
261 void __iomem *port_mmio = ahci_port_base(ap);
263 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
266 static ssize_t ahci_read_em_buffer(struct device *dev,
267 struct device_attribute *attr, char *buf)
269 struct Scsi_Host *shost = class_to_shost(dev);
270 struct ata_port *ap = ata_shost_to_port(shost);
271 struct ahci_host_priv *hpriv = ap->host->private_data;
272 void __iomem *mmio = hpriv->mmio;
273 void __iomem *em_mmio = mmio + hpriv->em_loc;
279 spin_lock_irqsave(ap->lock, flags);
281 em_ctl = readl(mmio + HOST_EM_CTL);
282 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
283 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
284 spin_unlock_irqrestore(ap->lock, flags);
288 if (!(em_ctl & EM_CTL_MR)) {
289 spin_unlock_irqrestore(ap->lock, flags);
293 if (!(em_ctl & EM_CTL_SMB))
294 em_mmio += hpriv->em_buf_sz;
296 count = hpriv->em_buf_sz;
298 /* the count should not be larger than PAGE_SIZE */
299 if (count > PAGE_SIZE) {
300 if (printk_ratelimit())
302 "EM read buffer size too large: "
303 "buffer size %u, page size %lu\n",
304 hpriv->em_buf_sz, PAGE_SIZE);
308 for (i = 0; i < count; i += 4) {
309 msg = readl(em_mmio + i);
311 buf[i + 1] = (msg >> 8) & 0xff;
312 buf[i + 2] = (msg >> 16) & 0xff;
313 buf[i + 3] = (msg >> 24) & 0xff;
316 spin_unlock_irqrestore(ap->lock, flags);
321 static ssize_t ahci_store_em_buffer(struct device *dev,
322 struct device_attribute *attr,
323 const char *buf, size_t size)
325 struct Scsi_Host *shost = class_to_shost(dev);
326 struct ata_port *ap = ata_shost_to_port(shost);
327 struct ahci_host_priv *hpriv = ap->host->private_data;
328 void __iomem *mmio = hpriv->mmio;
329 void __iomem *em_mmio = mmio + hpriv->em_loc;
330 const unsigned char *msg_buf = buf;
335 /* check size validity */
336 if (!(ap->flags & ATA_FLAG_EM) ||
337 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
338 size % 4 || size > hpriv->em_buf_sz)
341 spin_lock_irqsave(ap->lock, flags);
343 em_ctl = readl(mmio + HOST_EM_CTL);
344 if (em_ctl & EM_CTL_TM) {
345 spin_unlock_irqrestore(ap->lock, flags);
349 for (i = 0; i < size; i += 4) {
350 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
351 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
352 writel(msg, em_mmio + i);
355 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
357 spin_unlock_irqrestore(ap->lock, flags);
362 static ssize_t ahci_show_em_supported(struct device *dev,
363 struct device_attribute *attr, char *buf)
365 struct Scsi_Host *shost = class_to_shost(dev);
366 struct ata_port *ap = ata_shost_to_port(shost);
367 struct ahci_host_priv *hpriv = ap->host->private_data;
368 void __iomem *mmio = hpriv->mmio;
371 em_ctl = readl(mmio + HOST_EM_CTL);
373 return sprintf(buf, "%s%s%s%s\n",
374 em_ctl & EM_CTL_LED ? "led " : "",
375 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
376 em_ctl & EM_CTL_SES ? "ses-2 " : "",
377 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
381 * ahci_save_initial_config - Save and fixup initial config values
382 * @dev: target AHCI device
383 * @hpriv: host private area to store config values
385 * Some registers containing configuration info might be setup by
386 * BIOS and might be cleared on reset. This function saves the
387 * initial values of those registers into @hpriv such that they
388 * can be restored after controller reset.
390 * If inconsistent, config values are fixed up by this function.
392 * If it is not set already this function sets hpriv->start_engine to
398 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
400 void __iomem *mmio = hpriv->mmio;
401 u32 cap, cap2, vers, port_map;
404 /* make sure AHCI mode is enabled before accessing CAP */
405 ahci_enable_ahci(mmio);
407 /* Values prefixed with saved_ are written back to host after
408 * reset. Values without are used for driver operation.
410 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
411 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
413 /* CAP2 register is only defined for AHCI 1.2 and later */
414 vers = readl(mmio + HOST_VERSION);
415 if ((vers >> 16) > 1 ||
416 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
417 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
419 hpriv->saved_cap2 = cap2 = 0;
421 /* some chips have errata preventing 64bit use */
422 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
423 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
427 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
428 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
429 cap &= ~HOST_CAP_NCQ;
432 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
433 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
437 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
438 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
439 cap &= ~HOST_CAP_PMP;
442 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
444 "controller can't do SNTF, turning off CAP_SNTF\n");
445 cap &= ~HOST_CAP_SNTF;
448 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
450 "controller can't do DEVSLP, turning off\n");
451 cap2 &= ~HOST_CAP2_SDS;
452 cap2 &= ~HOST_CAP2_SADM;
455 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
456 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
460 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
461 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
462 cap &= ~HOST_CAP_FBS;
465 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
466 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
467 port_map, hpriv->force_port_map);
468 port_map = hpriv->force_port_map;
469 hpriv->saved_port_map = port_map;
472 if (hpriv->mask_port_map) {
473 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
475 port_map & hpriv->mask_port_map);
476 port_map &= hpriv->mask_port_map;
479 /* cross check port_map and cap.n_ports */
483 for (i = 0; i < AHCI_MAX_PORTS; i++)
484 if (port_map & (1 << i))
487 /* If PI has more ports than n_ports, whine, clear
488 * port_map and let it be generated from n_ports.
490 if (map_ports > ahci_nr_ports(cap)) {
492 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
493 port_map, ahci_nr_ports(cap));
498 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
499 if (!port_map && vers < 0x10300) {
500 port_map = (1 << ahci_nr_ports(cap)) - 1;
501 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
503 /* write the fixed up value to the PI register */
504 hpriv->saved_port_map = port_map;
507 /* record values to use during operation */
510 hpriv->port_map = port_map;
512 if (!hpriv->start_engine)
513 hpriv->start_engine = ahci_start_engine;
515 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
518 * ahci_restore_initial_config - Restore initial config
519 * @host: target ATA host
521 * Restore initial config stored by ahci_save_initial_config().
526 static void ahci_restore_initial_config(struct ata_host *host)
528 struct ahci_host_priv *hpriv = host->private_data;
529 void __iomem *mmio = hpriv->mmio;
531 writel(hpriv->saved_cap, mmio + HOST_CAP);
532 if (hpriv->saved_cap2)
533 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
534 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
535 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
538 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
540 static const int offset[] = {
541 [SCR_STATUS] = PORT_SCR_STAT,
542 [SCR_CONTROL] = PORT_SCR_CTL,
543 [SCR_ERROR] = PORT_SCR_ERR,
544 [SCR_ACTIVE] = PORT_SCR_ACT,
545 [SCR_NOTIFICATION] = PORT_SCR_NTF,
547 struct ahci_host_priv *hpriv = ap->host->private_data;
549 if (sc_reg < ARRAY_SIZE(offset) &&
550 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
551 return offset[sc_reg];
555 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
557 void __iomem *port_mmio = ahci_port_base(link->ap);
558 int offset = ahci_scr_offset(link->ap, sc_reg);
561 *val = readl(port_mmio + offset);
567 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
569 void __iomem *port_mmio = ahci_port_base(link->ap);
570 int offset = ahci_scr_offset(link->ap, sc_reg);
573 writel(val, port_mmio + offset);
579 void ahci_start_engine(struct ata_port *ap)
581 void __iomem *port_mmio = ahci_port_base(ap);
585 tmp = readl(port_mmio + PORT_CMD);
586 tmp |= PORT_CMD_START;
587 writel(tmp, port_mmio + PORT_CMD);
588 readl(port_mmio + PORT_CMD); /* flush */
590 EXPORT_SYMBOL_GPL(ahci_start_engine);
592 int ahci_stop_engine(struct ata_port *ap)
594 void __iomem *port_mmio = ahci_port_base(ap);
597 tmp = readl(port_mmio + PORT_CMD);
599 /* check if the HBA is idle */
600 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
603 /* setting HBA to idle */
604 tmp &= ~PORT_CMD_START;
605 writel(tmp, port_mmio + PORT_CMD);
607 /* wait for engine to stop. This could be as long as 500 msec */
608 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
609 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
610 if (tmp & PORT_CMD_LIST_ON)
615 EXPORT_SYMBOL_GPL(ahci_stop_engine);
617 void ahci_start_fis_rx(struct ata_port *ap)
619 void __iomem *port_mmio = ahci_port_base(ap);
620 struct ahci_host_priv *hpriv = ap->host->private_data;
621 struct ahci_port_priv *pp = ap->private_data;
624 /* set FIS registers */
625 if (hpriv->cap & HOST_CAP_64)
626 writel((pp->cmd_slot_dma >> 16) >> 16,
627 port_mmio + PORT_LST_ADDR_HI);
628 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
630 if (hpriv->cap & HOST_CAP_64)
631 writel((pp->rx_fis_dma >> 16) >> 16,
632 port_mmio + PORT_FIS_ADDR_HI);
633 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
635 /* enable FIS reception */
636 tmp = readl(port_mmio + PORT_CMD);
637 tmp |= PORT_CMD_FIS_RX;
638 writel(tmp, port_mmio + PORT_CMD);
641 readl(port_mmio + PORT_CMD);
643 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
645 static int ahci_stop_fis_rx(struct ata_port *ap)
647 void __iomem *port_mmio = ahci_port_base(ap);
650 /* disable FIS reception */
651 tmp = readl(port_mmio + PORT_CMD);
652 tmp &= ~PORT_CMD_FIS_RX;
653 writel(tmp, port_mmio + PORT_CMD);
655 /* wait for completion, spec says 500ms, give it 1000 */
656 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
657 PORT_CMD_FIS_ON, 10, 1000);
658 if (tmp & PORT_CMD_FIS_ON)
664 static void ahci_power_up(struct ata_port *ap)
666 struct ahci_host_priv *hpriv = ap->host->private_data;
667 void __iomem *port_mmio = ahci_port_base(ap);
670 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
673 if (hpriv->cap & HOST_CAP_SSS) {
674 cmd |= PORT_CMD_SPIN_UP;
675 writel(cmd, port_mmio + PORT_CMD);
679 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
682 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
685 struct ata_port *ap = link->ap;
686 struct ahci_host_priv *hpriv = ap->host->private_data;
687 struct ahci_port_priv *pp = ap->private_data;
688 void __iomem *port_mmio = ahci_port_base(ap);
690 if (policy != ATA_LPM_MAX_POWER) {
692 * Disable interrupts on Phy Ready. This keeps us from
693 * getting woken up due to spurious phy ready
696 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
697 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
699 sata_link_scr_lpm(link, policy, false);
702 if (hpriv->cap & HOST_CAP_ALPM) {
703 u32 cmd = readl(port_mmio + PORT_CMD);
705 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
706 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
707 cmd |= PORT_CMD_ICC_ACTIVE;
709 writel(cmd, port_mmio + PORT_CMD);
710 readl(port_mmio + PORT_CMD);
712 /* wait 10ms to be sure we've come out of LPM state */
715 cmd |= PORT_CMD_ALPE;
716 if (policy == ATA_LPM_MIN_POWER)
719 /* write out new cmd value */
720 writel(cmd, port_mmio + PORT_CMD);
724 /* set aggressive device sleep */
725 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
726 (hpriv->cap2 & HOST_CAP2_SADM) &&
727 (link->device->flags & ATA_DFLAG_DEVSLP)) {
728 if (policy == ATA_LPM_MIN_POWER)
729 ahci_set_aggressive_devslp(ap, true);
731 ahci_set_aggressive_devslp(ap, false);
734 if (policy == ATA_LPM_MAX_POWER) {
735 sata_link_scr_lpm(link, policy, false);
737 /* turn PHYRDY IRQ back on */
738 pp->intr_mask |= PORT_IRQ_PHYRDY;
739 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
746 static void ahci_power_down(struct ata_port *ap)
748 struct ahci_host_priv *hpriv = ap->host->private_data;
749 void __iomem *port_mmio = ahci_port_base(ap);
752 if (!(hpriv->cap & HOST_CAP_SSS))
755 /* put device into listen mode, first set PxSCTL.DET to 0 */
756 scontrol = readl(port_mmio + PORT_SCR_CTL);
758 writel(scontrol, port_mmio + PORT_SCR_CTL);
760 /* then set PxCMD.SUD to 0 */
761 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
762 cmd &= ~PORT_CMD_SPIN_UP;
763 writel(cmd, port_mmio + PORT_CMD);
767 static void ahci_start_port(struct ata_port *ap)
769 struct ahci_host_priv *hpriv = ap->host->private_data;
770 struct ahci_port_priv *pp = ap->private_data;
771 struct ata_link *link;
772 struct ahci_em_priv *emp;
776 /* enable FIS reception */
777 ahci_start_fis_rx(ap);
780 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
781 hpriv->start_engine(ap);
784 if (ap->flags & ATA_FLAG_EM) {
785 ata_for_each_link(link, ap, EDGE) {
786 emp = &pp->em_priv[link->pmp];
788 /* EM Transmit bit maybe busy during init */
789 for (i = 0; i < EM_MAX_RETRY; i++) {
790 rc = ap->ops->transmit_led_message(ap,
794 * If busy, give a breather but do not
795 * release EH ownership by using msleep()
796 * instead of ata_msleep(). EM Transmit
797 * bit is busy for the whole host and
798 * releasing ownership will cause other
799 * ports to fail the same way.
809 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
810 ata_for_each_link(link, ap, EDGE)
811 ahci_init_sw_activity(link);
815 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
820 rc = ahci_stop_engine(ap);
822 *emsg = "failed to stop engine";
826 /* disable FIS reception */
827 rc = ahci_stop_fis_rx(ap);
829 *emsg = "failed stop FIS RX";
836 int ahci_reset_controller(struct ata_host *host)
838 struct ahci_host_priv *hpriv = host->private_data;
839 void __iomem *mmio = hpriv->mmio;
842 /* we must be in AHCI mode, before using anything
843 * AHCI-specific, such as HOST_RESET.
845 ahci_enable_ahci(mmio);
847 /* global controller reset */
848 if (!ahci_skip_host_reset) {
849 tmp = readl(mmio + HOST_CTL);
850 if ((tmp & HOST_RESET) == 0) {
851 writel(tmp | HOST_RESET, mmio + HOST_CTL);
852 readl(mmio + HOST_CTL); /* flush */
856 * to perform host reset, OS should set HOST_RESET
857 * and poll until this bit is read to be "0".
858 * reset must complete within 1 second, or
859 * the hardware should be considered fried.
861 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
862 HOST_RESET, 10, 1000);
864 if (tmp & HOST_RESET) {
865 dev_err(host->dev, "controller reset failed (0x%x)\n",
870 /* turn on AHCI mode */
871 ahci_enable_ahci(mmio);
873 /* Some registers might be cleared on reset. Restore
876 ahci_restore_initial_config(host);
878 dev_info(host->dev, "skipping global host reset\n");
882 EXPORT_SYMBOL_GPL(ahci_reset_controller);
884 static void ahci_sw_activity(struct ata_link *link)
886 struct ata_port *ap = link->ap;
887 struct ahci_port_priv *pp = ap->private_data;
888 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
890 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
894 if (!timer_pending(&emp->timer))
895 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
898 static void ahci_sw_activity_blink(unsigned long arg)
900 struct ata_link *link = (struct ata_link *)arg;
901 struct ata_port *ap = link->ap;
902 struct ahci_port_priv *pp = ap->private_data;
903 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
904 unsigned long led_message = emp->led_state;
905 u32 activity_led_state;
908 led_message &= EM_MSG_LED_VALUE;
909 led_message |= ap->port_no | (link->pmp << 8);
911 /* check to see if we've had activity. If so,
912 * toggle state of LED and reset timer. If not,
913 * turn LED to desired idle state.
915 spin_lock_irqsave(ap->lock, flags);
916 if (emp->saved_activity != emp->activity) {
917 emp->saved_activity = emp->activity;
918 /* get the current LED state */
919 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
921 if (activity_led_state)
922 activity_led_state = 0;
924 activity_led_state = 1;
926 /* clear old state */
927 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
930 led_message |= (activity_led_state << 16);
931 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
934 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
935 if (emp->blink_policy == BLINK_OFF)
936 led_message |= (1 << 16);
938 spin_unlock_irqrestore(ap->lock, flags);
939 ap->ops->transmit_led_message(ap, led_message, 4);
942 static void ahci_init_sw_activity(struct ata_link *link)
944 struct ata_port *ap = link->ap;
945 struct ahci_port_priv *pp = ap->private_data;
946 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
948 /* init activity stats, setup timer */
949 emp->saved_activity = emp->activity = 0;
950 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
952 /* check our blink policy and set flag for link if it's enabled */
953 if (emp->blink_policy)
954 link->flags |= ATA_LFLAG_SW_ACTIVITY;
957 int ahci_reset_em(struct ata_host *host)
959 struct ahci_host_priv *hpriv = host->private_data;
960 void __iomem *mmio = hpriv->mmio;
963 em_ctl = readl(mmio + HOST_EM_CTL);
964 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
967 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
970 EXPORT_SYMBOL_GPL(ahci_reset_em);
972 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
975 struct ahci_host_priv *hpriv = ap->host->private_data;
976 struct ahci_port_priv *pp = ap->private_data;
977 void __iomem *mmio = hpriv->mmio;
979 u32 message[] = {0, 0};
982 struct ahci_em_priv *emp;
984 /* get the slot number from the message */
985 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
986 if (pmp < EM_MAX_SLOTS)
987 emp = &pp->em_priv[pmp];
991 spin_lock_irqsave(ap->lock, flags);
994 * if we are still busy transmitting a previous message,
997 em_ctl = readl(mmio + HOST_EM_CTL);
998 if (em_ctl & EM_CTL_TM) {
999 spin_unlock_irqrestore(ap->lock, flags);
1003 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1005 * create message header - this is all zero except for
1006 * the message size, which is 4 bytes.
1008 message[0] |= (4 << 8);
1010 /* ignore 0:4 of byte zero, fill in port info yourself */
1011 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1013 /* write message to EM_LOC */
1014 writel(message[0], mmio + hpriv->em_loc);
1015 writel(message[1], mmio + hpriv->em_loc+4);
1018 * tell hardware to transmit the message
1020 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1023 /* save off new led state for port/slot */
1024 emp->led_state = state;
1026 spin_unlock_irqrestore(ap->lock, flags);
1030 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1032 struct ahci_port_priv *pp = ap->private_data;
1033 struct ata_link *link;
1034 struct ahci_em_priv *emp;
1037 ata_for_each_link(link, ap, EDGE) {
1038 emp = &pp->em_priv[link->pmp];
1039 rc += sprintf(buf, "%lx\n", emp->led_state);
1044 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1049 struct ahci_port_priv *pp = ap->private_data;
1050 struct ahci_em_priv *emp;
1052 if (kstrtouint(buf, 0, &state) < 0)
1055 /* get the slot number from the message */
1056 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1057 if (pmp < EM_MAX_SLOTS)
1058 emp = &pp->em_priv[pmp];
1062 /* mask off the activity bits if we are in sw_activity
1063 * mode, user should turn off sw_activity before setting
1064 * activity led through em_message
1066 if (emp->blink_policy)
1067 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1069 return ap->ops->transmit_led_message(ap, state, size);
1072 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1074 struct ata_link *link = dev->link;
1075 struct ata_port *ap = link->ap;
1076 struct ahci_port_priv *pp = ap->private_data;
1077 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1078 u32 port_led_state = emp->led_state;
1080 /* save the desired Activity LED behavior */
1083 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1085 /* set the LED to OFF */
1086 port_led_state &= EM_MSG_LED_VALUE_OFF;
1087 port_led_state |= (ap->port_no | (link->pmp << 8));
1088 ap->ops->transmit_led_message(ap, port_led_state, 4);
1090 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1091 if (val == BLINK_OFF) {
1092 /* set LED to ON for idle */
1093 port_led_state &= EM_MSG_LED_VALUE_OFF;
1094 port_led_state |= (ap->port_no | (link->pmp << 8));
1095 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1096 ap->ops->transmit_led_message(ap, port_led_state, 4);
1099 emp->blink_policy = val;
1103 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1105 struct ata_link *link = dev->link;
1106 struct ata_port *ap = link->ap;
1107 struct ahci_port_priv *pp = ap->private_data;
1108 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1110 /* display the saved value of activity behavior for this
1113 return sprintf(buf, "%d\n", emp->blink_policy);
1116 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1117 int port_no, void __iomem *mmio,
1118 void __iomem *port_mmio)
1120 struct ahci_host_priv *hpriv = ap->host->private_data;
1121 const char *emsg = NULL;
1125 /* make sure port is not active */
1126 rc = ahci_deinit_port(ap, &emsg);
1128 dev_warn(dev, "%s (%d)\n", emsg, rc);
1131 tmp = readl(port_mmio + PORT_SCR_ERR);
1132 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1133 writel(tmp, port_mmio + PORT_SCR_ERR);
1135 /* clear port IRQ */
1136 tmp = readl(port_mmio + PORT_IRQ_STAT);
1137 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1139 writel(tmp, port_mmio + PORT_IRQ_STAT);
1141 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1143 /* mark esata ports */
1144 tmp = readl(port_mmio + PORT_CMD);
1145 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1146 ap->pflags |= ATA_PFLAG_EXTERNAL;
1149 void ahci_init_controller(struct ata_host *host)
1151 struct ahci_host_priv *hpriv = host->private_data;
1152 void __iomem *mmio = hpriv->mmio;
1154 void __iomem *port_mmio;
1157 for (i = 0; i < host->n_ports; i++) {
1158 struct ata_port *ap = host->ports[i];
1160 port_mmio = ahci_port_base(ap);
1161 if (ata_port_is_dummy(ap))
1164 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1167 tmp = readl(mmio + HOST_CTL);
1168 VPRINTK("HOST_CTL 0x%x\n", tmp);
1169 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1170 tmp = readl(mmio + HOST_CTL);
1171 VPRINTK("HOST_CTL 0x%x\n", tmp);
1173 EXPORT_SYMBOL_GPL(ahci_init_controller);
1175 static void ahci_dev_config(struct ata_device *dev)
1177 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1179 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1180 dev->max_sectors = 255;
1182 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1186 unsigned int ahci_dev_classify(struct ata_port *ap)
1188 void __iomem *port_mmio = ahci_port_base(ap);
1189 struct ata_taskfile tf;
1192 tmp = readl(port_mmio + PORT_SIG);
1193 tf.lbah = (tmp >> 24) & 0xff;
1194 tf.lbam = (tmp >> 16) & 0xff;
1195 tf.lbal = (tmp >> 8) & 0xff;
1196 tf.nsect = (tmp) & 0xff;
1198 return ata_dev_classify(&tf);
1200 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1202 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1205 dma_addr_t cmd_tbl_dma;
1207 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1209 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1210 pp->cmd_slot[tag].status = 0;
1211 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1212 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1214 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1216 int ahci_kick_engine(struct ata_port *ap)
1218 void __iomem *port_mmio = ahci_port_base(ap);
1219 struct ahci_host_priv *hpriv = ap->host->private_data;
1220 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1225 rc = ahci_stop_engine(ap);
1230 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1232 busy = status & (ATA_BUSY | ATA_DRQ);
1233 if (!busy && !sata_pmp_attached(ap)) {
1238 if (!(hpriv->cap & HOST_CAP_CLO)) {
1244 tmp = readl(port_mmio + PORT_CMD);
1245 tmp |= PORT_CMD_CLO;
1246 writel(tmp, port_mmio + PORT_CMD);
1249 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1250 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1251 if (tmp & PORT_CMD_CLO)
1254 /* restart engine */
1256 hpriv->start_engine(ap);
1259 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1261 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1262 struct ata_taskfile *tf, int is_cmd, u16 flags,
1263 unsigned long timeout_msec)
1265 const u32 cmd_fis_len = 5; /* five dwords */
1266 struct ahci_port_priv *pp = ap->private_data;
1267 void __iomem *port_mmio = ahci_port_base(ap);
1268 u8 *fis = pp->cmd_tbl;
1271 /* prep the command */
1272 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1273 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1275 /* set port value for softreset of Port Multiplier */
1276 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1277 tmp = readl(port_mmio + PORT_FBS);
1278 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1279 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1280 writel(tmp, port_mmio + PORT_FBS);
1281 pp->fbs_last_dev = pmp;
1285 writel(1, port_mmio + PORT_CMD_ISSUE);
1288 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1289 0x1, 0x1, 1, timeout_msec);
1291 ahci_kick_engine(ap);
1295 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1300 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1301 int pmp, unsigned long deadline,
1302 int (*check_ready)(struct ata_link *link))
1304 struct ata_port *ap = link->ap;
1305 struct ahci_host_priv *hpriv = ap->host->private_data;
1306 struct ahci_port_priv *pp = ap->private_data;
1307 const char *reason = NULL;
1308 unsigned long now, msecs;
1309 struct ata_taskfile tf;
1310 bool fbs_disabled = false;
1315 /* prepare for SRST (AHCI-1.1 10.4.1) */
1316 rc = ahci_kick_engine(ap);
1317 if (rc && rc != -EOPNOTSUPP)
1318 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1321 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1322 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1323 * that is attached to port multiplier.
1325 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1326 ahci_disable_fbs(ap);
1327 fbs_disabled = true;
1330 ata_tf_init(link->device, &tf);
1332 /* issue the first D2H Register FIS */
1335 if (time_after(deadline, now))
1336 msecs = jiffies_to_msecs(deadline - now);
1339 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1340 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1342 reason = "1st FIS failed";
1346 /* spec says at least 5us, but be generous and sleep for 1ms */
1349 /* issue the second D2H Register FIS */
1350 tf.ctl &= ~ATA_SRST;
1351 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1353 /* wait for link to become ready */
1354 rc = ata_wait_after_reset(link, deadline, check_ready);
1355 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1357 * Workaround for cases where link online status can't
1358 * be trusted. Treat device readiness timeout as link
1361 ata_link_info(link, "device not ready, treating as offline\n");
1362 *class = ATA_DEV_NONE;
1364 /* link occupied, -ENODEV too is an error */
1365 reason = "device not ready";
1368 *class = ahci_dev_classify(ap);
1370 /* re-enable FBS if disabled before */
1372 ahci_enable_fbs(ap);
1374 DPRINTK("EXIT, class=%u\n", *class);
1378 ata_link_err(link, "softreset failed (%s)\n", reason);
1382 int ahci_check_ready(struct ata_link *link)
1384 void __iomem *port_mmio = ahci_port_base(link->ap);
1385 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1387 return ata_check_ready(status);
1389 EXPORT_SYMBOL_GPL(ahci_check_ready);
1391 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1392 unsigned long deadline)
1394 int pmp = sata_srst_pmp(link);
1398 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1400 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1402 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1404 void __iomem *port_mmio = ahci_port_base(link->ap);
1405 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1406 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1409 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1410 * which can save timeout delay.
1412 if (irq_status & PORT_IRQ_BAD_PMP)
1415 return ata_check_ready(status);
1418 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1419 unsigned long deadline)
1421 struct ata_port *ap = link->ap;
1422 void __iomem *port_mmio = ahci_port_base(ap);
1423 int pmp = sata_srst_pmp(link);
1429 rc = ahci_do_softreset(link, class, pmp, deadline,
1430 ahci_bad_pmp_check_ready);
1433 * Soft reset fails with IPMS set when PMP is enabled but
1434 * SATA HDD/ODD is connected to SATA port, do soft reset
1438 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1439 if (irq_sts & PORT_IRQ_BAD_PMP) {
1441 "applying PMP SRST workaround "
1443 rc = ahci_do_softreset(link, class, 0, deadline,
1451 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1452 unsigned long deadline)
1454 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1455 struct ata_port *ap = link->ap;
1456 struct ahci_port_priv *pp = ap->private_data;
1457 struct ahci_host_priv *hpriv = ap->host->private_data;
1458 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1459 struct ata_taskfile tf;
1465 ahci_stop_engine(ap);
1467 /* clear D2H reception area to properly wait for D2H FIS */
1468 ata_tf_init(link->device, &tf);
1469 tf.command = ATA_BUSY;
1470 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1472 rc = sata_link_hardreset(link, timing, deadline, &online,
1475 hpriv->start_engine(ap);
1478 *class = ahci_dev_classify(ap);
1480 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1484 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1486 struct ata_port *ap = link->ap;
1487 void __iomem *port_mmio = ahci_port_base(ap);
1490 ata_std_postreset(link, class);
1492 /* Make sure port's ATAPI bit is set appropriately */
1493 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1494 if (*class == ATA_DEV_ATAPI)
1495 new_tmp |= PORT_CMD_ATAPI;
1497 new_tmp &= ~PORT_CMD_ATAPI;
1498 if (new_tmp != tmp) {
1499 writel(new_tmp, port_mmio + PORT_CMD);
1500 readl(port_mmio + PORT_CMD); /* flush */
1504 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1506 struct scatterlist *sg;
1507 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1513 * Next, the S/G list.
1515 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1516 dma_addr_t addr = sg_dma_address(sg);
1517 u32 sg_len = sg_dma_len(sg);
1519 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1520 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1521 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1527 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1529 struct ata_port *ap = qc->ap;
1530 struct ahci_port_priv *pp = ap->private_data;
1532 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1533 return ata_std_qc_defer(qc);
1535 return sata_pmp_qc_defer_cmd_switch(qc);
1538 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1540 struct ata_port *ap = qc->ap;
1541 struct ahci_port_priv *pp = ap->private_data;
1542 int is_atapi = ata_is_atapi(qc->tf.protocol);
1545 const u32 cmd_fis_len = 5; /* five dwords */
1546 unsigned int n_elem;
1549 * Fill in command table information. First, the header,
1550 * a SATA Register - Host to Device command FIS.
1552 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1554 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1556 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1557 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1561 if (qc->flags & ATA_QCFLAG_DMAMAP)
1562 n_elem = ahci_fill_sg(qc, cmd_tbl);
1565 * Fill in command slot information.
1567 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1568 if (qc->tf.flags & ATA_TFLAG_WRITE)
1569 opts |= AHCI_CMD_WRITE;
1571 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1573 ahci_fill_cmd_slot(pp, qc->tag, opts);
1578 static void ahci_fbs_dec_intr(struct ata_port *ap)
1580 struct ahci_port_priv *pp = ap->private_data;
1581 void __iomem *port_mmio = ahci_port_base(ap);
1582 u32 fbs = readl(port_mmio + PORT_FBS);
1586 BUG_ON(!pp->fbs_enabled);
1588 /* time to wait for DEC is not specified by AHCI spec,
1589 * add a retry loop for safety.
1591 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1592 fbs = readl(port_mmio + PORT_FBS);
1593 while ((fbs & PORT_FBS_DEC) && retries--) {
1595 fbs = readl(port_mmio + PORT_FBS);
1598 if (fbs & PORT_FBS_DEC)
1599 dev_err(ap->host->dev, "failed to clear device error\n");
1602 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1604 struct ahci_host_priv *hpriv = ap->host->private_data;
1605 struct ahci_port_priv *pp = ap->private_data;
1606 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1607 struct ata_link *link = NULL;
1608 struct ata_queued_cmd *active_qc;
1609 struct ata_eh_info *active_ehi;
1610 bool fbs_need_dec = false;
1613 /* determine active link with error */
1614 if (pp->fbs_enabled) {
1615 void __iomem *port_mmio = ahci_port_base(ap);
1616 u32 fbs = readl(port_mmio + PORT_FBS);
1617 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1619 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1620 link = &ap->pmp_link[pmp];
1621 fbs_need_dec = true;
1625 ata_for_each_link(link, ap, EDGE)
1626 if (ata_link_active(link))
1632 active_qc = ata_qc_from_tag(ap, link->active_tag);
1633 active_ehi = &link->eh_info;
1635 /* record irq stat */
1636 ata_ehi_clear_desc(host_ehi);
1637 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1639 /* AHCI needs SError cleared; otherwise, it might lock up */
1640 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1641 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1642 host_ehi->serror |= serror;
1644 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1645 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1646 irq_stat &= ~PORT_IRQ_IF_ERR;
1648 if (irq_stat & PORT_IRQ_TF_ERR) {
1649 /* If qc is active, charge it; otherwise, the active
1650 * link. There's no active qc on NCQ errors. It will
1651 * be determined by EH by reading log page 10h.
1654 active_qc->err_mask |= AC_ERR_DEV;
1656 active_ehi->err_mask |= AC_ERR_DEV;
1658 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1659 host_ehi->serror &= ~SERR_INTERNAL;
1662 if (irq_stat & PORT_IRQ_UNK_FIS) {
1663 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1665 active_ehi->err_mask |= AC_ERR_HSM;
1666 active_ehi->action |= ATA_EH_RESET;
1667 ata_ehi_push_desc(active_ehi,
1668 "unknown FIS %08x %08x %08x %08x" ,
1669 unk[0], unk[1], unk[2], unk[3]);
1672 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1673 active_ehi->err_mask |= AC_ERR_HSM;
1674 active_ehi->action |= ATA_EH_RESET;
1675 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1678 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1679 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1680 host_ehi->action |= ATA_EH_RESET;
1681 ata_ehi_push_desc(host_ehi, "host bus error");
1684 if (irq_stat & PORT_IRQ_IF_ERR) {
1686 active_ehi->err_mask |= AC_ERR_DEV;
1688 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1689 host_ehi->action |= ATA_EH_RESET;
1692 ata_ehi_push_desc(host_ehi, "interface fatal error");
1695 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1696 ata_ehi_hotplugged(host_ehi);
1697 ata_ehi_push_desc(host_ehi, "%s",
1698 irq_stat & PORT_IRQ_CONNECT ?
1699 "connection status changed" : "PHY RDY changed");
1702 /* okay, let's hand over to EH */
1704 if (irq_stat & PORT_IRQ_FREEZE)
1705 ata_port_freeze(ap);
1706 else if (fbs_need_dec) {
1707 ata_link_abort(link);
1708 ahci_fbs_dec_intr(ap);
1713 static void ahci_handle_port_interrupt(struct ata_port *ap,
1714 void __iomem *port_mmio, u32 status)
1716 struct ata_eh_info *ehi = &ap->link.eh_info;
1717 struct ahci_port_priv *pp = ap->private_data;
1718 struct ahci_host_priv *hpriv = ap->host->private_data;
1719 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1723 /* ignore BAD_PMP while resetting */
1724 if (unlikely(resetting))
1725 status &= ~PORT_IRQ_BAD_PMP;
1727 if (sata_lpm_ignore_phy_events(&ap->link)) {
1728 status &= ~PORT_IRQ_PHYRDY;
1729 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1732 if (unlikely(status & PORT_IRQ_ERROR)) {
1733 ahci_error_intr(ap, status);
1737 if (status & PORT_IRQ_SDB_FIS) {
1738 /* If SNotification is available, leave notification
1739 * handling to sata_async_notification(). If not,
1740 * emulate it by snooping SDB FIS RX area.
1742 * Snooping FIS RX area is probably cheaper than
1743 * poking SNotification but some constrollers which
1744 * implement SNotification, ICH9 for example, don't
1745 * store AN SDB FIS into receive area.
1747 if (hpriv->cap & HOST_CAP_SNTF)
1748 sata_async_notification(ap);
1750 /* If the 'N' bit in word 0 of the FIS is set,
1751 * we just received asynchronous notification.
1752 * Tell libata about it.
1754 * Lack of SNotification should not appear in
1755 * ahci 1.2, so the workaround is unnecessary
1756 * when FBS is enabled.
1758 if (pp->fbs_enabled)
1761 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1762 u32 f0 = le32_to_cpu(f[0]);
1764 sata_async_notification(ap);
1769 /* pp->active_link is not reliable once FBS is enabled, both
1770 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1771 * NCQ and non-NCQ commands may be in flight at the same time.
1773 if (pp->fbs_enabled) {
1774 if (ap->qc_active) {
1775 qc_active = readl(port_mmio + PORT_SCR_ACT);
1776 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1779 /* pp->active_link is valid iff any command is in flight */
1780 if (ap->qc_active && pp->active_link->sactive)
1781 qc_active = readl(port_mmio + PORT_SCR_ACT);
1783 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1787 rc = ata_qc_complete_multiple(ap, qc_active);
1789 /* while resetting, invalid completions are expected */
1790 if (unlikely(rc < 0 && !resetting)) {
1791 ehi->err_mask |= AC_ERR_HSM;
1792 ehi->action |= ATA_EH_RESET;
1793 ata_port_freeze(ap);
1797 static void ahci_port_intr(struct ata_port *ap)
1799 void __iomem *port_mmio = ahci_port_base(ap);
1802 status = readl(port_mmio + PORT_IRQ_STAT);
1803 writel(status, port_mmio + PORT_IRQ_STAT);
1805 ahci_handle_port_interrupt(ap, port_mmio, status);
1808 static irqreturn_t ahci_port_thread_fn(int irq, void *dev_instance)
1810 struct ata_port *ap = dev_instance;
1811 struct ahci_port_priv *pp = ap->private_data;
1812 void __iomem *port_mmio = ahci_port_base(ap);
1815 status = atomic_xchg(&pp->intr_status, 0);
1819 spin_lock_bh(ap->lock);
1820 ahci_handle_port_interrupt(ap, port_mmio, status);
1821 spin_unlock_bh(ap->lock);
1826 static irqreturn_t ahci_multi_irqs_intr(int irq, void *dev_instance)
1828 struct ata_port *ap = dev_instance;
1829 void __iomem *port_mmio = ahci_port_base(ap);
1830 struct ahci_port_priv *pp = ap->private_data;
1835 status = readl(port_mmio + PORT_IRQ_STAT);
1836 writel(status, port_mmio + PORT_IRQ_STAT);
1838 atomic_or(status, &pp->intr_status);
1842 return IRQ_WAKE_THREAD;
1845 static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1847 unsigned int i, handled = 0;
1849 for (i = 0; i < host->n_ports; i++) {
1850 struct ata_port *ap;
1852 if (!(irq_masked & (1 << i)))
1855 ap = host->ports[i];
1858 VPRINTK("port %u\n", i);
1860 VPRINTK("port %u (no irq)\n", i);
1861 if (ata_ratelimit())
1863 "interrupt on disabled port %u\n", i);
1872 static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
1874 struct ata_host *host = dev_instance;
1875 struct ahci_host_priv *hpriv;
1876 unsigned int rc = 0;
1878 u32 irq_stat, irq_masked;
1882 hpriv = host->private_data;
1885 /* sigh. 0xffffffff is a valid return from h/w */
1886 irq_stat = readl(mmio + HOST_IRQ_STAT);
1890 irq_masked = irq_stat & hpriv->port_map;
1892 spin_lock(&host->lock);
1895 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
1896 * it should be cleared before all the port events are cleared.
1898 writel(irq_stat, mmio + HOST_IRQ_STAT);
1900 rc = ahci_handle_port_intr(host, irq_masked);
1902 spin_unlock(&host->lock);
1906 return IRQ_RETVAL(rc);
1909 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1911 struct ata_host *host = dev_instance;
1912 struct ahci_host_priv *hpriv;
1913 unsigned int rc = 0;
1915 u32 irq_stat, irq_masked;
1919 hpriv = host->private_data;
1922 /* sigh. 0xffffffff is a valid return from h/w */
1923 irq_stat = readl(mmio + HOST_IRQ_STAT);
1927 irq_masked = irq_stat & hpriv->port_map;
1929 spin_lock(&host->lock);
1931 rc = ahci_handle_port_intr(host, irq_masked);
1933 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1934 * it should be cleared after all the port events are cleared;
1935 * otherwise, it will raise a spurious interrupt after each
1936 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1939 * Also, use the unmasked value to clear interrupt as spurious
1940 * pending event on a dummy port might cause screaming IRQ.
1942 writel(irq_stat, mmio + HOST_IRQ_STAT);
1944 spin_unlock(&host->lock);
1948 return IRQ_RETVAL(rc);
1951 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1953 struct ata_port *ap = qc->ap;
1954 void __iomem *port_mmio = ahci_port_base(ap);
1955 struct ahci_port_priv *pp = ap->private_data;
1957 /* Keep track of the currently active link. It will be used
1958 * in completion path to determine whether NCQ phase is in
1961 pp->active_link = qc->dev->link;
1963 if (qc->tf.protocol == ATA_PROT_NCQ)
1964 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1966 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1967 u32 fbs = readl(port_mmio + PORT_FBS);
1968 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1969 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1970 writel(fbs, port_mmio + PORT_FBS);
1971 pp->fbs_last_dev = qc->dev->link->pmp;
1974 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1976 ahci_sw_activity(qc->dev->link);
1980 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1982 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1984 struct ahci_port_priv *pp = qc->ap->private_data;
1985 u8 *rx_fis = pp->rx_fis;
1987 if (pp->fbs_enabled)
1988 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1991 * After a successful execution of an ATA PIO data-in command,
1992 * the device doesn't send D2H Reg FIS to update the TF and
1993 * the host should take TF and E_Status from the preceding PIO
1996 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1997 !(qc->flags & ATA_QCFLAG_FAILED)) {
1998 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1999 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2001 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2006 static void ahci_freeze(struct ata_port *ap)
2008 void __iomem *port_mmio = ahci_port_base(ap);
2011 writel(0, port_mmio + PORT_IRQ_MASK);
2014 static void ahci_thaw(struct ata_port *ap)
2016 struct ahci_host_priv *hpriv = ap->host->private_data;
2017 void __iomem *mmio = hpriv->mmio;
2018 void __iomem *port_mmio = ahci_port_base(ap);
2020 struct ahci_port_priv *pp = ap->private_data;
2023 tmp = readl(port_mmio + PORT_IRQ_STAT);
2024 writel(tmp, port_mmio + PORT_IRQ_STAT);
2025 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2027 /* turn IRQ back on */
2028 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2031 void ahci_error_handler(struct ata_port *ap)
2033 struct ahci_host_priv *hpriv = ap->host->private_data;
2035 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2036 /* restart engine */
2037 ahci_stop_engine(ap);
2038 hpriv->start_engine(ap);
2041 sata_pmp_error_handler(ap);
2043 if (!ata_dev_enabled(ap->link.device))
2044 ahci_stop_engine(ap);
2046 EXPORT_SYMBOL_GPL(ahci_error_handler);
2048 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2050 struct ata_port *ap = qc->ap;
2052 /* make DMA engine forget about the failed command */
2053 if (qc->flags & ATA_QCFLAG_FAILED)
2054 ahci_kick_engine(ap);
2057 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2059 struct ahci_host_priv *hpriv = ap->host->private_data;
2060 void __iomem *port_mmio = ahci_port_base(ap);
2061 struct ata_device *dev = ap->link.device;
2062 u32 devslp, dm, dito, mdat, deto;
2064 unsigned int err_mask;
2066 devslp = readl(port_mmio + PORT_DEVSLP);
2067 if (!(devslp & PORT_DEVSLP_DSP)) {
2068 dev_info(ap->host->dev, "port does not support device sleep\n");
2072 /* disable device sleep */
2074 if (devslp & PORT_DEVSLP_ADSE) {
2075 writel(devslp & ~PORT_DEVSLP_ADSE,
2076 port_mmio + PORT_DEVSLP);
2077 err_mask = ata_dev_set_feature(dev,
2078 SETFEATURES_SATA_DISABLE,
2080 if (err_mask && err_mask != AC_ERR_DEV)
2081 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2086 /* device sleep was already enabled */
2087 if (devslp & PORT_DEVSLP_ADSE)
2090 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2091 rc = ahci_stop_engine(ap);
2095 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2096 dito = devslp_idle_timeout / (dm + 1);
2100 /* Use the nominal value 10 ms if the read MDAT is zero,
2101 * the nominal value of DETO is 20 ms.
2103 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2104 ATA_LOG_DEVSLP_VALID_MASK) {
2105 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2106 ATA_LOG_DEVSLP_MDAT_MASK;
2109 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2117 /* Make dito, mdat, deto bits to 0s */
2118 devslp &= ~GENMASK_ULL(24, 2);
2119 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2120 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2121 (deto << PORT_DEVSLP_DETO_OFFSET) |
2123 writel(devslp, port_mmio + PORT_DEVSLP);
2125 hpriv->start_engine(ap);
2127 /* enable device sleep feature for the drive */
2128 err_mask = ata_dev_set_feature(dev,
2129 SETFEATURES_SATA_ENABLE,
2131 if (err_mask && err_mask != AC_ERR_DEV)
2132 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2135 static void ahci_enable_fbs(struct ata_port *ap)
2137 struct ahci_host_priv *hpriv = ap->host->private_data;
2138 struct ahci_port_priv *pp = ap->private_data;
2139 void __iomem *port_mmio = ahci_port_base(ap);
2143 if (!pp->fbs_supported)
2146 fbs = readl(port_mmio + PORT_FBS);
2147 if (fbs & PORT_FBS_EN) {
2148 pp->fbs_enabled = true;
2149 pp->fbs_last_dev = -1; /* initialization */
2153 rc = ahci_stop_engine(ap);
2157 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2158 fbs = readl(port_mmio + PORT_FBS);
2159 if (fbs & PORT_FBS_EN) {
2160 dev_info(ap->host->dev, "FBS is enabled\n");
2161 pp->fbs_enabled = true;
2162 pp->fbs_last_dev = -1; /* initialization */
2164 dev_err(ap->host->dev, "Failed to enable FBS\n");
2166 hpriv->start_engine(ap);
2169 static void ahci_disable_fbs(struct ata_port *ap)
2171 struct ahci_host_priv *hpriv = ap->host->private_data;
2172 struct ahci_port_priv *pp = ap->private_data;
2173 void __iomem *port_mmio = ahci_port_base(ap);
2177 if (!pp->fbs_supported)
2180 fbs = readl(port_mmio + PORT_FBS);
2181 if ((fbs & PORT_FBS_EN) == 0) {
2182 pp->fbs_enabled = false;
2186 rc = ahci_stop_engine(ap);
2190 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2191 fbs = readl(port_mmio + PORT_FBS);
2192 if (fbs & PORT_FBS_EN)
2193 dev_err(ap->host->dev, "Failed to disable FBS\n");
2195 dev_info(ap->host->dev, "FBS is disabled\n");
2196 pp->fbs_enabled = false;
2199 hpriv->start_engine(ap);
2202 static void ahci_pmp_attach(struct ata_port *ap)
2204 void __iomem *port_mmio = ahci_port_base(ap);
2205 struct ahci_port_priv *pp = ap->private_data;
2208 cmd = readl(port_mmio + PORT_CMD);
2209 cmd |= PORT_CMD_PMP;
2210 writel(cmd, port_mmio + PORT_CMD);
2212 ahci_enable_fbs(ap);
2214 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2217 * We must not change the port interrupt mask register if the
2218 * port is marked frozen, the value in pp->intr_mask will be
2219 * restored later when the port is thawed.
2221 * Note that during initialization, the port is marked as
2222 * frozen since the irq handler is not yet registered.
2224 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2225 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2228 static void ahci_pmp_detach(struct ata_port *ap)
2230 void __iomem *port_mmio = ahci_port_base(ap);
2231 struct ahci_port_priv *pp = ap->private_data;
2234 ahci_disable_fbs(ap);
2236 cmd = readl(port_mmio + PORT_CMD);
2237 cmd &= ~PORT_CMD_PMP;
2238 writel(cmd, port_mmio + PORT_CMD);
2240 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2242 /* see comment above in ahci_pmp_attach() */
2243 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2244 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2247 int ahci_port_resume(struct ata_port *ap)
2250 ahci_start_port(ap);
2252 if (sata_pmp_attached(ap))
2253 ahci_pmp_attach(ap);
2255 ahci_pmp_detach(ap);
2259 EXPORT_SYMBOL_GPL(ahci_port_resume);
2262 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2264 const char *emsg = NULL;
2267 rc = ahci_deinit_port(ap, &emsg);
2269 ahci_power_down(ap);
2271 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2272 ata_port_freeze(ap);
2279 static int ahci_port_start(struct ata_port *ap)
2281 struct ahci_host_priv *hpriv = ap->host->private_data;
2282 struct device *dev = ap->host->dev;
2283 struct ahci_port_priv *pp;
2286 size_t dma_sz, rx_fis_sz;
2288 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2292 if (ap->host->n_ports > 1) {
2293 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2294 if (!pp->irq_desc) {
2295 devm_kfree(dev, pp);
2298 snprintf(pp->irq_desc, 8,
2299 "%s%d", dev_driver_string(dev), ap->port_no);
2302 /* check FBS capability */
2303 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2304 void __iomem *port_mmio = ahci_port_base(ap);
2305 u32 cmd = readl(port_mmio + PORT_CMD);
2306 if (cmd & PORT_CMD_FBSCP)
2307 pp->fbs_supported = true;
2308 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2309 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2311 pp->fbs_supported = true;
2313 dev_warn(dev, "port %d is not capable of FBS\n",
2317 if (pp->fbs_supported) {
2318 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2319 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2321 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2322 rx_fis_sz = AHCI_RX_FIS_SZ;
2325 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2328 memset(mem, 0, dma_sz);
2331 * First item in chunk of DMA memory: 32-slot command table,
2332 * 32 bytes each in size
2335 pp->cmd_slot_dma = mem_dma;
2337 mem += AHCI_CMD_SLOT_SZ;
2338 mem_dma += AHCI_CMD_SLOT_SZ;
2341 * Second item: Received-FIS area
2344 pp->rx_fis_dma = mem_dma;
2347 mem_dma += rx_fis_sz;
2350 * Third item: data area for storing a single command
2351 * and its scatter-gather table
2354 pp->cmd_tbl_dma = mem_dma;
2357 * Save off initial list of interrupts to be enabled.
2358 * This could be changed later
2360 pp->intr_mask = DEF_PORT_IRQ;
2363 * Switch to per-port locking in case each port has its own MSI vector.
2365 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2366 spin_lock_init(&pp->lock);
2367 ap->lock = &pp->lock;
2370 ap->private_data = pp;
2372 /* engage engines, captain */
2373 return ahci_port_resume(ap);
2376 static void ahci_port_stop(struct ata_port *ap)
2378 const char *emsg = NULL;
2381 /* de-initialize port */
2382 rc = ahci_deinit_port(ap, &emsg);
2384 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2387 void ahci_print_info(struct ata_host *host, const char *scc_s)
2389 struct ahci_host_priv *hpriv = host->private_data;
2390 void __iomem *mmio = hpriv->mmio;
2391 u32 vers, cap, cap2, impl, speed;
2392 const char *speed_s;
2394 vers = readl(mmio + HOST_VERSION);
2397 impl = hpriv->port_map;
2399 speed = (cap >> 20) & 0xf;
2402 else if (speed == 2)
2404 else if (speed == 3)
2410 "AHCI %02x%02x.%02x%02x "
2411 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2414 (vers >> 24) & 0xff,
2415 (vers >> 16) & 0xff,
2419 ((cap >> 8) & 0x1f) + 1,
2433 cap & HOST_CAP_64 ? "64bit " : "",
2434 cap & HOST_CAP_NCQ ? "ncq " : "",
2435 cap & HOST_CAP_SNTF ? "sntf " : "",
2436 cap & HOST_CAP_MPS ? "ilck " : "",
2437 cap & HOST_CAP_SSS ? "stag " : "",
2438 cap & HOST_CAP_ALPM ? "pm " : "",
2439 cap & HOST_CAP_LED ? "led " : "",
2440 cap & HOST_CAP_CLO ? "clo " : "",
2441 cap & HOST_CAP_ONLY ? "only " : "",
2442 cap & HOST_CAP_PMP ? "pmp " : "",
2443 cap & HOST_CAP_FBS ? "fbs " : "",
2444 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2445 cap & HOST_CAP_SSC ? "slum " : "",
2446 cap & HOST_CAP_PART ? "part " : "",
2447 cap & HOST_CAP_CCC ? "ccc " : "",
2448 cap & HOST_CAP_EMS ? "ems " : "",
2449 cap & HOST_CAP_SXS ? "sxs " : "",
2450 cap2 & HOST_CAP2_DESO ? "deso " : "",
2451 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2452 cap2 & HOST_CAP2_SDS ? "sds " : "",
2453 cap2 & HOST_CAP2_APST ? "apst " : "",
2454 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2455 cap2 & HOST_CAP2_BOH ? "boh " : ""
2458 EXPORT_SYMBOL_GPL(ahci_print_info);
2460 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2461 struct ata_port_info *pi)
2464 void __iomem *mmio = hpriv->mmio;
2465 u32 em_loc = readl(mmio + HOST_EM_LOC);
2466 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2468 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2471 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2475 hpriv->em_loc = ((em_loc >> 16) * 4);
2476 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2477 hpriv->em_msg_type = messages;
2478 pi->flags |= ATA_FLAG_EM;
2479 if (!(em_ctl & EM_CTL_ALHD))
2480 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2483 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2485 static int ahci_host_activate_multi_irqs(struct ata_host *host, int irq,
2486 struct scsi_host_template *sht)
2490 rc = ata_host_start(host);
2494 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2495 * allocated. That is one MSI per port, starting from @irq.
2497 for (i = 0; i < host->n_ports; i++) {
2498 struct ahci_port_priv *pp = host->ports[i]->private_data;
2500 /* Do not receive interrupts sent by dummy ports */
2502 disable_irq(irq + i);
2506 rc = devm_request_threaded_irq(host->dev, irq + i,
2507 ahci_multi_irqs_intr,
2508 ahci_port_thread_fn, 0,
2509 pp->irq_desc, host->ports[i]);
2512 ata_port_desc(host->ports[i], "irq %d", irq + i);
2514 return ata_host_register(host, sht);
2518 * ahci_host_activate - start AHCI host, request IRQs and register it
2519 * @host: target ATA host
2520 * @sht: scsi_host_template to use when registering the host
2523 * Inherited from calling layer (may sleep).
2526 * 0 on success, -errno otherwise.
2528 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2530 struct ahci_host_priv *hpriv = host->private_data;
2531 int irq = hpriv->irq;
2534 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
2535 rc = ahci_host_activate_multi_irqs(host, irq, sht);
2536 else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ)
2537 rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr,
2540 rc = ata_host_activate(host, irq, ahci_single_level_irq_intr,
2544 EXPORT_SYMBOL_GPL(ahci_host_activate);
2546 MODULE_AUTHOR("Jeff Garzik");
2547 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2548 MODULE_LICENSE("GPL");