2 * Broadcom SATA3 AHCI Controller Driver
4 * Copyright © 2009-2015 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/ahci_platform.h>
18 #include <linux/compiler.h>
19 #include <linux/device.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/libata.h>
25 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/reset.h>
29 #include <linux/string.h>
33 #define DRV_NAME "brcm-ahci"
35 #define SATA_TOP_CTRL_VERSION 0x0
36 #define SATA_TOP_CTRL_BUS_CTRL 0x4
37 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
38 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
39 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
40 #define PIODATA_ENDIAN_SHIFT 6
41 #define ENDIAN_SWAP_NONE 0
42 #define ENDIAN_SWAP_FULL 2
43 #define OVERRIDE_HWINIT BIT(16)
44 #define SATA_TOP_CTRL_TP_CTRL 0x8
45 #define SATA_TOP_CTRL_PHY_CTRL 0xc
46 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0
47 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
48 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4
49 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
50 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
51 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
52 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
53 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
54 #define SATA_TOP_CTRL_PHY_OFFS 0x8
55 #define SATA_TOP_MAX_PHYS 2
57 #define SATA_FIRST_PORT_CTRL 0x700
58 #define SATA_NEXT_PORT_CTRL_OFFSET 0x80
59 #define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
61 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
62 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
63 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
64 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
70 #define BUS_CTRL_ENDIAN_CONF \
71 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \
72 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
73 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
75 enum brcm_ahci_version {
76 BRCM_SATA_BCM7425 = 1,
81 enum brcm_ahci_quirks {
82 BRCM_AHCI_QUIRK_NO_NCQ = BIT(0),
83 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
86 struct brcm_ahci_priv {
88 void __iomem *top_ctrl;
91 enum brcm_ahci_version version;
92 struct reset_control *rcdev;
95 static const struct ata_port_info ahci_brcm_port_info = {
96 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
97 .link_flags = ATA_LFLAG_NO_DB_DELAY,
99 .udma_mask = ATA_UDMA6,
100 .port_ops = &ahci_platform_ops,
103 static inline u32 brcm_sata_readreg(void __iomem *addr)
106 * MIPS endianness is configured by boot strap, which also reverses all
107 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
110 * Other architectures (e.g., ARM) either do not support big endian, or
111 * else leave I/O in little endian mode.
113 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
114 return __raw_readl(addr);
116 return readl_relaxed(addr);
119 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
121 /* See brcm_sata_readreg() comments */
122 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
123 __raw_writel(val, addr);
125 writel_relaxed(val, addr);
128 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
130 struct brcm_ahci_priv *priv = hpriv->plat_data;
131 u32 bus_ctrl, port_ctrl, host_caps;
134 /* Enable support for ALPM */
135 bus_ctrl = brcm_sata_readreg(priv->top_ctrl +
136 SATA_TOP_CTRL_BUS_CTRL);
137 brcm_sata_writereg(bus_ctrl | OVERRIDE_HWINIT,
138 priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
139 host_caps = readl(hpriv->mmio + HOST_CAP);
140 writel(host_caps | HOST_CAP_ALPM, hpriv->mmio);
141 brcm_sata_writereg(bus_ctrl, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
144 * Adjust timeout to allow PLL sufficient time to lock while waking
145 * up from slumber mode.
147 for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
148 i < SATA_TOP_MAX_PHYS;
149 i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
150 if (priv->port_mask & BIT(i))
152 hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
156 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
158 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
159 (port * SATA_TOP_CTRL_PHY_OFFS);
163 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
166 /* clear PHY_DEFAULT_POWER_STATE */
167 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
168 reg = brcm_sata_readreg(p);
169 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
170 brcm_sata_writereg(reg, p);
172 /* reset the PHY digital logic */
173 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
174 reg = brcm_sata_readreg(p);
175 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
176 SATA_TOP_CTRL_2_SW_RST_RX);
177 reg |= SATA_TOP_CTRL_2_SW_RST_TX;
178 brcm_sata_writereg(reg, p);
179 reg = brcm_sata_readreg(p);
180 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
181 brcm_sata_writereg(reg, p);
182 reg = brcm_sata_readreg(p);
183 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
184 brcm_sata_writereg(reg, p);
185 (void)brcm_sata_readreg(p);
188 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
190 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
191 (port * SATA_TOP_CTRL_PHY_OFFS);
195 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
198 /* power-off the PHY digital logic */
199 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
200 reg = brcm_sata_readreg(p);
201 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
202 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
203 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
204 brcm_sata_writereg(reg, p);
206 /* set PHY_DEFAULT_POWER_STATE */
207 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
208 reg = brcm_sata_readreg(p);
209 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
210 brcm_sata_writereg(reg, p);
213 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
217 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
218 if (priv->port_mask & BIT(i))
219 brcm_sata_phy_enable(priv, i);
222 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
226 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
227 if (priv->port_mask & BIT(i))
228 brcm_sata_phy_disable(priv, i);
231 static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
232 struct brcm_ahci_priv *priv)
236 impl = readl(hpriv->mmio + HOST_PORTS_IMPL);
238 if (fls(impl) > SATA_TOP_MAX_PHYS)
239 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
242 dev_info(priv->dev, "no ports found\n");
247 static void brcm_sata_init(struct brcm_ahci_priv *priv)
249 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
251 /* Configure endianness */
252 if (priv->version == BRCM_SATA_NSP) {
253 u32 data = brcm_sata_readreg(ctrl);
255 data &= ~((0x03 << DMADATA_ENDIAN_SHIFT) |
256 (0x03 << DMADESC_ENDIAN_SHIFT));
257 data |= (0x02 << DMADATA_ENDIAN_SHIFT) |
258 (0x02 << DMADESC_ENDIAN_SHIFT);
259 brcm_sata_writereg(data, ctrl);
261 brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, ctrl);
264 #ifdef CONFIG_PM_SLEEP
265 static int brcm_ahci_suspend(struct device *dev)
267 struct ata_host *host = dev_get_drvdata(dev);
268 struct ahci_host_priv *hpriv = host->private_data;
269 struct brcm_ahci_priv *priv = hpriv->plat_data;
271 brcm_sata_phys_disable(priv);
273 return ahci_platform_suspend(dev);
276 static int brcm_ahci_resume(struct device *dev)
278 struct ata_host *host = dev_get_drvdata(dev);
279 struct ahci_host_priv *hpriv = host->private_data;
280 struct brcm_ahci_priv *priv = hpriv->plat_data;
283 /* Make sure clocks are turned on before re-configuration */
284 ret = ahci_platform_enable_clks(hpriv);
288 ret = ahci_platform_enable_regulators(hpriv);
290 goto out_disable_clks;
292 brcm_sata_init(priv);
293 brcm_sata_phys_enable(priv);
294 brcm_sata_alpm_init(hpriv);
296 /* Since we had to enable clocks earlier on, we cannot use
297 * ahci_platform_resume() as-is since a second call to
298 * ahci_platform_enable_resources() would bump up the resources
299 * (regulators, clocks, PHYs) count artificially so we copy the part
300 * after ahci_platform_enable_resources().
302 ret = ahci_platform_enable_phys(hpriv);
304 goto out_disable_phys;
306 ret = ahci_platform_resume_host(dev);
308 goto out_disable_platform_phys;
310 /* We resumed so update PM runtime state */
311 pm_runtime_disable(dev);
312 pm_runtime_set_active(dev);
313 pm_runtime_enable(dev);
317 out_disable_platform_phys:
318 ahci_platform_disable_phys(hpriv);
320 brcm_sata_phys_disable(priv);
321 ahci_platform_disable_regulators(hpriv);
323 ahci_platform_disable_clks(hpriv);
328 static struct scsi_host_template ahci_platform_sht = {
332 static const struct of_device_id ahci_of_match[] = {
333 {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
334 {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
335 {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
338 MODULE_DEVICE_TABLE(of, ahci_of_match);
340 static int brcm_ahci_probe(struct platform_device *pdev)
342 const struct of_device_id *of_id;
343 struct device *dev = &pdev->dev;
344 struct brcm_ahci_priv *priv;
345 struct ahci_host_priv *hpriv;
346 struct resource *res;
349 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
353 of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
357 priv->version = (enum brcm_ahci_version)of_id->data;
360 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
361 priv->top_ctrl = devm_ioremap_resource(dev, res);
362 if (IS_ERR(priv->top_ctrl))
363 return PTR_ERR(priv->top_ctrl);
365 /* Reset is optional depending on platform */
366 priv->rcdev = devm_reset_control_get(&pdev->dev, "ahci");
367 if (!IS_ERR_OR_NULL(priv->rcdev))
368 reset_control_deassert(priv->rcdev);
370 if ((priv->version == BRCM_SATA_BCM7425) ||
371 (priv->version == BRCM_SATA_NSP)) {
372 priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
373 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
376 hpriv = ahci_platform_get_resources(pdev);
378 ret = PTR_ERR(hpriv);
382 ret = ahci_platform_enable_clks(hpriv);
386 ret = ahci_platform_enable_regulators(hpriv);
388 goto out_disable_clks;
390 /* Must be first so as to configure endianness including that
391 * of the standard AHCI register space.
393 brcm_sata_init(priv);
395 /* Initializes priv->port_mask which is used below */
396 priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
397 if (!priv->port_mask) {
399 goto out_disable_regulators;
402 /* Must be done before ahci_platform_enable_phys() */
403 brcm_sata_phys_enable(priv);
405 hpriv->plat_data = priv;
406 hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP;
408 brcm_sata_alpm_init(hpriv);
410 if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
411 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
413 ret = ahci_platform_enable_phys(hpriv);
415 goto out_disable_phys;
417 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
420 goto out_disable_platform_phys;
422 dev_info(dev, "Broadcom AHCI SATA3 registered\n");
426 out_disable_platform_phys:
427 ahci_platform_disable_phys(hpriv);
429 brcm_sata_phys_disable(priv);
430 out_disable_regulators:
431 ahci_platform_disable_regulators(hpriv);
433 ahci_platform_disable_clks(hpriv);
435 if (!IS_ERR_OR_NULL(priv->rcdev))
436 reset_control_assert(priv->rcdev);
440 static int brcm_ahci_remove(struct platform_device *pdev)
442 struct ata_host *host = dev_get_drvdata(&pdev->dev);
443 struct ahci_host_priv *hpriv = host->private_data;
444 struct brcm_ahci_priv *priv = hpriv->plat_data;
447 brcm_sata_phys_disable(priv);
449 ret = ata_platform_remove_one(pdev);
456 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
458 static struct platform_driver brcm_ahci_driver = {
459 .probe = brcm_ahci_probe,
460 .remove = brcm_ahci_remove,
463 .of_match_table = ahci_of_match,
464 .pm = &ahci_brcm_pm_ops,
467 module_platform_driver(brcm_ahci_driver);
469 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
470 MODULE_AUTHOR("Brian Norris");
471 MODULE_LICENSE("GPL");
472 MODULE_ALIAS("platform:sata-brcmstb");