2 * Broadcom SATA3 AHCI Controller Driver
4 * Copyright © 2009-2015 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/ahci_platform.h>
18 #include <linux/compiler.h>
19 #include <linux/device.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/libata.h>
25 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/reset.h>
29 #include <linux/string.h>
33 #define DRV_NAME "brcm-ahci"
35 #define SATA_TOP_CTRL_VERSION 0x0
36 #define SATA_TOP_CTRL_BUS_CTRL 0x4
37 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
38 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
39 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
40 #define PIODATA_ENDIAN_SHIFT 6
41 #define ENDIAN_SWAP_NONE 0
42 #define ENDIAN_SWAP_FULL 2
43 #define SATA_TOP_CTRL_TP_CTRL 0x8
44 #define SATA_TOP_CTRL_PHY_CTRL 0xc
45 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0
46 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
47 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4
48 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
49 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
50 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
51 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
52 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
53 #define SATA_TOP_CTRL_PHY_OFFS 0x8
54 #define SATA_TOP_MAX_PHYS 2
56 #define SATA_FIRST_PORT_CTRL 0x700
57 #define SATA_NEXT_PORT_CTRL_OFFSET 0x80
58 #define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
60 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
61 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
62 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
63 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
69 #define BUS_CTRL_ENDIAN_CONF \
70 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \
71 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
72 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
74 enum brcm_ahci_version {
75 BRCM_SATA_BCM7425 = 1,
80 enum brcm_ahci_quirks {
81 BRCM_AHCI_QUIRK_NO_NCQ = BIT(0),
82 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
85 struct brcm_ahci_priv {
87 void __iomem *top_ctrl;
90 enum brcm_ahci_version version;
91 struct reset_control *rcdev;
94 static const struct ata_port_info ahci_brcm_port_info = {
95 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
96 .link_flags = ATA_LFLAG_NO_DB_DELAY,
98 .udma_mask = ATA_UDMA6,
99 .port_ops = &ahci_platform_ops,
102 static inline u32 brcm_sata_readreg(void __iomem *addr)
105 * MIPS endianness is configured by boot strap, which also reverses all
106 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
109 * Other architectures (e.g., ARM) either do not support big endian, or
110 * else leave I/O in little endian mode.
112 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
113 return __raw_readl(addr);
115 return readl_relaxed(addr);
118 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
120 /* See brcm_sata_readreg() comments */
121 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
122 __raw_writel(val, addr);
124 writel_relaxed(val, addr);
127 static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
129 struct brcm_ahci_priv *priv = hpriv->plat_data;
130 u32 port_ctrl, host_caps;
133 /* Enable support for ALPM */
134 host_caps = readl(hpriv->mmio + HOST_CAP);
135 if (!(host_caps & HOST_CAP_ALPM))
136 hpriv->flags |= AHCI_HFLAG_YES_ALPM;
139 * Adjust timeout to allow PLL sufficient time to lock while waking
140 * up from slumber mode.
142 for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
143 i < SATA_TOP_MAX_PHYS;
144 i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
145 if (priv->port_mask & BIT(i))
147 hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
151 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
153 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
154 (port * SATA_TOP_CTRL_PHY_OFFS);
158 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
161 /* clear PHY_DEFAULT_POWER_STATE */
162 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
163 reg = brcm_sata_readreg(p);
164 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
165 brcm_sata_writereg(reg, p);
167 /* reset the PHY digital logic */
168 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
169 reg = brcm_sata_readreg(p);
170 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
171 SATA_TOP_CTRL_2_SW_RST_RX);
172 reg |= SATA_TOP_CTRL_2_SW_RST_TX;
173 brcm_sata_writereg(reg, p);
174 reg = brcm_sata_readreg(p);
175 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
176 brcm_sata_writereg(reg, p);
177 reg = brcm_sata_readreg(p);
178 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
179 brcm_sata_writereg(reg, p);
180 (void)brcm_sata_readreg(p);
183 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
185 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
186 (port * SATA_TOP_CTRL_PHY_OFFS);
190 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
193 /* power-off the PHY digital logic */
194 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
195 reg = brcm_sata_readreg(p);
196 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
197 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
198 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
199 brcm_sata_writereg(reg, p);
201 /* set PHY_DEFAULT_POWER_STATE */
202 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
203 reg = brcm_sata_readreg(p);
204 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
205 brcm_sata_writereg(reg, p);
208 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
212 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
213 if (priv->port_mask & BIT(i))
214 brcm_sata_phy_enable(priv, i);
217 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
221 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
222 if (priv->port_mask & BIT(i))
223 brcm_sata_phy_disable(priv, i);
226 static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv,
227 struct brcm_ahci_priv *priv)
231 impl = readl(hpriv->mmio + HOST_PORTS_IMPL);
233 if (fls(impl) > SATA_TOP_MAX_PHYS)
234 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
237 dev_info(priv->dev, "no ports found\n");
242 static void brcm_sata_init(struct brcm_ahci_priv *priv)
244 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
246 /* Configure endianness */
247 if (priv->version == BRCM_SATA_NSP) {
248 u32 data = brcm_sata_readreg(ctrl);
250 data &= ~((0x03 << DMADATA_ENDIAN_SHIFT) |
251 (0x03 << DMADESC_ENDIAN_SHIFT));
252 data |= (0x02 << DMADATA_ENDIAN_SHIFT) |
253 (0x02 << DMADESC_ENDIAN_SHIFT);
254 brcm_sata_writereg(data, ctrl);
256 brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, ctrl);
259 #ifdef CONFIG_PM_SLEEP
260 static int brcm_ahci_suspend(struct device *dev)
262 struct ata_host *host = dev_get_drvdata(dev);
263 struct ahci_host_priv *hpriv = host->private_data;
264 struct brcm_ahci_priv *priv = hpriv->plat_data;
266 brcm_sata_phys_disable(priv);
268 return ahci_platform_suspend(dev);
271 static int brcm_ahci_resume(struct device *dev)
273 struct ata_host *host = dev_get_drvdata(dev);
274 struct ahci_host_priv *hpriv = host->private_data;
275 struct brcm_ahci_priv *priv = hpriv->plat_data;
278 /* Make sure clocks are turned on before re-configuration */
279 ret = ahci_platform_enable_clks(hpriv);
283 ret = ahci_platform_enable_regulators(hpriv);
285 goto out_disable_clks;
287 brcm_sata_init(priv);
288 brcm_sata_phys_enable(priv);
289 brcm_sata_alpm_init(hpriv);
291 /* Since we had to enable clocks earlier on, we cannot use
292 * ahci_platform_resume() as-is since a second call to
293 * ahci_platform_enable_resources() would bump up the resources
294 * (regulators, clocks, PHYs) count artificially so we copy the part
295 * after ahci_platform_enable_resources().
297 ret = ahci_platform_enable_phys(hpriv);
299 goto out_disable_phys;
301 ret = ahci_platform_resume_host(dev);
303 goto out_disable_platform_phys;
305 /* We resumed so update PM runtime state */
306 pm_runtime_disable(dev);
307 pm_runtime_set_active(dev);
308 pm_runtime_enable(dev);
312 out_disable_platform_phys:
313 ahci_platform_disable_phys(hpriv);
315 brcm_sata_phys_disable(priv);
316 ahci_platform_disable_regulators(hpriv);
318 ahci_platform_disable_clks(hpriv);
323 static struct scsi_host_template ahci_platform_sht = {
327 static const struct of_device_id ahci_of_match[] = {
328 {.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
329 {.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
330 {.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
333 MODULE_DEVICE_TABLE(of, ahci_of_match);
335 static int brcm_ahci_probe(struct platform_device *pdev)
337 const struct of_device_id *of_id;
338 struct device *dev = &pdev->dev;
339 struct brcm_ahci_priv *priv;
340 struct ahci_host_priv *hpriv;
341 struct resource *res;
344 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
348 of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
352 priv->version = (enum brcm_ahci_version)of_id->data;
355 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
356 priv->top_ctrl = devm_ioremap_resource(dev, res);
357 if (IS_ERR(priv->top_ctrl))
358 return PTR_ERR(priv->top_ctrl);
360 /* Reset is optional depending on platform */
361 priv->rcdev = devm_reset_control_get(&pdev->dev, "ahci");
362 if (!IS_ERR_OR_NULL(priv->rcdev))
363 reset_control_deassert(priv->rcdev);
365 if ((priv->version == BRCM_SATA_BCM7425) ||
366 (priv->version == BRCM_SATA_NSP)) {
367 priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
368 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
371 hpriv = ahci_platform_get_resources(pdev);
373 ret = PTR_ERR(hpriv);
377 ret = ahci_platform_enable_clks(hpriv);
381 ret = ahci_platform_enable_regulators(hpriv);
383 goto out_disable_clks;
385 /* Must be first so as to configure endianness including that
386 * of the standard AHCI register space.
388 brcm_sata_init(priv);
390 /* Initializes priv->port_mask which is used below */
391 priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
392 if (!priv->port_mask) {
394 goto out_disable_regulators;
397 /* Must be done before ahci_platform_enable_phys() */
398 brcm_sata_phys_enable(priv);
400 hpriv->plat_data = priv;
401 hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP;
403 brcm_sata_alpm_init(hpriv);
405 if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
406 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
407 hpriv->flags |= AHCI_HFLAG_NO_WRITE_TO_RO;
409 ret = ahci_platform_enable_phys(hpriv);
411 goto out_disable_phys;
413 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
416 goto out_disable_platform_phys;
418 dev_info(dev, "Broadcom AHCI SATA3 registered\n");
422 out_disable_platform_phys:
423 ahci_platform_disable_phys(hpriv);
425 brcm_sata_phys_disable(priv);
426 out_disable_regulators:
427 ahci_platform_disable_regulators(hpriv);
429 ahci_platform_disable_clks(hpriv);
431 if (!IS_ERR_OR_NULL(priv->rcdev))
432 reset_control_assert(priv->rcdev);
436 static int brcm_ahci_remove(struct platform_device *pdev)
438 struct ata_host *host = dev_get_drvdata(&pdev->dev);
439 struct ahci_host_priv *hpriv = host->private_data;
440 struct brcm_ahci_priv *priv = hpriv->plat_data;
443 brcm_sata_phys_disable(priv);
445 ret = ata_platform_remove_one(pdev);
452 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
454 static struct platform_driver brcm_ahci_driver = {
455 .probe = brcm_ahci_probe,
456 .remove = brcm_ahci_remove,
459 .of_match_table = ahci_of_match,
460 .pm = &ahci_brcm_pm_ops,
463 module_platform_driver(brcm_ahci_driver);
465 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
466 MODULE_AUTHOR("Brian Norris");
467 MODULE_LICENSE("GPL");
468 MODULE_ALIAS("platform:sata-brcmstb");