2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
62 /* board IDs by feature in alphabetical order */
70 /* board IDs for specific chipsets in alphabetical order */
77 board_ahci_sb700, /* for SB700 and SB800 */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static void ahci_remove_one(struct pci_dev *dev);
89 static void ahci_shutdown_one(struct pci_dev *dev);
90 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
95 static bool is_mcp89_apple(struct pci_dev *pdev);
96 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
97 unsigned long deadline);
99 static int ahci_pci_device_runtime_suspend(struct device *dev);
100 static int ahci_pci_device_runtime_resume(struct device *dev);
101 #ifdef CONFIG_PM_SLEEP
102 static int ahci_pci_device_suspend(struct device *dev);
103 static int ahci_pci_device_resume(struct device *dev);
105 #endif /* CONFIG_PM */
107 static struct scsi_host_template ahci_sht = {
111 static struct ata_port_operations ahci_vt8251_ops = {
112 .inherits = &ahci_ops,
113 .hardreset = ahci_vt8251_hardreset,
116 static struct ata_port_operations ahci_p5wdh_ops = {
117 .inherits = &ahci_ops,
118 .hardreset = ahci_p5wdh_hardreset,
121 static struct ata_port_operations ahci_avn_ops = {
122 .inherits = &ahci_ops,
123 .hardreset = ahci_avn_hardreset,
126 static const struct ata_port_info ahci_port_info[] = {
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_ign_iferr] = {
135 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
141 [board_ahci_nomsi] = {
142 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
148 [board_ahci_noncq] = {
149 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
150 .flags = AHCI_FLAG_COMMON,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
155 [board_ahci_nosntf] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
162 [board_ahci_yes_fbs] = {
163 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_avn_ops,
176 [board_ahci_mcp65] = {
177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
179 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
184 [board_ahci_mcp77] = {
185 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_ops,
191 [board_ahci_mcp89] = {
192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
199 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
200 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
201 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_ops,
206 [board_ahci_sb600] = {
207 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
208 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
209 AHCI_HFLAG_32BIT_ONLY),
210 .flags = AHCI_FLAG_COMMON,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_pmp_retry_srst_ops,
215 [board_ahci_sb700] = { /* for SB700 and SB800 */
216 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
217 .flags = AHCI_FLAG_COMMON,
218 .pio_mask = ATA_PIO4,
219 .udma_mask = ATA_UDMA6,
220 .port_ops = &ahci_pmp_retry_srst_ops,
222 [board_ahci_vt8251] = {
223 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
224 .flags = AHCI_FLAG_COMMON,
225 .pio_mask = ATA_PIO4,
226 .udma_mask = ATA_UDMA6,
227 .port_ops = &ahci_vt8251_ops,
231 static const struct pci_device_id ahci_pci_tbl[] = {
233 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
234 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
235 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
236 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
237 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
238 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
239 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
240 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
241 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
243 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
244 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
245 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
246 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
247 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
248 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
249 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
250 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
255 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
259 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
261 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
262 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
263 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
264 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
265 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
266 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
268 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
269 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
270 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
271 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
272 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
294 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
296 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
297 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
298 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
299 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
300 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
301 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
302 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
303 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
304 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
305 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
307 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
308 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
310 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
312 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
313 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
314 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
315 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
317 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
319 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
320 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
321 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
322 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
323 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
328 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
329 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
330 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
331 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
336 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
337 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
338 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
344 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
346 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
350 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
354 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
355 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
359 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
360 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
361 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
362 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
364 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
366 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
367 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
368 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
369 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
370 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
371 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
372 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
373 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
374 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
375 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
379 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
380 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
384 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
388 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
389 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
390 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
391 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
393 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
394 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
395 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
396 /* JMicron 362B and 362C have an AHCI function with IDE class code */
397 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
398 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
399 /* May need to update quirk_jmicron_async_suspend() for additions */
402 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
403 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
405 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
411 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
412 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
413 /* AMD is using RAID class only for ahci controllers */
414 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
415 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
418 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
419 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
422 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
508 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
509 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
510 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
512 /* ST Microelectronics */
513 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
516 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
517 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
519 .class = PCI_CLASS_STORAGE_SATA_AHCI,
520 .class_mask = 0xffffff,
521 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
522 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
523 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
524 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
525 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
526 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
532 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
534 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
536 .driver_data = board_ahci_yes_fbs },
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
540 .driver_data = board_ahci_yes_fbs },
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
542 .driver_data = board_ahci_yes_fbs },
543 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
544 .driver_data = board_ahci_yes_fbs },
545 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
546 .driver_data = board_ahci_yes_fbs },
549 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
550 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
553 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
554 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
555 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
556 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
559 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
560 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
562 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
563 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
566 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
568 /* Generic, PCI class code for AHCI */
569 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
570 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
572 { } /* terminate list */
575 static const struct dev_pm_ops ahci_pci_pm_ops = {
576 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
577 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
578 ahci_pci_device_runtime_resume, NULL)
581 static struct pci_driver ahci_pci_driver = {
583 .id_table = ahci_pci_tbl,
584 .probe = ahci_init_one,
585 .remove = ahci_remove_one,
586 .shutdown = ahci_shutdown_one,
588 .pm = &ahci_pci_pm_ops,
592 #if IS_ENABLED(CONFIG_PATA_MARVELL)
593 static int marvell_enable;
595 static int marvell_enable = 1;
597 module_param(marvell_enable, int, 0644);
598 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
601 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
602 struct ahci_host_priv *hpriv)
604 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
605 dev_info(&pdev->dev, "JMB361 has only one port\n");
606 hpriv->force_port_map = 1;
610 * Temporary Marvell 6145 hack: PATA port presence
611 * is asserted through the standard AHCI port
612 * presence register, as bit 4 (counting from 0)
614 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
615 if (pdev->device == 0x6121)
616 hpriv->mask_port_map = 0x3;
618 hpriv->mask_port_map = 0xf;
620 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
623 ahci_save_initial_config(&pdev->dev, hpriv);
626 static int ahci_pci_reset_controller(struct ata_host *host)
628 struct pci_dev *pdev = to_pci_dev(host->dev);
631 rc = ahci_reset_controller(host);
635 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
636 struct ahci_host_priv *hpriv = host->private_data;
640 pci_read_config_word(pdev, 0x92, &tmp16);
641 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
642 tmp16 |= hpriv->port_map;
643 pci_write_config_word(pdev, 0x92, tmp16);
650 static void ahci_pci_init_controller(struct ata_host *host)
652 struct ahci_host_priv *hpriv = host->private_data;
653 struct pci_dev *pdev = to_pci_dev(host->dev);
654 void __iomem *port_mmio;
658 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
659 if (pdev->device == 0x6121)
663 port_mmio = __ahci_port_base(host, mv);
665 writel(0, port_mmio + PORT_IRQ_MASK);
668 tmp = readl(port_mmio + PORT_IRQ_STAT);
669 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
671 writel(tmp, port_mmio + PORT_IRQ_STAT);
674 ahci_init_controller(host);
677 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
678 unsigned long deadline)
680 struct ata_port *ap = link->ap;
681 struct ahci_host_priv *hpriv = ap->host->private_data;
687 ahci_stop_engine(ap);
689 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
690 deadline, &online, NULL);
692 hpriv->start_engine(ap);
694 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
696 /* vt8251 doesn't clear BSY on signature FIS reception,
697 * request follow-up softreset.
699 return online ? -EAGAIN : rc;
702 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
705 struct ata_port *ap = link->ap;
706 struct ahci_port_priv *pp = ap->private_data;
707 struct ahci_host_priv *hpriv = ap->host->private_data;
708 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
709 struct ata_taskfile tf;
713 ahci_stop_engine(ap);
715 /* clear D2H reception area to properly wait for D2H FIS */
716 ata_tf_init(link->device, &tf);
717 tf.command = ATA_BUSY;
718 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
720 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
721 deadline, &online, NULL);
723 hpriv->start_engine(ap);
725 /* The pseudo configuration device on SIMG4726 attached to
726 * ASUS P5W-DH Deluxe doesn't send signature FIS after
727 * hardreset if no device is attached to the first downstream
728 * port && the pseudo device locks up on SRST w/ PMP==0. To
729 * work around this, wait for !BSY only briefly. If BSY isn't
730 * cleared, perform CLO and proceed to IDENTIFY (achieved by
731 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
733 * Wait for two seconds. Devices attached to downstream port
734 * which can't process the following IDENTIFY after this will
735 * have to be reset again. For most cases, this should
736 * suffice while making probing snappish enough.
739 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
742 ahci_kick_engine(ap);
748 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
750 * It has been observed with some SSDs that the timing of events in the
751 * link synchronization phase can leave the port in a state that can not
752 * be recovered by a SATA-hard-reset alone. The failing signature is
753 * SStatus.DET stuck at 1 ("Device presence detected but Phy
754 * communication not established"). It was found that unloading and
755 * reloading the driver when this problem occurs allows the drive
756 * connection to be recovered (DET advanced to 0x3). The critical
757 * component of reloading the driver is that the port state machines are
758 * reset by bouncing "port enable" in the AHCI PCS configuration
759 * register. So, reproduce that effect by bouncing a port whenever we
760 * see DET==1 after a reset.
762 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
763 unsigned long deadline)
765 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
766 struct ata_port *ap = link->ap;
767 struct ahci_port_priv *pp = ap->private_data;
768 struct ahci_host_priv *hpriv = ap->host->private_data;
769 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
770 unsigned long tmo = deadline - jiffies;
771 struct ata_taskfile tf;
777 ahci_stop_engine(ap);
779 for (i = 0; i < 2; i++) {
782 int port = ap->port_no;
783 struct ata_host *host = ap->host;
784 struct pci_dev *pdev = to_pci_dev(host->dev);
786 /* clear D2H reception area to properly wait for D2H FIS */
787 ata_tf_init(link->device, &tf);
788 tf.command = ATA_BUSY;
789 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
791 rc = sata_link_hardreset(link, timing, deadline, &online,
794 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
795 (sstatus & 0xf) != 1)
798 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
801 pci_read_config_word(pdev, 0x92, &val);
803 pci_write_config_word(pdev, 0x92, val);
804 ata_msleep(ap, 1000);
806 pci_write_config_word(pdev, 0x92, val);
810 hpriv->start_engine(ap);
813 *class = ahci_dev_classify(ap);
815 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
821 static void ahci_pci_disable_interrupts(struct ata_host *host)
823 struct ahci_host_priv *hpriv = host->private_data;
824 void __iomem *mmio = hpriv->mmio;
827 /* AHCI spec rev1.1 section 8.3.3:
828 * Software must disable interrupts prior to requesting a
829 * transition of the HBA to D3 state.
831 ctl = readl(mmio + HOST_CTL);
833 writel(ctl, mmio + HOST_CTL);
834 readl(mmio + HOST_CTL); /* flush */
837 static int ahci_pci_device_runtime_suspend(struct device *dev)
839 struct pci_dev *pdev = to_pci_dev(dev);
840 struct ata_host *host = pci_get_drvdata(pdev);
842 ahci_pci_disable_interrupts(host);
846 static int ahci_pci_device_runtime_resume(struct device *dev)
848 struct pci_dev *pdev = to_pci_dev(dev);
849 struct ata_host *host = pci_get_drvdata(pdev);
852 rc = ahci_pci_reset_controller(host);
855 ahci_pci_init_controller(host);
859 #ifdef CONFIG_PM_SLEEP
860 static int ahci_pci_device_suspend(struct device *dev)
862 struct pci_dev *pdev = to_pci_dev(dev);
863 struct ata_host *host = pci_get_drvdata(pdev);
864 struct ahci_host_priv *hpriv = host->private_data;
866 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
868 "BIOS update required for suspend/resume\n");
872 ahci_pci_disable_interrupts(host);
873 return ata_host_suspend(host, PMSG_SUSPEND);
876 static int ahci_pci_device_resume(struct device *dev)
878 struct pci_dev *pdev = to_pci_dev(dev);
879 struct ata_host *host = pci_get_drvdata(pdev);
882 /* Apple BIOS helpfully mangles the registers on resume */
883 if (is_mcp89_apple(pdev))
884 ahci_mcp89_apple_enable(pdev);
886 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
887 rc = ahci_pci_reset_controller(host);
891 ahci_pci_init_controller(host);
894 ata_host_resume(host);
900 #endif /* CONFIG_PM */
902 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
907 * If the device fixup already set the dma_mask to some non-standard
908 * value, don't extend it here. This happens on STA2X11, for example.
910 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
914 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
915 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
917 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
920 "64-bit DMA enable failed\n");
925 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
927 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
930 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
933 "32-bit consistent DMA enable failed\n");
940 static void ahci_pci_print_info(struct ata_host *host)
942 struct pci_dev *pdev = to_pci_dev(host->dev);
946 pci_read_config_word(pdev, 0x0a, &cc);
947 if (cc == PCI_CLASS_STORAGE_IDE)
949 else if (cc == PCI_CLASS_STORAGE_SATA)
951 else if (cc == PCI_CLASS_STORAGE_RAID)
956 ahci_print_info(host, scc_s);
959 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
960 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
961 * support PMP and the 4726 either directly exports the device
962 * attached to the first downstream port or acts as a hardware storage
963 * controller and emulate a single ATA device (can be RAID 0/1 or some
964 * other configuration).
966 * When there's no device attached to the first downstream port of the
967 * 4726, "Config Disk" appears, which is a pseudo ATA device to
968 * configure the 4726. However, ATA emulation of the device is very
969 * lame. It doesn't send signature D2H Reg FIS after the initial
970 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
972 * The following function works around the problem by always using
973 * hardreset on the port and not depending on receiving signature FIS
974 * afterward. If signature FIS isn't received soon, ATA class is
975 * assumed without follow-up softreset.
977 static void ahci_p5wdh_workaround(struct ata_host *host)
979 static const struct dmi_system_id sysids[] = {
981 .ident = "P5W DH Deluxe",
983 DMI_MATCH(DMI_SYS_VENDOR,
984 "ASUSTEK COMPUTER INC"),
985 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
990 struct pci_dev *pdev = to_pci_dev(host->dev);
992 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
993 dmi_check_system(sysids)) {
994 struct ata_port *ap = host->ports[1];
997 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
999 ap->ops = &ahci_p5wdh_ops;
1000 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1005 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1006 * booting in BIOS compatibility mode. We restore the registers but not ID.
1008 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1012 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1014 pci_read_config_dword(pdev, 0xf8, &val);
1016 /* the following changes the device ID, but appears not to affect function */
1017 /* val = (val & ~0xf0000000) | 0x80000000; */
1018 pci_write_config_dword(pdev, 0xf8, val);
1020 pci_read_config_dword(pdev, 0x54c, &val);
1022 pci_write_config_dword(pdev, 0x54c, val);
1024 pci_read_config_dword(pdev, 0x4a4, &val);
1027 pci_write_config_dword(pdev, 0x4a4, val);
1029 pci_read_config_dword(pdev, 0x54c, &val);
1031 pci_write_config_dword(pdev, 0x54c, val);
1033 pci_read_config_dword(pdev, 0xf8, &val);
1034 val &= ~(1 << 0x1b);
1035 pci_write_config_dword(pdev, 0xf8, val);
1038 static bool is_mcp89_apple(struct pci_dev *pdev)
1040 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1041 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1042 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1043 pdev->subsystem_device == 0xcb89;
1046 /* only some SB600 ahci controllers can do 64bit DMA */
1047 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1049 static const struct dmi_system_id sysids[] = {
1051 * The oldest version known to be broken is 0901 and
1052 * working is 1501 which was released on 2007-10-26.
1053 * Enable 64bit DMA on 1501 and anything newer.
1055 * Please read bko#9412 for more info.
1058 .ident = "ASUS M2A-VM",
1060 DMI_MATCH(DMI_BOARD_VENDOR,
1061 "ASUSTeK Computer INC."),
1062 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1064 .driver_data = "20071026", /* yyyymmdd */
1067 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1068 * support 64bit DMA.
1070 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1071 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1072 * This spelling mistake was fixed in BIOS version 1.5, so
1073 * 1.5 and later have the Manufacturer as
1074 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1075 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1077 * BIOS versions earlier than 1.9 had a Board Product Name
1078 * DMI field of "MS-7376". This was changed to be
1079 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1080 * match on DMI_BOARD_NAME of "MS-7376".
1083 .ident = "MSI K9A2 Platinum",
1085 DMI_MATCH(DMI_BOARD_VENDOR,
1086 "MICRO-STAR INTER"),
1087 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1091 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1094 * This board also had the typo mentioned above in the
1095 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1096 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1099 .ident = "MSI K9AGM2",
1101 DMI_MATCH(DMI_BOARD_VENDOR,
1102 "MICRO-STAR INTER"),
1103 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1107 * All BIOS versions for the Asus M3A support 64bit DMA.
1108 * (all release versions from 0301 to 1206 were tested)
1111 .ident = "ASUS M3A",
1113 DMI_MATCH(DMI_BOARD_VENDOR,
1114 "ASUSTeK Computer INC."),
1115 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1120 const struct dmi_system_id *match;
1121 int year, month, date;
1124 match = dmi_first_match(sysids);
1125 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1129 if (!match->driver_data)
1132 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1133 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1135 if (strcmp(buf, match->driver_data) >= 0)
1138 dev_warn(&pdev->dev,
1139 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1145 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1149 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1151 static const struct dmi_system_id broken_systems[] = {
1153 .ident = "HP Compaq nx6310",
1155 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1156 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1158 /* PCI slot number of the controller */
1159 .driver_data = (void *)0x1FUL,
1162 .ident = "HP Compaq 6720s",
1164 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1165 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1167 /* PCI slot number of the controller */
1168 .driver_data = (void *)0x1FUL,
1171 { } /* terminate list */
1173 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1176 unsigned long slot = (unsigned long)dmi->driver_data;
1177 /* apply the quirk only to on-board controllers */
1178 return slot == PCI_SLOT(pdev->devfn);
1184 static bool ahci_broken_suspend(struct pci_dev *pdev)
1186 static const struct dmi_system_id sysids[] = {
1188 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1189 * to the harddisk doesn't become online after
1190 * resuming from STR. Warn and fail suspend.
1192 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1194 * Use dates instead of versions to match as HP is
1195 * apparently recycling both product and version
1198 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1203 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1204 DMI_MATCH(DMI_PRODUCT_NAME,
1205 "HP Pavilion dv4 Notebook PC"),
1207 .driver_data = "20090105", /* F.30 */
1212 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1213 DMI_MATCH(DMI_PRODUCT_NAME,
1214 "HP Pavilion dv5 Notebook PC"),
1216 .driver_data = "20090506", /* F.16 */
1221 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1222 DMI_MATCH(DMI_PRODUCT_NAME,
1223 "HP Pavilion dv6 Notebook PC"),
1225 .driver_data = "20090423", /* F.21 */
1230 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1231 DMI_MATCH(DMI_PRODUCT_NAME,
1232 "HP HDX18 Notebook PC"),
1234 .driver_data = "20090430", /* F.23 */
1237 * Acer eMachines G725 has the same problem. BIOS
1238 * V1.03 is known to be broken. V3.04 is known to
1239 * work. Between, there are V1.06, V2.06 and V3.03
1240 * that we don't have much idea about. For now,
1241 * blacklist anything older than V3.04.
1243 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1248 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1249 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1251 .driver_data = "20091216", /* V3.04 */
1253 { } /* terminate list */
1255 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1256 int year, month, date;
1259 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1262 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1263 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1265 return strcmp(buf, dmi->driver_data) < 0;
1268 static bool ahci_broken_lpm(struct pci_dev *pdev)
1270 static const struct dmi_system_id sysids[] = {
1271 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1274 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1275 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1277 .driver_data = "20180406", /* 1.31 */
1281 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1282 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1284 .driver_data = "20180420", /* 1.28 */
1288 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1289 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1291 .driver_data = "20180315", /* 1.33 */
1295 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1296 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1299 * Note date based on release notes, 2.35 has been
1300 * reported to be good, but I've been unable to get
1301 * a hold of the reporter to get the DMI BIOS date.
1304 .driver_data = "20180310", /* 2.35 */
1306 { } /* terminate list */
1308 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1309 int year, month, date;
1315 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1316 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1318 return strcmp(buf, dmi->driver_data) < 0;
1321 static bool ahci_broken_online(struct pci_dev *pdev)
1323 #define ENCODE_BUSDEVFN(bus, slot, func) \
1324 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1325 static const struct dmi_system_id sysids[] = {
1327 * There are several gigabyte boards which use
1328 * SIMG5723s configured as hardware RAID. Certain
1329 * 5723 firmware revisions shipped there keep the link
1330 * online but fail to answer properly to SRST or
1331 * IDENTIFY when no device is attached downstream
1332 * causing libata to retry quite a few times leading
1333 * to excessive detection delay.
1335 * As these firmwares respond to the second reset try
1336 * with invalid device signature, considering unknown
1337 * sig as offline works around the problem acceptably.
1340 .ident = "EP45-DQ6",
1342 DMI_MATCH(DMI_BOARD_VENDOR,
1343 "Gigabyte Technology Co., Ltd."),
1344 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1346 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1349 .ident = "EP45-DS5",
1351 DMI_MATCH(DMI_BOARD_VENDOR,
1352 "Gigabyte Technology Co., Ltd."),
1353 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1355 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1357 { } /* terminate list */
1359 #undef ENCODE_BUSDEVFN
1360 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1366 val = (unsigned long)dmi->driver_data;
1368 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1371 static bool ahci_broken_devslp(struct pci_dev *pdev)
1373 /* device with broken DEVSLP but still showing SDS capability */
1374 static const struct pci_device_id ids[] = {
1375 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1379 return pci_match_id(ids, pdev);
1382 #ifdef CONFIG_ATA_ACPI
1383 static void ahci_gtf_filter_workaround(struct ata_host *host)
1385 static const struct dmi_system_id sysids[] = {
1387 * Aspire 3810T issues a bunch of SATA enable commands
1388 * via _GTF including an invalid one and one which is
1389 * rejected by the device. Among the successful ones
1390 * is FPDMA non-zero offset enable which when enabled
1391 * only on the drive side leads to NCQ command
1392 * failures. Filter it out.
1395 .ident = "Aspire 3810T",
1397 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1398 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1400 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1404 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1405 unsigned int filter;
1411 filter = (unsigned long)dmi->driver_data;
1412 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1413 filter, dmi->ident);
1415 for (i = 0; i < host->n_ports; i++) {
1416 struct ata_port *ap = host->ports[i];
1417 struct ata_link *link;
1418 struct ata_device *dev;
1420 ata_for_each_link(link, ap, EDGE)
1421 ata_for_each_dev(dev, link, ALL)
1422 dev->gtf_filter |= filter;
1426 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1431 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1432 * as DUMMY, or detected but eventually get a "link down" and never get up
1433 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1434 * port_map may hold a value of 0x00.
1436 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1437 * and can significantly reduce the occurrence of the problem.
1439 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1441 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1442 struct pci_dev *pdev)
1444 static const struct dmi_system_id sysids[] = {
1446 .ident = "Acer Switch Alpha 12",
1448 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1449 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1455 if (dmi_check_system(sysids)) {
1456 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1457 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1458 hpriv->port_map = 0x7;
1459 hpriv->cap = 0xC734FF02;
1466 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1467 * Workaround is to make sure all pending IRQs are served before leaving
1470 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1472 struct ata_host *host = dev_instance;
1473 struct ahci_host_priv *hpriv;
1474 unsigned int rc = 0;
1476 u32 irq_stat, irq_masked;
1477 unsigned int handled = 1;
1480 hpriv = host->private_data;
1482 irq_stat = readl(mmio + HOST_IRQ_STAT);
1487 irq_masked = irq_stat & hpriv->port_map;
1488 spin_lock(&host->lock);
1489 rc = ahci_handle_port_intr(host, irq_masked);
1492 writel(irq_stat, mmio + HOST_IRQ_STAT);
1493 irq_stat = readl(mmio + HOST_IRQ_STAT);
1494 spin_unlock(&host->lock);
1498 return IRQ_RETVAL(handled);
1502 static int ahci_get_irq_vector(struct ata_host *host, int port)
1504 return pci_irq_vector(to_pci_dev(host->dev), port);
1507 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1508 struct ahci_host_priv *hpriv)
1512 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1516 * If number of MSIs is less than number of ports then Sharing Last
1517 * Message mode could be enforced. In this case assume that advantage
1518 * of multipe MSIs is negated and use single MSI mode instead.
1521 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1522 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1524 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1525 hpriv->get_irq_vector = ahci_get_irq_vector;
1526 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1531 * Fallback to single MSI mode if the controller
1532 * enforced MRSM mode.
1535 "ahci: MRSM is on, fallback to single MSI\n");
1536 pci_free_irq_vectors(pdev);
1541 * If the host is not capable of supporting per-port vectors, fall
1542 * back to single MSI before finally attempting single MSI-X.
1544 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1547 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1550 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1552 unsigned int board_id = ent->driver_data;
1553 struct ata_port_info pi = ahci_port_info[board_id];
1554 const struct ata_port_info *ppi[] = { &pi, NULL };
1555 struct device *dev = &pdev->dev;
1556 struct ahci_host_priv *hpriv;
1557 struct ata_host *host;
1559 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1563 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1565 ata_print_version_once(&pdev->dev, DRV_VERSION);
1567 /* The AHCI driver can only drive the SATA ports, the PATA driver
1568 can drive them all so if both drivers are selected make sure
1569 AHCI stays out of the way */
1570 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1573 /* Apple BIOS on MCP89 prevents us using AHCI */
1574 if (is_mcp89_apple(pdev))
1575 ahci_mcp89_apple_enable(pdev);
1577 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1578 * At the moment, we can only use the AHCI mode. Let the users know
1579 * that for SAS drives they're out of luck.
1581 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1582 dev_info(&pdev->dev,
1583 "PDC42819 can only drive SATA devices with this driver\n");
1585 /* Some devices use non-standard BARs */
1586 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1587 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1588 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1589 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1590 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1591 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1593 /* acquire resources */
1594 rc = pcim_enable_device(pdev);
1598 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1599 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1602 /* ICH6s share the same PCI ID for both piix and ahci
1603 * modes. Enabling ahci mode while MAP indicates
1604 * combined mode is a bad idea. Yield to ata_piix.
1606 pci_read_config_byte(pdev, ICH_MAP, &map);
1608 dev_info(&pdev->dev,
1609 "controller is in combined mode, can't enable AHCI mode\n");
1614 /* AHCI controllers often implement SFF compatible interface.
1615 * Grab all PCI BARs just in case.
1617 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1619 pcim_pin_device(pdev);
1623 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1626 hpriv->flags |= (unsigned long)pi.private_data;
1628 /* MCP65 revision A1 and A2 can't do MSI */
1629 if (board_id == board_ahci_mcp65 &&
1630 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1631 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1633 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1634 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1635 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1637 /* only some SB600s can do 64bit DMA */
1638 if (ahci_sb600_enable_64bit(pdev))
1639 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1641 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1643 /* must set flag prior to save config in order to take effect */
1644 if (ahci_broken_devslp(pdev))
1645 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1648 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1649 hpriv->irq_handler = ahci_thunderx_irq_handler;
1652 /* save initial config */
1653 ahci_pci_save_initial_config(pdev, hpriv);
1656 if (hpriv->cap & HOST_CAP_NCQ) {
1657 pi.flags |= ATA_FLAG_NCQ;
1659 * Auto-activate optimization is supposed to be
1660 * supported on all AHCI controllers indicating NCQ
1661 * capability, but it seems to be broken on some
1662 * chipsets including NVIDIAs.
1664 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1665 pi.flags |= ATA_FLAG_FPDMA_AA;
1668 * All AHCI controllers should be forward-compatible
1669 * with the new auxiliary field. This code should be
1670 * conditionalized if any buggy AHCI controllers are
1673 pi.flags |= ATA_FLAG_FPDMA_AUX;
1676 if (hpriv->cap & HOST_CAP_PMP)
1677 pi.flags |= ATA_FLAG_PMP;
1679 ahci_set_em_messages(hpriv, &pi);
1681 if (ahci_broken_system_poweroff(pdev)) {
1682 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1683 dev_info(&pdev->dev,
1684 "quirky BIOS, skipping spindown on poweroff\n");
1687 if (ahci_broken_lpm(pdev)) {
1688 pi.flags |= ATA_FLAG_NO_LPM;
1689 dev_warn(&pdev->dev,
1690 "BIOS update required for Link Power Management support\n");
1693 if (ahci_broken_suspend(pdev)) {
1694 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1695 dev_warn(&pdev->dev,
1696 "BIOS update required for suspend/resume\n");
1699 if (ahci_broken_online(pdev)) {
1700 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1701 dev_info(&pdev->dev,
1702 "online status unreliable, applying workaround\n");
1706 /* Acer SA5-271 workaround modifies private_data */
1707 acer_sa5_271_workaround(hpriv, pdev);
1709 /* CAP.NP sometimes indicate the index of the last enabled
1710 * port, at other times, that of the last possible port, so
1711 * determining the maximum port number requires looking at
1712 * both CAP.NP and port_map.
1714 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1716 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1719 host->private_data = hpriv;
1721 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1722 /* legacy intx interrupts */
1725 hpriv->irq = pci_irq_vector(pdev, 0);
1727 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1728 host->flags |= ATA_HOST_PARALLEL_SCAN;
1730 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1732 if (pi.flags & ATA_FLAG_EM)
1733 ahci_reset_em(host);
1735 for (i = 0; i < host->n_ports; i++) {
1736 struct ata_port *ap = host->ports[i];
1738 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1739 ata_port_pbar_desc(ap, ahci_pci_bar,
1740 0x100 + ap->port_no * 0x80, "port");
1742 /* set enclosure management message type */
1743 if (ap->flags & ATA_FLAG_EM)
1744 ap->em_message_type = hpriv->em_msg_type;
1747 /* disabled/not-implemented port */
1748 if (!(hpriv->port_map & (1 << i)))
1749 ap->ops = &ata_dummy_port_ops;
1752 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1753 ahci_p5wdh_workaround(host);
1755 /* apply gtf filter quirk */
1756 ahci_gtf_filter_workaround(host);
1758 /* initialize adapter */
1759 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1763 rc = ahci_pci_reset_controller(host);
1767 ahci_pci_init_controller(host);
1768 ahci_pci_print_info(host);
1770 pci_set_master(pdev);
1772 rc = ahci_host_activate(host, &ahci_sht);
1776 pm_runtime_put_noidle(&pdev->dev);
1780 static void ahci_shutdown_one(struct pci_dev *pdev)
1782 ata_pci_shutdown_one(pdev);
1785 static void ahci_remove_one(struct pci_dev *pdev)
1787 pm_runtime_get_noresume(&pdev->dev);
1788 ata_pci_remove_one(pdev);
1791 module_pci_driver(ahci_pci_driver);
1793 MODULE_AUTHOR("Jeff Garzik");
1794 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1795 MODULE_LICENSE("GPL");
1796 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1797 MODULE_VERSION(DRV_VERSION);