2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
62 /* board IDs by feature in alphabetical order */
70 /* board IDs for specific chipsets in alphabetical order */
77 board_ahci_sb700, /* for SB700 and SB800 */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
97 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
98 static int ahci_pci_device_resume(struct pci_dev *pdev);
101 static struct scsi_host_template ahci_sht = {
105 static struct ata_port_operations ahci_vt8251_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_vt8251_hardreset,
110 static struct ata_port_operations ahci_p5wdh_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_p5wdh_hardreset,
115 static struct ata_port_operations ahci_avn_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_avn_hardreset,
120 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
225 static const struct pci_device_id ahci_pci_tbl[] = {
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
271 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
272 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
288 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
289 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
290 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
291 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
292 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
293 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
294 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
295 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
296 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
297 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
298 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
299 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
300 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
301 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
302 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
303 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
304 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
305 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
307 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
308 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
309 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
310 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
311 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
313 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
318 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
319 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
320 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
321 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
322 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
323 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
328 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
329 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
338 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
339 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
340 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
341 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
342 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
344 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
348 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
349 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
352 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
353 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
354 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
355 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
356 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
357 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
358 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
359 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
360 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
361 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
363 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
364 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
365 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
366 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
367 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
368 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
369 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
370 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
371 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
372 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
373 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
374 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
375 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
376 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
379 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
380 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
386 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
387 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
388 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
389 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
391 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
392 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
393 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
394 /* JMicron 362B and 362C have an AHCI function with IDE class code */
395 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
396 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
397 /* May need to update quirk_jmicron_async_suspend() for additions */
400 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
401 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
403 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
405 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
409 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
410 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
411 /* AMD is using RAID class only for ahci controllers */
412 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
413 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
416 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
417 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
420 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
507 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
508 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
510 /* ST Microelectronics */
511 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
514 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
515 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
516 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
517 .class = PCI_CLASS_STORAGE_SATA_AHCI,
518 .class_mask = 0xffffff,
519 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
521 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
522 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
523 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
524 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
525 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
526 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
532 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
534 .driver_data = board_ahci_yes_fbs },
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
536 .driver_data = board_ahci_yes_fbs },
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
540 .driver_data = board_ahci_yes_fbs },
541 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
542 .driver_data = board_ahci_yes_fbs },
543 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
544 .driver_data = board_ahci_yes_fbs },
547 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
548 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
551 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
552 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
553 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
554 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
557 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
558 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
560 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
561 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
564 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
566 /* Generic, PCI class code for AHCI */
567 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
568 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
570 { } /* terminate list */
574 static struct pci_driver ahci_pci_driver = {
576 .id_table = ahci_pci_tbl,
577 .probe = ahci_init_one,
578 .remove = ata_pci_remove_one,
580 .suspend = ahci_pci_device_suspend,
581 .resume = ahci_pci_device_resume,
585 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
586 static int marvell_enable;
588 static int marvell_enable = 1;
590 module_param(marvell_enable, int, 0644);
591 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
594 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
595 struct ahci_host_priv *hpriv)
597 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
598 dev_info(&pdev->dev, "JMB361 has only one port\n");
599 hpriv->force_port_map = 1;
603 * Temporary Marvell 6145 hack: PATA port presence
604 * is asserted through the standard AHCI port
605 * presence register, as bit 4 (counting from 0)
607 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
608 if (pdev->device == 0x6121)
609 hpriv->mask_port_map = 0x3;
611 hpriv->mask_port_map = 0xf;
613 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
616 ahci_save_initial_config(&pdev->dev, hpriv);
619 static int ahci_pci_reset_controller(struct ata_host *host)
621 struct pci_dev *pdev = to_pci_dev(host->dev);
624 rc = ahci_reset_controller(host);
628 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
629 struct ahci_host_priv *hpriv = host->private_data;
633 pci_read_config_word(pdev, 0x92, &tmp16);
634 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
635 tmp16 |= hpriv->port_map;
636 pci_write_config_word(pdev, 0x92, tmp16);
643 static void ahci_pci_init_controller(struct ata_host *host)
645 struct ahci_host_priv *hpriv = host->private_data;
646 struct pci_dev *pdev = to_pci_dev(host->dev);
647 void __iomem *port_mmio;
651 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
652 if (pdev->device == 0x6121)
656 port_mmio = __ahci_port_base(host, mv);
658 writel(0, port_mmio + PORT_IRQ_MASK);
661 tmp = readl(port_mmio + PORT_IRQ_STAT);
662 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
664 writel(tmp, port_mmio + PORT_IRQ_STAT);
667 ahci_init_controller(host);
670 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
671 unsigned long deadline)
673 struct ata_port *ap = link->ap;
674 struct ahci_host_priv *hpriv = ap->host->private_data;
680 ahci_stop_engine(ap);
682 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
683 deadline, &online, NULL);
685 hpriv->start_engine(ap);
687 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
689 /* vt8251 doesn't clear BSY on signature FIS reception,
690 * request follow-up softreset.
692 return online ? -EAGAIN : rc;
695 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
696 unsigned long deadline)
698 struct ata_port *ap = link->ap;
699 struct ahci_port_priv *pp = ap->private_data;
700 struct ahci_host_priv *hpriv = ap->host->private_data;
701 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
702 struct ata_taskfile tf;
706 ahci_stop_engine(ap);
708 /* clear D2H reception area to properly wait for D2H FIS */
709 ata_tf_init(link->device, &tf);
710 tf.command = ATA_BUSY;
711 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
713 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
714 deadline, &online, NULL);
716 hpriv->start_engine(ap);
718 /* The pseudo configuration device on SIMG4726 attached to
719 * ASUS P5W-DH Deluxe doesn't send signature FIS after
720 * hardreset if no device is attached to the first downstream
721 * port && the pseudo device locks up on SRST w/ PMP==0. To
722 * work around this, wait for !BSY only briefly. If BSY isn't
723 * cleared, perform CLO and proceed to IDENTIFY (achieved by
724 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
726 * Wait for two seconds. Devices attached to downstream port
727 * which can't process the following IDENTIFY after this will
728 * have to be reset again. For most cases, this should
729 * suffice while making probing snappish enough.
732 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
735 ahci_kick_engine(ap);
741 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
743 * It has been observed with some SSDs that the timing of events in the
744 * link synchronization phase can leave the port in a state that can not
745 * be recovered by a SATA-hard-reset alone. The failing signature is
746 * SStatus.DET stuck at 1 ("Device presence detected but Phy
747 * communication not established"). It was found that unloading and
748 * reloading the driver when this problem occurs allows the drive
749 * connection to be recovered (DET advanced to 0x3). The critical
750 * component of reloading the driver is that the port state machines are
751 * reset by bouncing "port enable" in the AHCI PCS configuration
752 * register. So, reproduce that effect by bouncing a port whenever we
753 * see DET==1 after a reset.
755 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
756 unsigned long deadline)
758 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
759 struct ata_port *ap = link->ap;
760 struct ahci_port_priv *pp = ap->private_data;
761 struct ahci_host_priv *hpriv = ap->host->private_data;
762 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
763 unsigned long tmo = deadline - jiffies;
764 struct ata_taskfile tf;
770 ahci_stop_engine(ap);
772 for (i = 0; i < 2; i++) {
775 int port = ap->port_no;
776 struct ata_host *host = ap->host;
777 struct pci_dev *pdev = to_pci_dev(host->dev);
779 /* clear D2H reception area to properly wait for D2H FIS */
780 ata_tf_init(link->device, &tf);
781 tf.command = ATA_BUSY;
782 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
784 rc = sata_link_hardreset(link, timing, deadline, &online,
787 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
788 (sstatus & 0xf) != 1)
791 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
794 pci_read_config_word(pdev, 0x92, &val);
796 pci_write_config_word(pdev, 0x92, val);
797 ata_msleep(ap, 1000);
799 pci_write_config_word(pdev, 0x92, val);
803 hpriv->start_engine(ap);
806 *class = ahci_dev_classify(ap);
808 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
814 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
816 struct ata_host *host = pci_get_drvdata(pdev);
817 struct ahci_host_priv *hpriv = host->private_data;
818 void __iomem *mmio = hpriv->mmio;
821 if (mesg.event & PM_EVENT_SUSPEND &&
822 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
824 "BIOS update required for suspend/resume\n");
828 if (mesg.event & PM_EVENT_SLEEP) {
829 /* AHCI spec rev1.1 section 8.3.3:
830 * Software must disable interrupts prior to requesting a
831 * transition of the HBA to D3 state.
833 ctl = readl(mmio + HOST_CTL);
835 writel(ctl, mmio + HOST_CTL);
836 readl(mmio + HOST_CTL); /* flush */
839 return ata_pci_device_suspend(pdev, mesg);
842 static int ahci_pci_device_resume(struct pci_dev *pdev)
844 struct ata_host *host = pci_get_drvdata(pdev);
847 rc = ata_pci_device_do_resume(pdev);
851 /* Apple BIOS helpfully mangles the registers on resume */
852 if (is_mcp89_apple(pdev))
853 ahci_mcp89_apple_enable(pdev);
855 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
856 rc = ahci_pci_reset_controller(host);
860 ahci_pci_init_controller(host);
863 ata_host_resume(host);
869 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
874 * If the device fixup already set the dma_mask to some non-standard
875 * value, don't extend it here. This happens on STA2X11, for example.
877 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
881 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
882 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
884 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
887 "64-bit DMA enable failed\n");
892 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
894 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
897 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
900 "32-bit consistent DMA enable failed\n");
907 static void ahci_pci_print_info(struct ata_host *host)
909 struct pci_dev *pdev = to_pci_dev(host->dev);
913 pci_read_config_word(pdev, 0x0a, &cc);
914 if (cc == PCI_CLASS_STORAGE_IDE)
916 else if (cc == PCI_CLASS_STORAGE_SATA)
918 else if (cc == PCI_CLASS_STORAGE_RAID)
923 ahci_print_info(host, scc_s);
926 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
927 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
928 * support PMP and the 4726 either directly exports the device
929 * attached to the first downstream port or acts as a hardware storage
930 * controller and emulate a single ATA device (can be RAID 0/1 or some
931 * other configuration).
933 * When there's no device attached to the first downstream port of the
934 * 4726, "Config Disk" appears, which is a pseudo ATA device to
935 * configure the 4726. However, ATA emulation of the device is very
936 * lame. It doesn't send signature D2H Reg FIS after the initial
937 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
939 * The following function works around the problem by always using
940 * hardreset on the port and not depending on receiving signature FIS
941 * afterward. If signature FIS isn't received soon, ATA class is
942 * assumed without follow-up softreset.
944 static void ahci_p5wdh_workaround(struct ata_host *host)
946 static const struct dmi_system_id sysids[] = {
948 .ident = "P5W DH Deluxe",
950 DMI_MATCH(DMI_SYS_VENDOR,
951 "ASUSTEK COMPUTER INC"),
952 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
957 struct pci_dev *pdev = to_pci_dev(host->dev);
959 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
960 dmi_check_system(sysids)) {
961 struct ata_port *ap = host->ports[1];
964 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
966 ap->ops = &ahci_p5wdh_ops;
967 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
972 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
973 * booting in BIOS compatibility mode. We restore the registers but not ID.
975 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
979 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
981 pci_read_config_dword(pdev, 0xf8, &val);
983 /* the following changes the device ID, but appears not to affect function */
984 /* val = (val & ~0xf0000000) | 0x80000000; */
985 pci_write_config_dword(pdev, 0xf8, val);
987 pci_read_config_dword(pdev, 0x54c, &val);
989 pci_write_config_dword(pdev, 0x54c, val);
991 pci_read_config_dword(pdev, 0x4a4, &val);
994 pci_write_config_dword(pdev, 0x4a4, val);
996 pci_read_config_dword(pdev, 0x54c, &val);
998 pci_write_config_dword(pdev, 0x54c, val);
1000 pci_read_config_dword(pdev, 0xf8, &val);
1001 val &= ~(1 << 0x1b);
1002 pci_write_config_dword(pdev, 0xf8, val);
1005 static bool is_mcp89_apple(struct pci_dev *pdev)
1007 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1008 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1009 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1010 pdev->subsystem_device == 0xcb89;
1013 /* only some SB600 ahci controllers can do 64bit DMA */
1014 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1016 static const struct dmi_system_id sysids[] = {
1018 * The oldest version known to be broken is 0901 and
1019 * working is 1501 which was released on 2007-10-26.
1020 * Enable 64bit DMA on 1501 and anything newer.
1022 * Please read bko#9412 for more info.
1025 .ident = "ASUS M2A-VM",
1027 DMI_MATCH(DMI_BOARD_VENDOR,
1028 "ASUSTeK Computer INC."),
1029 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1031 .driver_data = "20071026", /* yyyymmdd */
1034 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1035 * support 64bit DMA.
1037 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1038 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1039 * This spelling mistake was fixed in BIOS version 1.5, so
1040 * 1.5 and later have the Manufacturer as
1041 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1042 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1044 * BIOS versions earlier than 1.9 had a Board Product Name
1045 * DMI field of "MS-7376". This was changed to be
1046 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1047 * match on DMI_BOARD_NAME of "MS-7376".
1050 .ident = "MSI K9A2 Platinum",
1052 DMI_MATCH(DMI_BOARD_VENDOR,
1053 "MICRO-STAR INTER"),
1054 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1058 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1061 * This board also had the typo mentioned above in the
1062 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1063 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1066 .ident = "MSI K9AGM2",
1068 DMI_MATCH(DMI_BOARD_VENDOR,
1069 "MICRO-STAR INTER"),
1070 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1074 * All BIOS versions for the Asus M3A support 64bit DMA.
1075 * (all release versions from 0301 to 1206 were tested)
1078 .ident = "ASUS M3A",
1080 DMI_MATCH(DMI_BOARD_VENDOR,
1081 "ASUSTeK Computer INC."),
1082 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1087 const struct dmi_system_id *match;
1088 int year, month, date;
1091 match = dmi_first_match(sysids);
1092 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1096 if (!match->driver_data)
1099 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1100 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1102 if (strcmp(buf, match->driver_data) >= 0)
1105 dev_warn(&pdev->dev,
1106 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1112 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1116 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1118 static const struct dmi_system_id broken_systems[] = {
1120 .ident = "HP Compaq nx6310",
1122 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1123 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1125 /* PCI slot number of the controller */
1126 .driver_data = (void *)0x1FUL,
1129 .ident = "HP Compaq 6720s",
1131 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1132 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1134 /* PCI slot number of the controller */
1135 .driver_data = (void *)0x1FUL,
1138 { } /* terminate list */
1140 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1143 unsigned long slot = (unsigned long)dmi->driver_data;
1144 /* apply the quirk only to on-board controllers */
1145 return slot == PCI_SLOT(pdev->devfn);
1151 static bool ahci_broken_suspend(struct pci_dev *pdev)
1153 static const struct dmi_system_id sysids[] = {
1155 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1156 * to the harddisk doesn't become online after
1157 * resuming from STR. Warn and fail suspend.
1159 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1161 * Use dates instead of versions to match as HP is
1162 * apparently recycling both product and version
1165 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1170 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1171 DMI_MATCH(DMI_PRODUCT_NAME,
1172 "HP Pavilion dv4 Notebook PC"),
1174 .driver_data = "20090105", /* F.30 */
1179 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1180 DMI_MATCH(DMI_PRODUCT_NAME,
1181 "HP Pavilion dv5 Notebook PC"),
1183 .driver_data = "20090506", /* F.16 */
1188 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1189 DMI_MATCH(DMI_PRODUCT_NAME,
1190 "HP Pavilion dv6 Notebook PC"),
1192 .driver_data = "20090423", /* F.21 */
1197 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1198 DMI_MATCH(DMI_PRODUCT_NAME,
1199 "HP HDX18 Notebook PC"),
1201 .driver_data = "20090430", /* F.23 */
1204 * Acer eMachines G725 has the same problem. BIOS
1205 * V1.03 is known to be broken. V3.04 is known to
1206 * work. Between, there are V1.06, V2.06 and V3.03
1207 * that we don't have much idea about. For now,
1208 * blacklist anything older than V3.04.
1210 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1215 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1216 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1218 .driver_data = "20091216", /* V3.04 */
1220 { } /* terminate list */
1222 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1223 int year, month, date;
1226 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1229 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1230 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1232 return strcmp(buf, dmi->driver_data) < 0;
1235 static bool ahci_broken_lpm(struct pci_dev *pdev)
1237 static const struct dmi_system_id sysids[] = {
1238 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1241 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1242 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1244 .driver_data = "20180406", /* 1.31 */
1248 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1249 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1251 .driver_data = "20180420", /* 1.28 */
1255 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1256 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1258 .driver_data = "20180315", /* 1.33 */
1262 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1263 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1266 * Note date based on release notes, 2.35 has been
1267 * reported to be good, but I've been unable to get
1268 * a hold of the reporter to get the DMI BIOS date.
1271 .driver_data = "20180310", /* 2.35 */
1273 { } /* terminate list */
1275 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1276 int year, month, date;
1282 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1283 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1285 return strcmp(buf, dmi->driver_data) < 0;
1288 static bool ahci_broken_online(struct pci_dev *pdev)
1290 #define ENCODE_BUSDEVFN(bus, slot, func) \
1291 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1292 static const struct dmi_system_id sysids[] = {
1294 * There are several gigabyte boards which use
1295 * SIMG5723s configured as hardware RAID. Certain
1296 * 5723 firmware revisions shipped there keep the link
1297 * online but fail to answer properly to SRST or
1298 * IDENTIFY when no device is attached downstream
1299 * causing libata to retry quite a few times leading
1300 * to excessive detection delay.
1302 * As these firmwares respond to the second reset try
1303 * with invalid device signature, considering unknown
1304 * sig as offline works around the problem acceptably.
1307 .ident = "EP45-DQ6",
1309 DMI_MATCH(DMI_BOARD_VENDOR,
1310 "Gigabyte Technology Co., Ltd."),
1311 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1313 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1316 .ident = "EP45-DS5",
1318 DMI_MATCH(DMI_BOARD_VENDOR,
1319 "Gigabyte Technology Co., Ltd."),
1320 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1322 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1324 { } /* terminate list */
1326 #undef ENCODE_BUSDEVFN
1327 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1333 val = (unsigned long)dmi->driver_data;
1335 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1338 static bool ahci_broken_devslp(struct pci_dev *pdev)
1340 /* device with broken DEVSLP but still showing SDS capability */
1341 static const struct pci_device_id ids[] = {
1342 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1346 return pci_match_id(ids, pdev);
1349 #ifdef CONFIG_ATA_ACPI
1350 static void ahci_gtf_filter_workaround(struct ata_host *host)
1352 static const struct dmi_system_id sysids[] = {
1354 * Aspire 3810T issues a bunch of SATA enable commands
1355 * via _GTF including an invalid one and one which is
1356 * rejected by the device. Among the successful ones
1357 * is FPDMA non-zero offset enable which when enabled
1358 * only on the drive side leads to NCQ command
1359 * failures. Filter it out.
1362 .ident = "Aspire 3810T",
1364 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1365 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1367 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1371 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1372 unsigned int filter;
1378 filter = (unsigned long)dmi->driver_data;
1379 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1380 filter, dmi->ident);
1382 for (i = 0; i < host->n_ports; i++) {
1383 struct ata_port *ap = host->ports[i];
1384 struct ata_link *link;
1385 struct ata_device *dev;
1387 ata_for_each_link(link, ap, EDGE)
1388 ata_for_each_dev(dev, link, ALL)
1389 dev->gtf_filter |= filter;
1393 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1398 * ahci_init_msix() only implements single MSI-X support, not multiple
1399 * MSI-X per-port interrupts. This is needed for host controllers that only
1400 * have MSI-X support implemented, but no MSI or intx.
1402 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1403 struct ahci_host_priv *hpriv)
1406 struct msix_entry entry = {};
1408 /* Do not init MSI-X if MSI is disabled for the device */
1409 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1412 nvec = pci_msix_vec_count(pdev);
1422 * There can be more than one vector (e.g. for error detection or
1423 * hdd hotplug). Only the first vector (entry.entry = 0) is used.
1425 rc = pci_enable_msix_exact(pdev, &entry, 1);
1429 hpriv->irq = entry.vector;
1434 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1440 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1441 struct ahci_host_priv *hpriv)
1445 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1448 nvec = pci_msi_vec_count(pdev);
1453 * If number of MSIs is less than number of ports then Sharing Last
1454 * Message mode could be enforced. In this case assume that advantage
1455 * of multipe MSIs is negated and use single MSI mode instead.
1460 rc = pci_enable_msi_exact(pdev, nvec);
1466 /* fallback to single MSI mode if the controller enforced MRSM mode */
1467 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1468 pci_disable_msi(pdev);
1469 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1474 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1481 rc = pci_enable_msi(pdev);
1485 hpriv->irq = pdev->irq;
1490 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1491 struct ahci_host_priv *hpriv)
1495 nvec = ahci_init_msi(pdev, n_ports, hpriv);
1500 * Currently, MSI-X support only implements single IRQ mode and
1501 * exists for controllers which can't do other types of IRQ. Only
1502 * set it up if MSI fails.
1504 nvec = ahci_init_msix(pdev, n_ports, hpriv);
1508 /* lagacy intx interrupts */
1510 hpriv->irq = pdev->irq;
1515 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1517 unsigned int board_id = ent->driver_data;
1518 struct ata_port_info pi = ahci_port_info[board_id];
1519 const struct ata_port_info *ppi[] = { &pi, NULL };
1520 struct device *dev = &pdev->dev;
1521 struct ahci_host_priv *hpriv;
1522 struct ata_host *host;
1524 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1528 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1530 ata_print_version_once(&pdev->dev, DRV_VERSION);
1532 /* The AHCI driver can only drive the SATA ports, the PATA driver
1533 can drive them all so if both drivers are selected make sure
1534 AHCI stays out of the way */
1535 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1538 /* Apple BIOS on MCP89 prevents us using AHCI */
1539 if (is_mcp89_apple(pdev))
1540 ahci_mcp89_apple_enable(pdev);
1542 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1543 * At the moment, we can only use the AHCI mode. Let the users know
1544 * that for SAS drives they're out of luck.
1546 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1547 dev_info(&pdev->dev,
1548 "PDC42819 can only drive SATA devices with this driver\n");
1550 /* Some devices use non-standard BARs */
1551 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1552 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1553 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1554 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1555 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1556 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1558 /* acquire resources */
1559 rc = pcim_enable_device(pdev);
1563 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1564 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1567 /* ICH6s share the same PCI ID for both piix and ahci
1568 * modes. Enabling ahci mode while MAP indicates
1569 * combined mode is a bad idea. Yield to ata_piix.
1571 pci_read_config_byte(pdev, ICH_MAP, &map);
1573 dev_info(&pdev->dev,
1574 "controller is in combined mode, can't enable AHCI mode\n");
1579 /* AHCI controllers often implement SFF compatible interface.
1580 * Grab all PCI BARs just in case.
1582 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1584 pcim_pin_device(pdev);
1588 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1591 hpriv->flags |= (unsigned long)pi.private_data;
1593 /* MCP65 revision A1 and A2 can't do MSI */
1594 if (board_id == board_ahci_mcp65 &&
1595 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1596 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1598 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1599 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1600 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1602 /* only some SB600s can do 64bit DMA */
1603 if (ahci_sb600_enable_64bit(pdev))
1604 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1606 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1608 /* must set flag prior to save config in order to take effect */
1609 if (ahci_broken_devslp(pdev))
1610 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1612 /* save initial config */
1613 ahci_pci_save_initial_config(pdev, hpriv);
1616 if (hpriv->cap & HOST_CAP_NCQ) {
1617 pi.flags |= ATA_FLAG_NCQ;
1619 * Auto-activate optimization is supposed to be
1620 * supported on all AHCI controllers indicating NCQ
1621 * capability, but it seems to be broken on some
1622 * chipsets including NVIDIAs.
1624 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1625 pi.flags |= ATA_FLAG_FPDMA_AA;
1628 * All AHCI controllers should be forward-compatible
1629 * with the new auxiliary field. This code should be
1630 * conditionalized if any buggy AHCI controllers are
1633 pi.flags |= ATA_FLAG_FPDMA_AUX;
1636 if (hpriv->cap & HOST_CAP_PMP)
1637 pi.flags |= ATA_FLAG_PMP;
1639 ahci_set_em_messages(hpriv, &pi);
1641 if (ahci_broken_system_poweroff(pdev)) {
1642 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1643 dev_info(&pdev->dev,
1644 "quirky BIOS, skipping spindown on poweroff\n");
1647 if (ahci_broken_lpm(pdev)) {
1648 pi.flags |= ATA_FLAG_NO_LPM;
1649 dev_warn(&pdev->dev,
1650 "BIOS update required for Link Power Management support\n");
1653 if (ahci_broken_suspend(pdev)) {
1654 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1655 dev_warn(&pdev->dev,
1656 "BIOS update required for suspend/resume\n");
1659 if (ahci_broken_online(pdev)) {
1660 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1661 dev_info(&pdev->dev,
1662 "online status unreliable, applying workaround\n");
1665 /* CAP.NP sometimes indicate the index of the last enabled
1666 * port, at other times, that of the last possible port, so
1667 * determining the maximum port number requires looking at
1668 * both CAP.NP and port_map.
1670 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1672 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1675 host->private_data = hpriv;
1677 ahci_init_interrupts(pdev, n_ports, hpriv);
1679 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1680 host->flags |= ATA_HOST_PARALLEL_SCAN;
1682 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1684 if (pi.flags & ATA_FLAG_EM)
1685 ahci_reset_em(host);
1687 for (i = 0; i < host->n_ports; i++) {
1688 struct ata_port *ap = host->ports[i];
1690 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1691 ata_port_pbar_desc(ap, ahci_pci_bar,
1692 0x100 + ap->port_no * 0x80, "port");
1694 /* set enclosure management message type */
1695 if (ap->flags & ATA_FLAG_EM)
1696 ap->em_message_type = hpriv->em_msg_type;
1699 /* disabled/not-implemented port */
1700 if (!(hpriv->port_map & (1 << i)))
1701 ap->ops = &ata_dummy_port_ops;
1704 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1705 ahci_p5wdh_workaround(host);
1707 /* apply gtf filter quirk */
1708 ahci_gtf_filter_workaround(host);
1710 /* initialize adapter */
1711 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1715 rc = ahci_pci_reset_controller(host);
1719 ahci_pci_init_controller(host);
1720 ahci_pci_print_info(host);
1722 pci_set_master(pdev);
1724 return ahci_host_activate(host, &ahci_sht);
1727 module_pci_driver(ahci_pci_driver);
1729 MODULE_AUTHOR("Jeff Garzik");
1730 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1731 MODULE_LICENSE("GPL");
1732 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1733 MODULE_VERSION(DRV_VERSION);