2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_STANDARD = 5,
64 /* board IDs by feature in alphabetical order */
72 /* board IDs for specific chipsets in alphabetical order */
79 board_ahci_sb700, /* for SB700 and SB800 */
83 board_ahci_mcp_linux = board_ahci_mcp65,
84 board_ahci_mcp67 = board_ahci_mcp65,
85 board_ahci_mcp73 = board_ahci_mcp65,
86 board_ahci_mcp79 = board_ahci_mcp77,
89 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
90 static void ahci_remove_one(struct pci_dev *dev);
91 static void ahci_shutdown_one(struct pci_dev *dev);
92 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
97 static bool is_mcp89_apple(struct pci_dev *pdev);
98 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
99 unsigned long deadline);
101 static int ahci_pci_device_runtime_suspend(struct device *dev);
102 static int ahci_pci_device_runtime_resume(struct device *dev);
103 #ifdef CONFIG_PM_SLEEP
104 static int ahci_pci_device_suspend(struct device *dev);
105 static int ahci_pci_device_resume(struct device *dev);
107 #endif /* CONFIG_PM */
109 static struct scsi_host_template ahci_sht = {
113 static struct ata_port_operations ahci_vt8251_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_vt8251_hardreset,
118 static struct ata_port_operations ahci_p5wdh_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_p5wdh_hardreset,
123 static struct ata_port_operations ahci_avn_ops = {
124 .inherits = &ahci_ops,
125 .hardreset = ahci_avn_hardreset,
128 static const struct ata_port_info ahci_port_info[] = {
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_ign_iferr] = {
137 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_nomsi] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_noncq] = {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
157 [board_ahci_nosntf] = {
158 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
159 .flags = AHCI_FLAG_COMMON,
160 .pio_mask = ATA_PIO4,
161 .udma_mask = ATA_UDMA6,
162 .port_ops = &ahci_ops,
164 [board_ahci_yes_fbs] = {
165 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
166 .flags = AHCI_FLAG_COMMON,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_avn_ops,
178 [board_ahci_mcp65] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
181 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
186 [board_ahci_mcp77] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
193 [board_ahci_mcp89] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
202 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
203 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
208 [board_ahci_sb600] = {
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = { /* for SB700 and SB800 */
218 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_pmp_retry_srst_ops,
224 [board_ahci_vt8251] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
226 .flags = AHCI_FLAG_COMMON,
227 .pio_mask = ATA_PIO4,
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &ahci_vt8251_ops,
233 static const struct pci_device_id ahci_pci_tbl[] = {
235 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
236 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
237 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
238 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
239 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
240 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
241 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
245 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
246 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
247 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
250 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
261 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
263 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
264 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
265 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
266 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
268 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
269 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
270 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
271 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
272 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
274 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
296 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
297 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
298 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
299 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
301 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
302 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
303 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
304 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
305 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
308 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
312 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
313 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
314 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
315 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
317 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
319 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
321 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
323 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
339 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
348 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
352 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
356 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
357 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
360 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
361 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
362 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
364 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
366 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
367 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
368 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
369 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
370 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
371 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
372 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
373 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
374 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
375 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
376 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
377 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
379 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
382 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
386 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
389 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
390 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
391 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
392 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
393 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
395 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
396 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
397 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
398 /* JMicron 362B and 362C have an AHCI function with IDE class code */
399 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
400 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
401 /* May need to update quirk_jmicron_async_suspend() for additions */
404 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
405 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
409 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
410 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
413 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
414 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
415 /* AMD is using RAID class only for ahci controllers */
416 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
417 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
420 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
421 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
424 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
510 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
511 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
512 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
514 /* ST Microelectronics */
515 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
518 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
519 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
521 .class = PCI_CLASS_STORAGE_SATA_AHCI,
522 .class_mask = 0xffffff,
523 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
525 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
526 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
527 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
532 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
534 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
536 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
540 .driver_data = board_ahci_yes_fbs },
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
542 .driver_data = board_ahci_yes_fbs },
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
544 .driver_data = board_ahci_yes_fbs },
545 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
546 .driver_data = board_ahci_yes_fbs },
547 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
548 .driver_data = board_ahci_yes_fbs },
551 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
552 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
555 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
556 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
557 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
558 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
559 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
560 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
563 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
564 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
566 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
567 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
570 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
572 /* Generic, PCI class code for AHCI */
573 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
574 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
576 { } /* terminate list */
579 static const struct dev_pm_ops ahci_pci_pm_ops = {
580 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
581 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
582 ahci_pci_device_runtime_resume, NULL)
585 static struct pci_driver ahci_pci_driver = {
587 .id_table = ahci_pci_tbl,
588 .probe = ahci_init_one,
589 .remove = ahci_remove_one,
590 .shutdown = ahci_shutdown_one,
592 .pm = &ahci_pci_pm_ops,
596 #if IS_ENABLED(CONFIG_PATA_MARVELL)
597 static int marvell_enable;
599 static int marvell_enable = 1;
601 module_param(marvell_enable, int, 0644);
602 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
605 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
606 struct ahci_host_priv *hpriv)
608 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
609 dev_info(&pdev->dev, "JMB361 has only one port\n");
610 hpriv->force_port_map = 1;
614 * Temporary Marvell 6145 hack: PATA port presence
615 * is asserted through the standard AHCI port
616 * presence register, as bit 4 (counting from 0)
618 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
619 if (pdev->device == 0x6121)
620 hpriv->mask_port_map = 0x3;
622 hpriv->mask_port_map = 0xf;
624 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
627 ahci_save_initial_config(&pdev->dev, hpriv);
630 static int ahci_pci_reset_controller(struct ata_host *host)
632 struct pci_dev *pdev = to_pci_dev(host->dev);
635 rc = ahci_reset_controller(host);
639 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
640 struct ahci_host_priv *hpriv = host->private_data;
644 pci_read_config_word(pdev, 0x92, &tmp16);
645 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
646 tmp16 |= hpriv->port_map;
647 pci_write_config_word(pdev, 0x92, tmp16);
654 static void ahci_pci_init_controller(struct ata_host *host)
656 struct ahci_host_priv *hpriv = host->private_data;
657 struct pci_dev *pdev = to_pci_dev(host->dev);
658 void __iomem *port_mmio;
662 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
663 if (pdev->device == 0x6121)
667 port_mmio = __ahci_port_base(host, mv);
669 writel(0, port_mmio + PORT_IRQ_MASK);
672 tmp = readl(port_mmio + PORT_IRQ_STAT);
673 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
675 writel(tmp, port_mmio + PORT_IRQ_STAT);
678 ahci_init_controller(host);
681 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
682 unsigned long deadline)
684 struct ata_port *ap = link->ap;
685 struct ahci_host_priv *hpriv = ap->host->private_data;
691 hpriv->stop_engine(ap);
693 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
694 deadline, &online, NULL);
696 hpriv->start_engine(ap);
698 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
700 /* vt8251 doesn't clear BSY on signature FIS reception,
701 * request follow-up softreset.
703 return online ? -EAGAIN : rc;
706 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
707 unsigned long deadline)
709 struct ata_port *ap = link->ap;
710 struct ahci_port_priv *pp = ap->private_data;
711 struct ahci_host_priv *hpriv = ap->host->private_data;
712 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
713 struct ata_taskfile tf;
717 hpriv->stop_engine(ap);
719 /* clear D2H reception area to properly wait for D2H FIS */
720 ata_tf_init(link->device, &tf);
721 tf.command = ATA_BUSY;
722 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
724 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
725 deadline, &online, NULL);
727 hpriv->start_engine(ap);
729 /* The pseudo configuration device on SIMG4726 attached to
730 * ASUS P5W-DH Deluxe doesn't send signature FIS after
731 * hardreset if no device is attached to the first downstream
732 * port && the pseudo device locks up on SRST w/ PMP==0. To
733 * work around this, wait for !BSY only briefly. If BSY isn't
734 * cleared, perform CLO and proceed to IDENTIFY (achieved by
735 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
737 * Wait for two seconds. Devices attached to downstream port
738 * which can't process the following IDENTIFY after this will
739 * have to be reset again. For most cases, this should
740 * suffice while making probing snappish enough.
743 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
746 ahci_kick_engine(ap);
752 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
754 * It has been observed with some SSDs that the timing of events in the
755 * link synchronization phase can leave the port in a state that can not
756 * be recovered by a SATA-hard-reset alone. The failing signature is
757 * SStatus.DET stuck at 1 ("Device presence detected but Phy
758 * communication not established"). It was found that unloading and
759 * reloading the driver when this problem occurs allows the drive
760 * connection to be recovered (DET advanced to 0x3). The critical
761 * component of reloading the driver is that the port state machines are
762 * reset by bouncing "port enable" in the AHCI PCS configuration
763 * register. So, reproduce that effect by bouncing a port whenever we
764 * see DET==1 after a reset.
766 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
767 unsigned long deadline)
769 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
770 struct ata_port *ap = link->ap;
771 struct ahci_port_priv *pp = ap->private_data;
772 struct ahci_host_priv *hpriv = ap->host->private_data;
773 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
774 unsigned long tmo = deadline - jiffies;
775 struct ata_taskfile tf;
781 hpriv->stop_engine(ap);
783 for (i = 0; i < 2; i++) {
786 int port = ap->port_no;
787 struct ata_host *host = ap->host;
788 struct pci_dev *pdev = to_pci_dev(host->dev);
790 /* clear D2H reception area to properly wait for D2H FIS */
791 ata_tf_init(link->device, &tf);
792 tf.command = ATA_BUSY;
793 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
795 rc = sata_link_hardreset(link, timing, deadline, &online,
798 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
799 (sstatus & 0xf) != 1)
802 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
805 pci_read_config_word(pdev, 0x92, &val);
807 pci_write_config_word(pdev, 0x92, val);
808 ata_msleep(ap, 1000);
810 pci_write_config_word(pdev, 0x92, val);
814 hpriv->start_engine(ap);
817 *class = ahci_dev_classify(ap);
819 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
825 static void ahci_pci_disable_interrupts(struct ata_host *host)
827 struct ahci_host_priv *hpriv = host->private_data;
828 void __iomem *mmio = hpriv->mmio;
831 /* AHCI spec rev1.1 section 8.3.3:
832 * Software must disable interrupts prior to requesting a
833 * transition of the HBA to D3 state.
835 ctl = readl(mmio + HOST_CTL);
837 writel(ctl, mmio + HOST_CTL);
838 readl(mmio + HOST_CTL); /* flush */
841 static int ahci_pci_device_runtime_suspend(struct device *dev)
843 struct pci_dev *pdev = to_pci_dev(dev);
844 struct ata_host *host = pci_get_drvdata(pdev);
846 ahci_pci_disable_interrupts(host);
850 static int ahci_pci_device_runtime_resume(struct device *dev)
852 struct pci_dev *pdev = to_pci_dev(dev);
853 struct ata_host *host = pci_get_drvdata(pdev);
856 rc = ahci_pci_reset_controller(host);
859 ahci_pci_init_controller(host);
863 #ifdef CONFIG_PM_SLEEP
864 static int ahci_pci_device_suspend(struct device *dev)
866 struct pci_dev *pdev = to_pci_dev(dev);
867 struct ata_host *host = pci_get_drvdata(pdev);
868 struct ahci_host_priv *hpriv = host->private_data;
870 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
872 "BIOS update required for suspend/resume\n");
876 ahci_pci_disable_interrupts(host);
877 return ata_host_suspend(host, PMSG_SUSPEND);
880 static int ahci_pci_device_resume(struct device *dev)
882 struct pci_dev *pdev = to_pci_dev(dev);
883 struct ata_host *host = pci_get_drvdata(pdev);
886 /* Apple BIOS helpfully mangles the registers on resume */
887 if (is_mcp89_apple(pdev))
888 ahci_mcp89_apple_enable(pdev);
890 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
891 rc = ahci_pci_reset_controller(host);
895 ahci_pci_init_controller(host);
898 ata_host_resume(host);
904 #endif /* CONFIG_PM */
906 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
911 * If the device fixup already set the dma_mask to some non-standard
912 * value, don't extend it here. This happens on STA2X11, for example.
914 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
918 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
919 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
921 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
924 "64-bit DMA enable failed\n");
929 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
931 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
934 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
937 "32-bit consistent DMA enable failed\n");
944 static void ahci_pci_print_info(struct ata_host *host)
946 struct pci_dev *pdev = to_pci_dev(host->dev);
950 pci_read_config_word(pdev, 0x0a, &cc);
951 if (cc == PCI_CLASS_STORAGE_IDE)
953 else if (cc == PCI_CLASS_STORAGE_SATA)
955 else if (cc == PCI_CLASS_STORAGE_RAID)
960 ahci_print_info(host, scc_s);
963 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
964 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
965 * support PMP and the 4726 either directly exports the device
966 * attached to the first downstream port or acts as a hardware storage
967 * controller and emulate a single ATA device (can be RAID 0/1 or some
968 * other configuration).
970 * When there's no device attached to the first downstream port of the
971 * 4726, "Config Disk" appears, which is a pseudo ATA device to
972 * configure the 4726. However, ATA emulation of the device is very
973 * lame. It doesn't send signature D2H Reg FIS after the initial
974 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
976 * The following function works around the problem by always using
977 * hardreset on the port and not depending on receiving signature FIS
978 * afterward. If signature FIS isn't received soon, ATA class is
979 * assumed without follow-up softreset.
981 static void ahci_p5wdh_workaround(struct ata_host *host)
983 static const struct dmi_system_id sysids[] = {
985 .ident = "P5W DH Deluxe",
987 DMI_MATCH(DMI_SYS_VENDOR,
988 "ASUSTEK COMPUTER INC"),
989 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
994 struct pci_dev *pdev = to_pci_dev(host->dev);
996 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
997 dmi_check_system(sysids)) {
998 struct ata_port *ap = host->ports[1];
1000 dev_info(&pdev->dev,
1001 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1003 ap->ops = &ahci_p5wdh_ops;
1004 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1009 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1010 * booting in BIOS compatibility mode. We restore the registers but not ID.
1012 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1016 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1018 pci_read_config_dword(pdev, 0xf8, &val);
1020 /* the following changes the device ID, but appears not to affect function */
1021 /* val = (val & ~0xf0000000) | 0x80000000; */
1022 pci_write_config_dword(pdev, 0xf8, val);
1024 pci_read_config_dword(pdev, 0x54c, &val);
1026 pci_write_config_dword(pdev, 0x54c, val);
1028 pci_read_config_dword(pdev, 0x4a4, &val);
1031 pci_write_config_dword(pdev, 0x4a4, val);
1033 pci_read_config_dword(pdev, 0x54c, &val);
1035 pci_write_config_dword(pdev, 0x54c, val);
1037 pci_read_config_dword(pdev, 0xf8, &val);
1038 val &= ~(1 << 0x1b);
1039 pci_write_config_dword(pdev, 0xf8, val);
1042 static bool is_mcp89_apple(struct pci_dev *pdev)
1044 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1045 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1046 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1047 pdev->subsystem_device == 0xcb89;
1050 /* only some SB600 ahci controllers can do 64bit DMA */
1051 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1053 static const struct dmi_system_id sysids[] = {
1055 * The oldest version known to be broken is 0901 and
1056 * working is 1501 which was released on 2007-10-26.
1057 * Enable 64bit DMA on 1501 and anything newer.
1059 * Please read bko#9412 for more info.
1062 .ident = "ASUS M2A-VM",
1064 DMI_MATCH(DMI_BOARD_VENDOR,
1065 "ASUSTeK Computer INC."),
1066 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1068 .driver_data = "20071026", /* yyyymmdd */
1071 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1072 * support 64bit DMA.
1074 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1075 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1076 * This spelling mistake was fixed in BIOS version 1.5, so
1077 * 1.5 and later have the Manufacturer as
1078 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1079 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1081 * BIOS versions earlier than 1.9 had a Board Product Name
1082 * DMI field of "MS-7376". This was changed to be
1083 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1084 * match on DMI_BOARD_NAME of "MS-7376".
1087 .ident = "MSI K9A2 Platinum",
1089 DMI_MATCH(DMI_BOARD_VENDOR,
1090 "MICRO-STAR INTER"),
1091 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1095 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1098 * This board also had the typo mentioned above in the
1099 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1100 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1103 .ident = "MSI K9AGM2",
1105 DMI_MATCH(DMI_BOARD_VENDOR,
1106 "MICRO-STAR INTER"),
1107 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1111 * All BIOS versions for the Asus M3A support 64bit DMA.
1112 * (all release versions from 0301 to 1206 were tested)
1115 .ident = "ASUS M3A",
1117 DMI_MATCH(DMI_BOARD_VENDOR,
1118 "ASUSTeK Computer INC."),
1119 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1124 const struct dmi_system_id *match;
1125 int year, month, date;
1128 match = dmi_first_match(sysids);
1129 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1133 if (!match->driver_data)
1136 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1137 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1139 if (strcmp(buf, match->driver_data) >= 0)
1142 dev_warn(&pdev->dev,
1143 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1149 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1153 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1155 static const struct dmi_system_id broken_systems[] = {
1157 .ident = "HP Compaq nx6310",
1159 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1160 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1162 /* PCI slot number of the controller */
1163 .driver_data = (void *)0x1FUL,
1166 .ident = "HP Compaq 6720s",
1168 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1169 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1171 /* PCI slot number of the controller */
1172 .driver_data = (void *)0x1FUL,
1175 { } /* terminate list */
1177 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1180 unsigned long slot = (unsigned long)dmi->driver_data;
1181 /* apply the quirk only to on-board controllers */
1182 return slot == PCI_SLOT(pdev->devfn);
1188 static bool ahci_broken_suspend(struct pci_dev *pdev)
1190 static const struct dmi_system_id sysids[] = {
1192 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1193 * to the harddisk doesn't become online after
1194 * resuming from STR. Warn and fail suspend.
1196 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1198 * Use dates instead of versions to match as HP is
1199 * apparently recycling both product and version
1202 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1207 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1208 DMI_MATCH(DMI_PRODUCT_NAME,
1209 "HP Pavilion dv4 Notebook PC"),
1211 .driver_data = "20090105", /* F.30 */
1216 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1217 DMI_MATCH(DMI_PRODUCT_NAME,
1218 "HP Pavilion dv5 Notebook PC"),
1220 .driver_data = "20090506", /* F.16 */
1225 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1226 DMI_MATCH(DMI_PRODUCT_NAME,
1227 "HP Pavilion dv6 Notebook PC"),
1229 .driver_data = "20090423", /* F.21 */
1234 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1235 DMI_MATCH(DMI_PRODUCT_NAME,
1236 "HP HDX18 Notebook PC"),
1238 .driver_data = "20090430", /* F.23 */
1241 * Acer eMachines G725 has the same problem. BIOS
1242 * V1.03 is known to be broken. V3.04 is known to
1243 * work. Between, there are V1.06, V2.06 and V3.03
1244 * that we don't have much idea about. For now,
1245 * blacklist anything older than V3.04.
1247 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1252 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1253 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1255 .driver_data = "20091216", /* V3.04 */
1257 { } /* terminate list */
1259 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1260 int year, month, date;
1263 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1266 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1267 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1269 return strcmp(buf, dmi->driver_data) < 0;
1272 static bool ahci_broken_lpm(struct pci_dev *pdev)
1274 static const struct dmi_system_id sysids[] = {
1275 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1278 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1279 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1281 .driver_data = "20180406", /* 1.31 */
1285 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1286 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1288 .driver_data = "20180420", /* 1.28 */
1292 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1293 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1295 .driver_data = "20180315", /* 1.33 */
1299 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1300 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1303 * Note date based on release notes, 2.35 has been
1304 * reported to be good, but I've been unable to get
1305 * a hold of the reporter to get the DMI BIOS date.
1308 .driver_data = "20180310", /* 2.35 */
1310 { } /* terminate list */
1312 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1313 int year, month, date;
1319 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1320 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1322 return strcmp(buf, dmi->driver_data) < 0;
1325 static bool ahci_broken_online(struct pci_dev *pdev)
1327 #define ENCODE_BUSDEVFN(bus, slot, func) \
1328 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1329 static const struct dmi_system_id sysids[] = {
1331 * There are several gigabyte boards which use
1332 * SIMG5723s configured as hardware RAID. Certain
1333 * 5723 firmware revisions shipped there keep the link
1334 * online but fail to answer properly to SRST or
1335 * IDENTIFY when no device is attached downstream
1336 * causing libata to retry quite a few times leading
1337 * to excessive detection delay.
1339 * As these firmwares respond to the second reset try
1340 * with invalid device signature, considering unknown
1341 * sig as offline works around the problem acceptably.
1344 .ident = "EP45-DQ6",
1346 DMI_MATCH(DMI_BOARD_VENDOR,
1347 "Gigabyte Technology Co., Ltd."),
1348 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1350 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1353 .ident = "EP45-DS5",
1355 DMI_MATCH(DMI_BOARD_VENDOR,
1356 "Gigabyte Technology Co., Ltd."),
1357 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1359 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1361 { } /* terminate list */
1363 #undef ENCODE_BUSDEVFN
1364 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1370 val = (unsigned long)dmi->driver_data;
1372 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1375 static bool ahci_broken_devslp(struct pci_dev *pdev)
1377 /* device with broken DEVSLP but still showing SDS capability */
1378 static const struct pci_device_id ids[] = {
1379 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1383 return pci_match_id(ids, pdev);
1386 #ifdef CONFIG_ATA_ACPI
1387 static void ahci_gtf_filter_workaround(struct ata_host *host)
1389 static const struct dmi_system_id sysids[] = {
1391 * Aspire 3810T issues a bunch of SATA enable commands
1392 * via _GTF including an invalid one and one which is
1393 * rejected by the device. Among the successful ones
1394 * is FPDMA non-zero offset enable which when enabled
1395 * only on the drive side leads to NCQ command
1396 * failures. Filter it out.
1399 .ident = "Aspire 3810T",
1401 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1402 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1404 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1408 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1409 unsigned int filter;
1415 filter = (unsigned long)dmi->driver_data;
1416 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1417 filter, dmi->ident);
1419 for (i = 0; i < host->n_ports; i++) {
1420 struct ata_port *ap = host->ports[i];
1421 struct ata_link *link;
1422 struct ata_device *dev;
1424 ata_for_each_link(link, ap, EDGE)
1425 ata_for_each_dev(dev, link, ALL)
1426 dev->gtf_filter |= filter;
1430 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1435 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1436 * as DUMMY, or detected but eventually get a "link down" and never get up
1437 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1438 * port_map may hold a value of 0x00.
1440 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1441 * and can significantly reduce the occurrence of the problem.
1443 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1445 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1446 struct pci_dev *pdev)
1448 static const struct dmi_system_id sysids[] = {
1450 .ident = "Acer Switch Alpha 12",
1452 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1453 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1459 if (dmi_check_system(sysids)) {
1460 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1461 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1462 hpriv->port_map = 0x7;
1463 hpriv->cap = 0xC734FF02;
1470 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1471 * Workaround is to make sure all pending IRQs are served before leaving
1474 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1476 struct ata_host *host = dev_instance;
1477 struct ahci_host_priv *hpriv;
1478 unsigned int rc = 0;
1480 u32 irq_stat, irq_masked;
1481 unsigned int handled = 1;
1483 hpriv = host->private_data;
1485 irq_stat = readl(mmio + HOST_IRQ_STAT);
1490 irq_masked = irq_stat & hpriv->port_map;
1491 spin_lock(&host->lock);
1492 rc = ahci_handle_port_intr(host, irq_masked);
1495 writel(irq_stat, mmio + HOST_IRQ_STAT);
1496 irq_stat = readl(mmio + HOST_IRQ_STAT);
1497 spin_unlock(&host->lock);
1500 return IRQ_RETVAL(handled);
1504 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1505 struct ahci_host_priv *hpriv)
1511 * Check if this device might have remapped nvme devices.
1513 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1514 pci_resource_len(pdev, bar) < SZ_512K ||
1515 bar != AHCI_PCI_BAR_STANDARD ||
1516 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1519 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1520 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1521 if ((cap & (1 << i)) == 0)
1523 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1524 != PCI_CLASS_STORAGE_EXPRESS)
1527 /* We've found a remapped device */
1534 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1535 dev_warn(&pdev->dev,
1536 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1539 * Don't rely on the msi-x capability in the remap case,
1540 * share the legacy interrupt across ahci and remapped devices.
1542 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1545 static int ahci_get_irq_vector(struct ata_host *host, int port)
1547 return pci_irq_vector(to_pci_dev(host->dev), port);
1550 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1551 struct ahci_host_priv *hpriv)
1555 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1559 * If number of MSIs is less than number of ports then Sharing Last
1560 * Message mode could be enforced. In this case assume that advantage
1561 * of multipe MSIs is negated and use single MSI mode instead.
1564 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1565 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1567 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1568 hpriv->get_irq_vector = ahci_get_irq_vector;
1569 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1574 * Fallback to single MSI mode if the controller
1575 * enforced MRSM mode.
1578 "ahci: MRSM is on, fallback to single MSI\n");
1579 pci_free_irq_vectors(pdev);
1584 * If the host is not capable of supporting per-port vectors, fall
1585 * back to single MSI before finally attempting single MSI-X.
1587 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1590 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1593 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1595 unsigned int board_id = ent->driver_data;
1596 struct ata_port_info pi = ahci_port_info[board_id];
1597 const struct ata_port_info *ppi[] = { &pi, NULL };
1598 struct device *dev = &pdev->dev;
1599 struct ahci_host_priv *hpriv;
1600 struct ata_host *host;
1602 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1606 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1608 ata_print_version_once(&pdev->dev, DRV_VERSION);
1610 /* The AHCI driver can only drive the SATA ports, the PATA driver
1611 can drive them all so if both drivers are selected make sure
1612 AHCI stays out of the way */
1613 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1616 /* Apple BIOS on MCP89 prevents us using AHCI */
1617 if (is_mcp89_apple(pdev))
1618 ahci_mcp89_apple_enable(pdev);
1620 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1621 * At the moment, we can only use the AHCI mode. Let the users know
1622 * that for SAS drives they're out of luck.
1624 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1625 dev_info(&pdev->dev,
1626 "PDC42819 can only drive SATA devices with this driver\n");
1628 /* Some devices use non-standard BARs */
1629 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1630 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1631 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1632 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1633 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1634 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1636 /* acquire resources */
1637 rc = pcim_enable_device(pdev);
1641 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1642 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1645 /* ICH6s share the same PCI ID for both piix and ahci
1646 * modes. Enabling ahci mode while MAP indicates
1647 * combined mode is a bad idea. Yield to ata_piix.
1649 pci_read_config_byte(pdev, ICH_MAP, &map);
1651 dev_info(&pdev->dev,
1652 "controller is in combined mode, can't enable AHCI mode\n");
1657 /* AHCI controllers often implement SFF compatible interface.
1658 * Grab all PCI BARs just in case.
1660 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1662 pcim_pin_device(pdev);
1666 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1669 hpriv->flags |= (unsigned long)pi.private_data;
1671 /* MCP65 revision A1 and A2 can't do MSI */
1672 if (board_id == board_ahci_mcp65 &&
1673 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1674 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1676 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1677 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1678 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1680 /* only some SB600s can do 64bit DMA */
1681 if (ahci_sb600_enable_64bit(pdev))
1682 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1684 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1686 /* detect remapped nvme devices */
1687 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1689 /* must set flag prior to save config in order to take effect */
1690 if (ahci_broken_devslp(pdev))
1691 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1694 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1695 hpriv->irq_handler = ahci_thunderx_irq_handler;
1698 /* save initial config */
1699 ahci_pci_save_initial_config(pdev, hpriv);
1702 if (hpriv->cap & HOST_CAP_NCQ) {
1703 pi.flags |= ATA_FLAG_NCQ;
1705 * Auto-activate optimization is supposed to be
1706 * supported on all AHCI controllers indicating NCQ
1707 * capability, but it seems to be broken on some
1708 * chipsets including NVIDIAs.
1710 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1711 pi.flags |= ATA_FLAG_FPDMA_AA;
1714 * All AHCI controllers should be forward-compatible
1715 * with the new auxiliary field. This code should be
1716 * conditionalized if any buggy AHCI controllers are
1719 pi.flags |= ATA_FLAG_FPDMA_AUX;
1722 if (hpriv->cap & HOST_CAP_PMP)
1723 pi.flags |= ATA_FLAG_PMP;
1725 ahci_set_em_messages(hpriv, &pi);
1727 if (ahci_broken_system_poweroff(pdev)) {
1728 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1729 dev_info(&pdev->dev,
1730 "quirky BIOS, skipping spindown on poweroff\n");
1733 if (ahci_broken_lpm(pdev)) {
1734 pi.flags |= ATA_FLAG_NO_LPM;
1735 dev_warn(&pdev->dev,
1736 "BIOS update required for Link Power Management support\n");
1739 if (ahci_broken_suspend(pdev)) {
1740 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1741 dev_warn(&pdev->dev,
1742 "BIOS update required for suspend/resume\n");
1745 if (ahci_broken_online(pdev)) {
1746 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1747 dev_info(&pdev->dev,
1748 "online status unreliable, applying workaround\n");
1752 /* Acer SA5-271 workaround modifies private_data */
1753 acer_sa5_271_workaround(hpriv, pdev);
1755 /* CAP.NP sometimes indicate the index of the last enabled
1756 * port, at other times, that of the last possible port, so
1757 * determining the maximum port number requires looking at
1758 * both CAP.NP and port_map.
1760 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1762 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1765 host->private_data = hpriv;
1767 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1768 /* legacy intx interrupts */
1771 hpriv->irq = pci_irq_vector(pdev, 0);
1773 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1774 host->flags |= ATA_HOST_PARALLEL_SCAN;
1776 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1778 if (!(hpriv->cap & HOST_CAP_PART))
1779 host->flags |= ATA_HOST_NO_PART;
1781 if (!(hpriv->cap & HOST_CAP_SSC))
1782 host->flags |= ATA_HOST_NO_SSC;
1784 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1785 host->flags |= ATA_HOST_NO_DEVSLP;
1787 if (pi.flags & ATA_FLAG_EM)
1788 ahci_reset_em(host);
1790 for (i = 0; i < host->n_ports; i++) {
1791 struct ata_port *ap = host->ports[i];
1793 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1794 ata_port_pbar_desc(ap, ahci_pci_bar,
1795 0x100 + ap->port_no * 0x80, "port");
1797 /* set enclosure management message type */
1798 if (ap->flags & ATA_FLAG_EM)
1799 ap->em_message_type = hpriv->em_msg_type;
1802 /* disabled/not-implemented port */
1803 if (!(hpriv->port_map & (1 << i)))
1804 ap->ops = &ata_dummy_port_ops;
1807 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1808 ahci_p5wdh_workaround(host);
1810 /* apply gtf filter quirk */
1811 ahci_gtf_filter_workaround(host);
1813 /* initialize adapter */
1814 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1818 rc = ahci_pci_reset_controller(host);
1822 ahci_pci_init_controller(host);
1823 ahci_pci_print_info(host);
1825 pci_set_master(pdev);
1827 rc = ahci_host_activate(host, &ahci_sht);
1831 pm_runtime_put_noidle(&pdev->dev);
1835 static void ahci_shutdown_one(struct pci_dev *pdev)
1837 ata_pci_shutdown_one(pdev);
1840 static void ahci_remove_one(struct pci_dev *pdev)
1842 pm_runtime_get_noresume(&pdev->dev);
1843 ata_pci_remove_one(pdev);
1846 module_pci_driver(ahci_pci_driver);
1848 MODULE_AUTHOR("Jeff Garzik");
1849 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1850 MODULE_LICENSE("GPL");
1851 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1852 MODULE_VERSION(DRV_VERSION);