1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
50 /* board IDs by feature in alphabetical order */
55 board_ahci_no_debounce_delay,
61 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_sb700, /* for SB700 and SB800 */
73 * board IDs for Intel chipsets that support more than 6 ports
74 * *and* end up needing the PCS quirk.
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static void ahci_remove_one(struct pci_dev *dev);
87 static void ahci_shutdown_one(struct pci_dev *dev);
88 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
89 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
93 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
94 static bool is_mcp89_apple(struct pci_dev *pdev);
95 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
96 unsigned long deadline);
98 static int ahci_pci_device_runtime_suspend(struct device *dev);
99 static int ahci_pci_device_runtime_resume(struct device *dev);
100 #ifdef CONFIG_PM_SLEEP
101 static int ahci_pci_device_suspend(struct device *dev);
102 static int ahci_pci_device_resume(struct device *dev);
104 #endif /* CONFIG_PM */
106 static struct scsi_host_template ahci_sht = {
110 static struct ata_port_operations ahci_vt8251_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_vt8251_hardreset,
115 static struct ata_port_operations ahci_p5wdh_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_p5wdh_hardreset,
120 static struct ata_port_operations ahci_avn_ops = {
121 .inherits = &ahci_ops,
122 .hardreset = ahci_avn_hardreset,
125 static const struct ata_port_info ahci_port_info[] = {
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
133 [board_ahci_43bit_dma] = {
134 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
140 [board_ahci_ign_iferr] = {
141 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
147 [board_ahci_low_power] = {
148 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
154 [board_ahci_no_debounce_delay] = {
155 .flags = AHCI_FLAG_COMMON,
156 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
161 [board_ahci_nomsi] = {
162 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
168 [board_ahci_noncq] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
175 [board_ahci_nosntf] = {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
177 .flags = AHCI_FLAG_COMMON,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_ops,
182 [board_ahci_yes_fbs] = {
183 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
187 .port_ops = &ahci_ops,
191 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
192 .flags = AHCI_FLAG_COMMON,
193 .pio_mask = ATA_PIO4,
194 .udma_mask = ATA_UDMA6,
195 .port_ops = &ahci_ops,
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_avn_ops,
203 [board_ahci_mcp65] = {
204 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
206 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
207 .pio_mask = ATA_PIO4,
208 .udma_mask = ATA_UDMA6,
209 .port_ops = &ahci_ops,
211 [board_ahci_mcp77] = {
212 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
213 .flags = AHCI_FLAG_COMMON,
214 .pio_mask = ATA_PIO4,
215 .udma_mask = ATA_UDMA6,
216 .port_ops = &ahci_ops,
218 [board_ahci_mcp89] = {
219 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_ops,
226 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
227 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
228 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_ops,
233 [board_ahci_sb600] = {
234 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
235 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
236 AHCI_HFLAG_32BIT_ONLY),
237 .flags = AHCI_FLAG_COMMON,
238 .pio_mask = ATA_PIO4,
239 .udma_mask = ATA_UDMA6,
240 .port_ops = &ahci_pmp_retry_srst_ops,
242 [board_ahci_sb700] = { /* for SB700 and SB800 */
243 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
244 .flags = AHCI_FLAG_COMMON,
245 .pio_mask = ATA_PIO4,
246 .udma_mask = ATA_UDMA6,
247 .port_ops = &ahci_pmp_retry_srst_ops,
249 [board_ahci_vt8251] = {
250 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
251 .flags = AHCI_FLAG_COMMON,
252 .pio_mask = ATA_PIO4,
253 .udma_mask = ATA_UDMA6,
254 .port_ops = &ahci_vt8251_ops,
256 [board_ahci_pcs7] = {
257 .flags = AHCI_FLAG_COMMON,
258 .pio_mask = ATA_PIO4,
259 .udma_mask = ATA_UDMA6,
260 .port_ops = &ahci_ops,
264 static const struct pci_device_id ahci_pci_tbl[] = {
266 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
267 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
268 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
269 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
270 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
271 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
272 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
273 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
274 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
275 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
276 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
277 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
278 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
279 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
280 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
281 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
282 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
285 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
286 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
287 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
290 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
292 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
293 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
294 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
295 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
296 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
297 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
298 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
299 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
300 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
301 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
303 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
304 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
305 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
306 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
327 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
328 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
329 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
330 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
331 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
332 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
333 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
334 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
335 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
336 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
337 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
338 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
339 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
340 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
342 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
343 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
344 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
345 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
346 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
347 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
351 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
352 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
353 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
354 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
355 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
360 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
361 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
363 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
364 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
369 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
370 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
371 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
372 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
376 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
377 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
378 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
379 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
380 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
383 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
384 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
385 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
387 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
389 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
391 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
392 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
393 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
394 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
396 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
397 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
398 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
399 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
404 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
405 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
406 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
407 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
408 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
409 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
410 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
413 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
414 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
415 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
416 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
417 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
419 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
421 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
422 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
423 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
424 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
425 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
426 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
427 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
428 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
429 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
430 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
431 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
432 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
433 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
434 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
435 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
436 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
437 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
439 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
440 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
441 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
442 /* JMicron 362B and 362C have an AHCI function with IDE class code */
443 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
444 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
445 /* May need to update quirk_jmicron_async_suspend() for additions */
448 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
449 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
451 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
452 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
453 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
454 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
456 /* Amazon's Annapurna Labs support */
457 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
458 .class = PCI_CLASS_STORAGE_SATA_AHCI,
459 .class_mask = 0xffffff,
462 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
463 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
464 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
465 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
466 /* AMD is using RAID class only for ahci controllers */
467 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
468 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
471 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
472 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
475 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
476 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
561 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
562 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
563 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
565 /* ST Microelectronics */
566 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
569 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
570 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
572 .class = PCI_CLASS_STORAGE_SATA_AHCI,
573 .class_mask = 0xffffff,
574 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
576 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
577 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
578 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
579 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
581 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
585 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
587 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
589 .driver_data = board_ahci_yes_fbs },
590 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
591 .driver_data = board_ahci_yes_fbs },
592 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
593 .driver_data = board_ahci_yes_fbs },
594 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
595 .driver_data = board_ahci_yes_fbs },
596 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
597 .driver_data = board_ahci_yes_fbs },
598 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
599 .driver_data = board_ahci_yes_fbs },
602 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
603 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
606 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
607 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
608 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
609 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
610 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
611 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
614 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
615 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
617 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
618 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
621 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
624 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
626 /* Generic, PCI class code for AHCI */
627 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
628 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
630 { } /* terminate list */
633 static const struct dev_pm_ops ahci_pci_pm_ops = {
634 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
635 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
636 ahci_pci_device_runtime_resume, NULL)
639 static struct pci_driver ahci_pci_driver = {
641 .id_table = ahci_pci_tbl,
642 .probe = ahci_init_one,
643 .remove = ahci_remove_one,
644 .shutdown = ahci_shutdown_one,
646 .pm = &ahci_pci_pm_ops,
650 #if IS_ENABLED(CONFIG_PATA_MARVELL)
651 static int marvell_enable;
653 static int marvell_enable = 1;
655 module_param(marvell_enable, int, 0644);
656 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
658 static int mobile_lpm_policy = -1;
659 module_param(mobile_lpm_policy, int, 0644);
660 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
662 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
663 struct ahci_host_priv *hpriv)
665 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
666 dev_info(&pdev->dev, "JMB361 has only one port\n");
667 hpriv->force_port_map = 1;
671 * Temporary Marvell 6145 hack: PATA port presence
672 * is asserted through the standard AHCI port
673 * presence register, as bit 4 (counting from 0)
675 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
676 if (pdev->device == 0x6121)
677 hpriv->mask_port_map = 0x3;
679 hpriv->mask_port_map = 0xf;
681 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
684 ahci_save_initial_config(&pdev->dev, hpriv);
687 static int ahci_pci_reset_controller(struct ata_host *host)
689 struct pci_dev *pdev = to_pci_dev(host->dev);
690 struct ahci_host_priv *hpriv = host->private_data;
693 rc = ahci_reset_controller(host);
698 * If platform firmware failed to enable ports, try to enable
701 ahci_intel_pcs_quirk(pdev, hpriv);
706 static void ahci_pci_init_controller(struct ata_host *host)
708 struct ahci_host_priv *hpriv = host->private_data;
709 struct pci_dev *pdev = to_pci_dev(host->dev);
710 void __iomem *port_mmio;
714 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
715 if (pdev->device == 0x6121)
719 port_mmio = __ahci_port_base(host, mv);
721 writel(0, port_mmio + PORT_IRQ_MASK);
724 tmp = readl(port_mmio + PORT_IRQ_STAT);
725 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
727 writel(tmp, port_mmio + PORT_IRQ_STAT);
730 ahci_init_controller(host);
733 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
734 unsigned long deadline)
736 struct ata_port *ap = link->ap;
737 struct ahci_host_priv *hpriv = ap->host->private_data;
743 hpriv->stop_engine(ap);
745 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
746 deadline, &online, NULL);
748 hpriv->start_engine(ap);
750 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
752 /* vt8251 doesn't clear BSY on signature FIS reception,
753 * request follow-up softreset.
755 return online ? -EAGAIN : rc;
758 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
759 unsigned long deadline)
761 struct ata_port *ap = link->ap;
762 struct ahci_port_priv *pp = ap->private_data;
763 struct ahci_host_priv *hpriv = ap->host->private_data;
764 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
765 struct ata_taskfile tf;
769 hpriv->stop_engine(ap);
771 /* clear D2H reception area to properly wait for D2H FIS */
772 ata_tf_init(link->device, &tf);
773 tf.command = ATA_BUSY;
774 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
776 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
777 deadline, &online, NULL);
779 hpriv->start_engine(ap);
781 /* The pseudo configuration device on SIMG4726 attached to
782 * ASUS P5W-DH Deluxe doesn't send signature FIS after
783 * hardreset if no device is attached to the first downstream
784 * port && the pseudo device locks up on SRST w/ PMP==0. To
785 * work around this, wait for !BSY only briefly. If BSY isn't
786 * cleared, perform CLO and proceed to IDENTIFY (achieved by
787 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
789 * Wait for two seconds. Devices attached to downstream port
790 * which can't process the following IDENTIFY after this will
791 * have to be reset again. For most cases, this should
792 * suffice while making probing snappish enough.
795 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
798 ahci_kick_engine(ap);
804 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
806 * It has been observed with some SSDs that the timing of events in the
807 * link synchronization phase can leave the port in a state that can not
808 * be recovered by a SATA-hard-reset alone. The failing signature is
809 * SStatus.DET stuck at 1 ("Device presence detected but Phy
810 * communication not established"). It was found that unloading and
811 * reloading the driver when this problem occurs allows the drive
812 * connection to be recovered (DET advanced to 0x3). The critical
813 * component of reloading the driver is that the port state machines are
814 * reset by bouncing "port enable" in the AHCI PCS configuration
815 * register. So, reproduce that effect by bouncing a port whenever we
816 * see DET==1 after a reset.
818 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
819 unsigned long deadline)
821 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
822 struct ata_port *ap = link->ap;
823 struct ahci_port_priv *pp = ap->private_data;
824 struct ahci_host_priv *hpriv = ap->host->private_data;
825 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
826 unsigned long tmo = deadline - jiffies;
827 struct ata_taskfile tf;
833 hpriv->stop_engine(ap);
835 for (i = 0; i < 2; i++) {
838 int port = ap->port_no;
839 struct ata_host *host = ap->host;
840 struct pci_dev *pdev = to_pci_dev(host->dev);
842 /* clear D2H reception area to properly wait for D2H FIS */
843 ata_tf_init(link->device, &tf);
844 tf.command = ATA_BUSY;
845 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
847 rc = sata_link_hardreset(link, timing, deadline, &online,
850 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
851 (sstatus & 0xf) != 1)
854 ata_link_info(link, "avn bounce port%d\n", port);
856 pci_read_config_word(pdev, 0x92, &val);
858 pci_write_config_word(pdev, 0x92, val);
859 ata_msleep(ap, 1000);
861 pci_write_config_word(pdev, 0x92, val);
865 hpriv->start_engine(ap);
868 *class = ahci_dev_classify(ap);
870 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
876 static void ahci_pci_disable_interrupts(struct ata_host *host)
878 struct ahci_host_priv *hpriv = host->private_data;
879 void __iomem *mmio = hpriv->mmio;
882 /* AHCI spec rev1.1 section 8.3.3:
883 * Software must disable interrupts prior to requesting a
884 * transition of the HBA to D3 state.
886 ctl = readl(mmio + HOST_CTL);
888 writel(ctl, mmio + HOST_CTL);
889 readl(mmio + HOST_CTL); /* flush */
892 static int ahci_pci_device_runtime_suspend(struct device *dev)
894 struct pci_dev *pdev = to_pci_dev(dev);
895 struct ata_host *host = pci_get_drvdata(pdev);
897 ahci_pci_disable_interrupts(host);
901 static int ahci_pci_device_runtime_resume(struct device *dev)
903 struct pci_dev *pdev = to_pci_dev(dev);
904 struct ata_host *host = pci_get_drvdata(pdev);
907 rc = ahci_pci_reset_controller(host);
910 ahci_pci_init_controller(host);
914 #ifdef CONFIG_PM_SLEEP
915 static int ahci_pci_device_suspend(struct device *dev)
917 struct pci_dev *pdev = to_pci_dev(dev);
918 struct ata_host *host = pci_get_drvdata(pdev);
919 struct ahci_host_priv *hpriv = host->private_data;
921 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
923 "BIOS update required for suspend/resume\n");
927 ahci_pci_disable_interrupts(host);
928 return ata_host_suspend(host, PMSG_SUSPEND);
931 static int ahci_pci_device_resume(struct device *dev)
933 struct pci_dev *pdev = to_pci_dev(dev);
934 struct ata_host *host = pci_get_drvdata(pdev);
937 /* Apple BIOS helpfully mangles the registers on resume */
938 if (is_mcp89_apple(pdev))
939 ahci_mcp89_apple_enable(pdev);
941 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
942 rc = ahci_pci_reset_controller(host);
946 ahci_pci_init_controller(host);
949 ata_host_resume(host);
955 #endif /* CONFIG_PM */
957 static int ahci_configure_dma_masks(struct pci_dev *pdev,
958 struct ahci_host_priv *hpriv)
963 if (hpriv->cap & HOST_CAP_64) {
965 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
972 * If the device fixup already set the dma_mask to some non-standard
973 * value, don't extend it here. This happens on STA2X11, for example.
975 * XXX: manipulating the DMA mask from platform code is completely
976 * bogus, platform code should use dev->bus_dma_limit instead..
978 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
981 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
983 dev_err(&pdev->dev, "DMA enable failed\n");
987 static void ahci_pci_print_info(struct ata_host *host)
989 struct pci_dev *pdev = to_pci_dev(host->dev);
993 pci_read_config_word(pdev, 0x0a, &cc);
994 if (cc == PCI_CLASS_STORAGE_IDE)
996 else if (cc == PCI_CLASS_STORAGE_SATA)
998 else if (cc == PCI_CLASS_STORAGE_RAID)
1003 ahci_print_info(host, scc_s);
1006 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1007 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1008 * support PMP and the 4726 either directly exports the device
1009 * attached to the first downstream port or acts as a hardware storage
1010 * controller and emulate a single ATA device (can be RAID 0/1 or some
1011 * other configuration).
1013 * When there's no device attached to the first downstream port of the
1014 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1015 * configure the 4726. However, ATA emulation of the device is very
1016 * lame. It doesn't send signature D2H Reg FIS after the initial
1017 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1019 * The following function works around the problem by always using
1020 * hardreset on the port and not depending on receiving signature FIS
1021 * afterward. If signature FIS isn't received soon, ATA class is
1022 * assumed without follow-up softreset.
1024 static void ahci_p5wdh_workaround(struct ata_host *host)
1026 static const struct dmi_system_id sysids[] = {
1028 .ident = "P5W DH Deluxe",
1030 DMI_MATCH(DMI_SYS_VENDOR,
1031 "ASUSTEK COMPUTER INC"),
1032 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1037 struct pci_dev *pdev = to_pci_dev(host->dev);
1039 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1040 dmi_check_system(sysids)) {
1041 struct ata_port *ap = host->ports[1];
1043 dev_info(&pdev->dev,
1044 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1046 ap->ops = &ahci_p5wdh_ops;
1047 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1052 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1053 * booting in BIOS compatibility mode. We restore the registers but not ID.
1055 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1059 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1061 pci_read_config_dword(pdev, 0xf8, &val);
1063 /* the following changes the device ID, but appears not to affect function */
1064 /* val = (val & ~0xf0000000) | 0x80000000; */
1065 pci_write_config_dword(pdev, 0xf8, val);
1067 pci_read_config_dword(pdev, 0x54c, &val);
1069 pci_write_config_dword(pdev, 0x54c, val);
1071 pci_read_config_dword(pdev, 0x4a4, &val);
1074 pci_write_config_dword(pdev, 0x4a4, val);
1076 pci_read_config_dword(pdev, 0x54c, &val);
1078 pci_write_config_dword(pdev, 0x54c, val);
1080 pci_read_config_dword(pdev, 0xf8, &val);
1081 val &= ~(1 << 0x1b);
1082 pci_write_config_dword(pdev, 0xf8, val);
1085 static bool is_mcp89_apple(struct pci_dev *pdev)
1087 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1088 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1089 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1090 pdev->subsystem_device == 0xcb89;
1093 /* only some SB600 ahci controllers can do 64bit DMA */
1094 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1096 static const struct dmi_system_id sysids[] = {
1098 * The oldest version known to be broken is 0901 and
1099 * working is 1501 which was released on 2007-10-26.
1100 * Enable 64bit DMA on 1501 and anything newer.
1102 * Please read bko#9412 for more info.
1105 .ident = "ASUS M2A-VM",
1107 DMI_MATCH(DMI_BOARD_VENDOR,
1108 "ASUSTeK Computer INC."),
1109 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1111 .driver_data = "20071026", /* yyyymmdd */
1114 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1115 * support 64bit DMA.
1117 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1118 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1119 * This spelling mistake was fixed in BIOS version 1.5, so
1120 * 1.5 and later have the Manufacturer as
1121 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1122 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1124 * BIOS versions earlier than 1.9 had a Board Product Name
1125 * DMI field of "MS-7376". This was changed to be
1126 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1127 * match on DMI_BOARD_NAME of "MS-7376".
1130 .ident = "MSI K9A2 Platinum",
1132 DMI_MATCH(DMI_BOARD_VENDOR,
1133 "MICRO-STAR INTER"),
1134 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1138 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1141 * This board also had the typo mentioned above in the
1142 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1143 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1146 .ident = "MSI K9AGM2",
1148 DMI_MATCH(DMI_BOARD_VENDOR,
1149 "MICRO-STAR INTER"),
1150 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1154 * All BIOS versions for the Asus M3A support 64bit DMA.
1155 * (all release versions from 0301 to 1206 were tested)
1158 .ident = "ASUS M3A",
1160 DMI_MATCH(DMI_BOARD_VENDOR,
1161 "ASUSTeK Computer INC."),
1162 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1167 const struct dmi_system_id *match;
1168 int year, month, date;
1171 match = dmi_first_match(sysids);
1172 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1176 if (!match->driver_data)
1179 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1180 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1182 if (strcmp(buf, match->driver_data) >= 0)
1185 dev_warn(&pdev->dev,
1186 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1192 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1196 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1198 static const struct dmi_system_id broken_systems[] = {
1200 .ident = "HP Compaq nx6310",
1202 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1203 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1205 /* PCI slot number of the controller */
1206 .driver_data = (void *)0x1FUL,
1209 .ident = "HP Compaq 6720s",
1211 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1212 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1214 /* PCI slot number of the controller */
1215 .driver_data = (void *)0x1FUL,
1218 { } /* terminate list */
1220 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1223 unsigned long slot = (unsigned long)dmi->driver_data;
1224 /* apply the quirk only to on-board controllers */
1225 return slot == PCI_SLOT(pdev->devfn);
1231 static bool ahci_broken_suspend(struct pci_dev *pdev)
1233 static const struct dmi_system_id sysids[] = {
1235 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1236 * to the harddisk doesn't become online after
1237 * resuming from STR. Warn and fail suspend.
1239 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1241 * Use dates instead of versions to match as HP is
1242 * apparently recycling both product and version
1245 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1250 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1251 DMI_MATCH(DMI_PRODUCT_NAME,
1252 "HP Pavilion dv4 Notebook PC"),
1254 .driver_data = "20090105", /* F.30 */
1259 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1260 DMI_MATCH(DMI_PRODUCT_NAME,
1261 "HP Pavilion dv5 Notebook PC"),
1263 .driver_data = "20090506", /* F.16 */
1268 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1269 DMI_MATCH(DMI_PRODUCT_NAME,
1270 "HP Pavilion dv6 Notebook PC"),
1272 .driver_data = "20090423", /* F.21 */
1277 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1278 DMI_MATCH(DMI_PRODUCT_NAME,
1279 "HP HDX18 Notebook PC"),
1281 .driver_data = "20090430", /* F.23 */
1284 * Acer eMachines G725 has the same problem. BIOS
1285 * V1.03 is known to be broken. V3.04 is known to
1286 * work. Between, there are V1.06, V2.06 and V3.03
1287 * that we don't have much idea about. For now,
1288 * blacklist anything older than V3.04.
1290 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1295 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1296 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1298 .driver_data = "20091216", /* V3.04 */
1300 { } /* terminate list */
1302 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1303 int year, month, date;
1306 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1309 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1310 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1312 return strcmp(buf, dmi->driver_data) < 0;
1315 static bool ahci_broken_lpm(struct pci_dev *pdev)
1317 static const struct dmi_system_id sysids[] = {
1318 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1321 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1322 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1324 .driver_data = "20180406", /* 1.31 */
1328 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1329 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1331 .driver_data = "20180420", /* 1.28 */
1335 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1336 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1338 .driver_data = "20180315", /* 1.33 */
1342 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1343 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1346 * Note date based on release notes, 2.35 has been
1347 * reported to be good, but I've been unable to get
1348 * a hold of the reporter to get the DMI BIOS date.
1351 .driver_data = "20180310", /* 2.35 */
1353 { } /* terminate list */
1355 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1356 int year, month, date;
1362 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1363 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1365 return strcmp(buf, dmi->driver_data) < 0;
1368 static bool ahci_broken_online(struct pci_dev *pdev)
1370 #define ENCODE_BUSDEVFN(bus, slot, func) \
1371 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1372 static const struct dmi_system_id sysids[] = {
1374 * There are several gigabyte boards which use
1375 * SIMG5723s configured as hardware RAID. Certain
1376 * 5723 firmware revisions shipped there keep the link
1377 * online but fail to answer properly to SRST or
1378 * IDENTIFY when no device is attached downstream
1379 * causing libata to retry quite a few times leading
1380 * to excessive detection delay.
1382 * As these firmwares respond to the second reset try
1383 * with invalid device signature, considering unknown
1384 * sig as offline works around the problem acceptably.
1387 .ident = "EP45-DQ6",
1389 DMI_MATCH(DMI_BOARD_VENDOR,
1390 "Gigabyte Technology Co., Ltd."),
1391 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1393 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1396 .ident = "EP45-DS5",
1398 DMI_MATCH(DMI_BOARD_VENDOR,
1399 "Gigabyte Technology Co., Ltd."),
1400 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1402 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1404 { } /* terminate list */
1406 #undef ENCODE_BUSDEVFN
1407 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1413 val = (unsigned long)dmi->driver_data;
1415 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1418 static bool ahci_broken_devslp(struct pci_dev *pdev)
1420 /* device with broken DEVSLP but still showing SDS capability */
1421 static const struct pci_device_id ids[] = {
1422 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1426 return pci_match_id(ids, pdev);
1429 #ifdef CONFIG_ATA_ACPI
1430 static void ahci_gtf_filter_workaround(struct ata_host *host)
1432 static const struct dmi_system_id sysids[] = {
1434 * Aspire 3810T issues a bunch of SATA enable commands
1435 * via _GTF including an invalid one and one which is
1436 * rejected by the device. Among the successful ones
1437 * is FPDMA non-zero offset enable which when enabled
1438 * only on the drive side leads to NCQ command
1439 * failures. Filter it out.
1442 .ident = "Aspire 3810T",
1444 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1445 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1447 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1451 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1452 unsigned int filter;
1458 filter = (unsigned long)dmi->driver_data;
1459 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1460 filter, dmi->ident);
1462 for (i = 0; i < host->n_ports; i++) {
1463 struct ata_port *ap = host->ports[i];
1464 struct ata_link *link;
1465 struct ata_device *dev;
1467 ata_for_each_link(link, ap, EDGE)
1468 ata_for_each_dev(dev, link, ALL)
1469 dev->gtf_filter |= filter;
1473 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1478 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1479 * as DUMMY, or detected but eventually get a "link down" and never get up
1480 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1481 * port_map may hold a value of 0x00.
1483 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1484 * and can significantly reduce the occurrence of the problem.
1486 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1488 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1489 struct pci_dev *pdev)
1491 static const struct dmi_system_id sysids[] = {
1493 .ident = "Acer Switch Alpha 12",
1495 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1496 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1502 if (dmi_check_system(sysids)) {
1503 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1504 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1505 hpriv->port_map = 0x7;
1506 hpriv->cap = 0xC734FF02;
1513 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1514 * Workaround is to make sure all pending IRQs are served before leaving
1517 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1519 struct ata_host *host = dev_instance;
1520 struct ahci_host_priv *hpriv;
1521 unsigned int rc = 0;
1523 u32 irq_stat, irq_masked;
1524 unsigned int handled = 1;
1526 hpriv = host->private_data;
1528 irq_stat = readl(mmio + HOST_IRQ_STAT);
1533 irq_masked = irq_stat & hpriv->port_map;
1534 spin_lock(&host->lock);
1535 rc = ahci_handle_port_intr(host, irq_masked);
1538 writel(irq_stat, mmio + HOST_IRQ_STAT);
1539 irq_stat = readl(mmio + HOST_IRQ_STAT);
1540 spin_unlock(&host->lock);
1543 return IRQ_RETVAL(handled);
1547 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1548 struct ahci_host_priv *hpriv)
1554 * Check if this device might have remapped nvme devices.
1556 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1557 pci_resource_len(pdev, bar) < SZ_512K ||
1558 bar != AHCI_PCI_BAR_STANDARD ||
1559 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1562 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1563 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1564 if ((cap & (1 << i)) == 0)
1566 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1567 != PCI_CLASS_STORAGE_EXPRESS)
1570 /* We've found a remapped device */
1571 hpriv->remapped_nvme++;
1574 if (!hpriv->remapped_nvme)
1577 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1578 hpriv->remapped_nvme);
1579 dev_warn(&pdev->dev,
1580 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1583 * Don't rely on the msi-x capability in the remap case,
1584 * share the legacy interrupt across ahci and remapped devices.
1586 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1589 static int ahci_get_irq_vector(struct ata_host *host, int port)
1591 return pci_irq_vector(to_pci_dev(host->dev), port);
1594 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1595 struct ahci_host_priv *hpriv)
1599 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1603 * If number of MSIs is less than number of ports then Sharing Last
1604 * Message mode could be enforced. In this case assume that advantage
1605 * of multipe MSIs is negated and use single MSI mode instead.
1608 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1609 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1611 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1612 hpriv->get_irq_vector = ahci_get_irq_vector;
1613 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1618 * Fallback to single MSI mode if the controller
1619 * enforced MRSM mode.
1622 "ahci: MRSM is on, fallback to single MSI\n");
1623 pci_free_irq_vectors(pdev);
1628 * If the host is not capable of supporting per-port vectors, fall
1629 * back to single MSI before finally attempting single MSI-X.
1631 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1634 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1637 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1638 struct ahci_host_priv *hpriv)
1640 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1643 /* Ignore processing for non mobile platforms */
1644 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1647 /* user modified policy via module param */
1648 if (mobile_lpm_policy != -1) {
1649 policy = mobile_lpm_policy;
1654 if (policy > ATA_LPM_MED_POWER &&
1655 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1656 if (hpriv->cap & HOST_CAP_PART)
1657 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1658 else if (hpriv->cap & HOST_CAP_SSC)
1659 policy = ATA_LPM_MIN_POWER;
1664 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1665 ap->target_lpm_policy = policy;
1668 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1670 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1674 * Only apply the 6-port PCS quirk for known legacy platforms.
1676 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1679 /* Skip applying the quirk on Denverton and beyond */
1680 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1684 * port_map is determined from PORTS_IMPL PCI register which is
1685 * implemented as write or write-once register. If the register
1686 * isn't programmed, ahci automatically generates it from number
1687 * of ports, which is good enough for PCS programming. It is
1688 * otherwise expected that platform firmware enables the ports
1689 * before the OS boots.
1691 pci_read_config_word(pdev, PCS_6, &tmp16);
1692 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1693 tmp16 |= hpriv->port_map;
1694 pci_write_config_word(pdev, PCS_6, tmp16);
1698 static ssize_t remapped_nvme_show(struct device *dev,
1699 struct device_attribute *attr,
1702 struct ata_host *host = dev_get_drvdata(dev);
1703 struct ahci_host_priv *hpriv = host->private_data;
1705 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1708 static DEVICE_ATTR_RO(remapped_nvme);
1710 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1712 unsigned int board_id = ent->driver_data;
1713 struct ata_port_info pi = ahci_port_info[board_id];
1714 const struct ata_port_info *ppi[] = { &pi, NULL };
1715 struct device *dev = &pdev->dev;
1716 struct ahci_host_priv *hpriv;
1717 struct ata_host *host;
1719 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1723 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1725 ata_print_version_once(&pdev->dev, DRV_VERSION);
1727 /* The AHCI driver can only drive the SATA ports, the PATA driver
1728 can drive them all so if both drivers are selected make sure
1729 AHCI stays out of the way */
1730 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1733 /* Apple BIOS on MCP89 prevents us using AHCI */
1734 if (is_mcp89_apple(pdev))
1735 ahci_mcp89_apple_enable(pdev);
1737 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1738 * At the moment, we can only use the AHCI mode. Let the users know
1739 * that for SAS drives they're out of luck.
1741 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1742 dev_info(&pdev->dev,
1743 "PDC42819 can only drive SATA devices with this driver\n");
1745 /* Some devices use non-standard BARs */
1746 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1747 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1748 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1749 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1750 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1751 if (pdev->device == 0xa01c)
1752 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1753 if (pdev->device == 0xa084)
1754 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1755 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1756 if (pdev->device == 0x7a08)
1757 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1760 /* acquire resources */
1761 rc = pcim_enable_device(pdev);
1765 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1766 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1769 /* ICH6s share the same PCI ID for both piix and ahci
1770 * modes. Enabling ahci mode while MAP indicates
1771 * combined mode is a bad idea. Yield to ata_piix.
1773 pci_read_config_byte(pdev, ICH_MAP, &map);
1775 dev_info(&pdev->dev,
1776 "controller is in combined mode, can't enable AHCI mode\n");
1781 /* AHCI controllers often implement SFF compatible interface.
1782 * Grab all PCI BARs just in case.
1784 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1786 pcim_pin_device(pdev);
1790 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1793 hpriv->flags |= (unsigned long)pi.private_data;
1795 /* MCP65 revision A1 and A2 can't do MSI */
1796 if (board_id == board_ahci_mcp65 &&
1797 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1798 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1800 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1801 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1802 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1804 /* only some SB600s can do 64bit DMA */
1805 if (ahci_sb600_enable_64bit(pdev))
1806 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1808 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1810 /* detect remapped nvme devices */
1811 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1813 sysfs_add_file_to_group(&pdev->dev.kobj,
1814 &dev_attr_remapped_nvme.attr,
1817 /* must set flag prior to save config in order to take effect */
1818 if (ahci_broken_devslp(pdev))
1819 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1822 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1823 pdev->device == 0xa235 &&
1824 pdev->revision < 0x30)
1825 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1827 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1828 hpriv->irq_handler = ahci_thunderx_irq_handler;
1831 /* save initial config */
1832 ahci_pci_save_initial_config(pdev, hpriv);
1835 if (hpriv->cap & HOST_CAP_NCQ) {
1836 pi.flags |= ATA_FLAG_NCQ;
1838 * Auto-activate optimization is supposed to be
1839 * supported on all AHCI controllers indicating NCQ
1840 * capability, but it seems to be broken on some
1841 * chipsets including NVIDIAs.
1843 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1844 pi.flags |= ATA_FLAG_FPDMA_AA;
1847 * All AHCI controllers should be forward-compatible
1848 * with the new auxiliary field. This code should be
1849 * conditionalized if any buggy AHCI controllers are
1852 pi.flags |= ATA_FLAG_FPDMA_AUX;
1855 if (hpriv->cap & HOST_CAP_PMP)
1856 pi.flags |= ATA_FLAG_PMP;
1858 ahci_set_em_messages(hpriv, &pi);
1860 if (ahci_broken_system_poweroff(pdev)) {
1861 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1862 dev_info(&pdev->dev,
1863 "quirky BIOS, skipping spindown on poweroff\n");
1866 if (ahci_broken_lpm(pdev)) {
1867 pi.flags |= ATA_FLAG_NO_LPM;
1868 dev_warn(&pdev->dev,
1869 "BIOS update required for Link Power Management support\n");
1872 if (ahci_broken_suspend(pdev)) {
1873 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1874 dev_warn(&pdev->dev,
1875 "BIOS update required for suspend/resume\n");
1878 if (ahci_broken_online(pdev)) {
1879 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1880 dev_info(&pdev->dev,
1881 "online status unreliable, applying workaround\n");
1885 /* Acer SA5-271 workaround modifies private_data */
1886 acer_sa5_271_workaround(hpriv, pdev);
1888 /* CAP.NP sometimes indicate the index of the last enabled
1889 * port, at other times, that of the last possible port, so
1890 * determining the maximum port number requires looking at
1891 * both CAP.NP and port_map.
1893 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1895 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1898 host->private_data = hpriv;
1900 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1901 /* legacy intx interrupts */
1904 hpriv->irq = pci_irq_vector(pdev, 0);
1906 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1907 host->flags |= ATA_HOST_PARALLEL_SCAN;
1909 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1911 if (!(hpriv->cap & HOST_CAP_PART))
1912 host->flags |= ATA_HOST_NO_PART;
1914 if (!(hpriv->cap & HOST_CAP_SSC))
1915 host->flags |= ATA_HOST_NO_SSC;
1917 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1918 host->flags |= ATA_HOST_NO_DEVSLP;
1920 if (pi.flags & ATA_FLAG_EM)
1921 ahci_reset_em(host);
1923 for (i = 0; i < host->n_ports; i++) {
1924 struct ata_port *ap = host->ports[i];
1926 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1927 ata_port_pbar_desc(ap, ahci_pci_bar,
1928 0x100 + ap->port_no * 0x80, "port");
1930 /* set enclosure management message type */
1931 if (ap->flags & ATA_FLAG_EM)
1932 ap->em_message_type = hpriv->em_msg_type;
1934 ahci_update_initial_lpm_policy(ap, hpriv);
1936 /* disabled/not-implemented port */
1937 if (!(hpriv->port_map & (1 << i)))
1938 ap->ops = &ata_dummy_port_ops;
1941 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1942 ahci_p5wdh_workaround(host);
1944 /* apply gtf filter quirk */
1945 ahci_gtf_filter_workaround(host);
1947 /* initialize adapter */
1948 rc = ahci_configure_dma_masks(pdev, hpriv);
1952 rc = ahci_pci_reset_controller(host);
1956 ahci_pci_init_controller(host);
1957 ahci_pci_print_info(host);
1959 pci_set_master(pdev);
1961 rc = ahci_host_activate(host, &ahci_sht);
1965 pm_runtime_put_noidle(&pdev->dev);
1969 static void ahci_shutdown_one(struct pci_dev *pdev)
1971 ata_pci_shutdown_one(pdev);
1974 static void ahci_remove_one(struct pci_dev *pdev)
1976 sysfs_remove_file_from_group(&pdev->dev.kobj,
1977 &dev_attr_remapped_nvme.attr,
1979 pm_runtime_get_noresume(&pdev->dev);
1980 ata_pci_remove_one(pdev);
1983 module_pci_driver(ahci_pci_driver);
1985 MODULE_AUTHOR("Jeff Garzik");
1986 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1987 MODULE_LICENSE("GPL");
1988 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1989 MODULE_VERSION(DRV_VERSION);