2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
65 /* board IDs by feature in alphabetical order */
74 /* board IDs for specific chipsets in alphabetical order */
81 board_ahci_sb700, /* for SB700 and SB800 */
85 * board IDs for Intel chipsets that support more than 6 ports
86 * *and* end up needing the PCS quirk.
91 board_ahci_mcp_linux = board_ahci_mcp65,
92 board_ahci_mcp67 = board_ahci_mcp65,
93 board_ahci_mcp73 = board_ahci_mcp65,
94 board_ahci_mcp79 = board_ahci_mcp77,
97 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
98 static void ahci_remove_one(struct pci_dev *dev);
99 static void ahci_shutdown_one(struct pci_dev *dev);
100 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
101 unsigned long deadline);
102 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
103 unsigned long deadline);
104 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
105 static bool is_mcp89_apple(struct pci_dev *pdev);
106 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
107 unsigned long deadline);
109 static int ahci_pci_device_runtime_suspend(struct device *dev);
110 static int ahci_pci_device_runtime_resume(struct device *dev);
111 #ifdef CONFIG_PM_SLEEP
112 static int ahci_pci_device_suspend(struct device *dev);
113 static int ahci_pci_device_resume(struct device *dev);
115 #endif /* CONFIG_PM */
117 static struct scsi_host_template ahci_sht = {
121 static struct ata_port_operations ahci_vt8251_ops = {
122 .inherits = &ahci_ops,
123 .hardreset = ahci_vt8251_hardreset,
126 static struct ata_port_operations ahci_p5wdh_ops = {
127 .inherits = &ahci_ops,
128 .hardreset = ahci_p5wdh_hardreset,
131 static struct ata_port_operations ahci_avn_ops = {
132 .inherits = &ahci_ops,
133 .hardreset = ahci_avn_hardreset,
136 static const struct ata_port_info ahci_port_info[] = {
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
144 [board_ahci_ign_iferr] = {
145 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
151 [board_ahci_mobile] = {
152 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
158 [board_ahci_nomsi] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
165 [board_ahci_noncq] = {
166 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
172 [board_ahci_nosntf] = {
173 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
174 .flags = AHCI_FLAG_COMMON,
175 .pio_mask = ATA_PIO4,
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &ahci_ops,
179 [board_ahci_yes_fbs] = {
180 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_avn_ops,
193 [board_ahci_mcp65] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
196 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
201 [board_ahci_mcp77] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
208 [board_ahci_mcp89] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
210 .flags = AHCI_FLAG_COMMON,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_ops,
216 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
217 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
218 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_ops,
223 [board_ahci_sb600] = {
224 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
225 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
226 AHCI_HFLAG_32BIT_ONLY),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
232 [board_ahci_sb700] = { /* for SB700 and SB800 */
233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_pmp_retry_srst_ops,
239 [board_ahci_vt8251] = {
240 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
241 .flags = AHCI_FLAG_COMMON,
242 .pio_mask = ATA_PIO4,
243 .udma_mask = ATA_UDMA6,
244 .port_ops = &ahci_vt8251_ops,
246 [board_ahci_pcs7] = {
247 .flags = AHCI_FLAG_COMMON,
248 .pio_mask = ATA_PIO4,
249 .udma_mask = ATA_UDMA6,
250 .port_ops = &ahci_ops,
254 static const struct pci_device_id ahci_pci_tbl[] = {
256 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
257 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
258 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
259 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
260 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
261 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
262 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
263 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
264 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
265 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
266 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
267 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
268 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
269 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
270 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
271 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
272 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
273 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
274 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
275 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
277 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
278 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
279 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
280 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
281 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
283 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
284 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
285 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
286 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
287 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
288 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
289 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
290 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
291 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
292 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
293 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
294 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
295 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
317 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
318 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
319 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
320 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
321 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
322 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
323 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
324 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
325 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
326 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
327 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
328 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
329 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
330 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
331 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
332 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
333 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
334 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
335 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
336 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
337 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
338 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
339 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
340 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
341 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
342 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
343 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
344 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
345 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
346 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
347 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
351 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
352 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
353 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
354 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
355 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
368 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
370 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
372 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
374 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
376 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
377 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
378 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
379 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
381 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
382 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
383 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
384 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
385 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
386 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
387 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
389 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
390 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
391 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
392 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
393 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
394 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
395 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
396 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
397 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
398 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
399 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
400 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
401 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
402 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
404 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
406 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
408 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
411 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
412 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
413 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
415 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
416 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
417 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
419 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
420 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
421 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
422 /* JMicron 362B and 362C have an AHCI function with IDE class code */
423 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
424 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
425 /* May need to update quirk_jmicron_async_suspend() for additions */
428 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
429 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
430 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
437 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
438 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
439 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
440 /* AMD is using RAID class only for ahci controllers */
441 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
442 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
445 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
446 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
449 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
470 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
471 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
472 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
473 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
474 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
522 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
523 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
524 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
525 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
526 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
536 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
537 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
539 /* ST Microelectronics */
540 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
543 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
544 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
545 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
546 .class = PCI_CLASS_STORAGE_SATA_AHCI,
547 .class_mask = 0xffffff,
548 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
550 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
551 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
552 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
553 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
555 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
556 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
557 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
558 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
559 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
561 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
562 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
563 .driver_data = board_ahci_yes_fbs },
564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
565 .driver_data = board_ahci_yes_fbs },
566 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
567 .driver_data = board_ahci_yes_fbs },
568 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
569 .driver_data = board_ahci_yes_fbs },
570 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
571 .driver_data = board_ahci_yes_fbs },
572 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
573 .driver_data = board_ahci_yes_fbs },
576 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
577 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
580 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
581 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
582 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
583 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
584 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
585 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
588 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
589 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
591 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
592 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
595 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
597 /* Generic, PCI class code for AHCI */
598 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
599 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
601 { } /* terminate list */
604 static const struct dev_pm_ops ahci_pci_pm_ops = {
605 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
606 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
607 ahci_pci_device_runtime_resume, NULL)
610 static struct pci_driver ahci_pci_driver = {
612 .id_table = ahci_pci_tbl,
613 .probe = ahci_init_one,
614 .remove = ahci_remove_one,
615 .shutdown = ahci_shutdown_one,
617 .pm = &ahci_pci_pm_ops,
621 #if IS_ENABLED(CONFIG_PATA_MARVELL)
622 static int marvell_enable;
624 static int marvell_enable = 1;
626 module_param(marvell_enable, int, 0644);
627 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
629 static int mobile_lpm_policy = -1;
630 module_param(mobile_lpm_policy, int, 0644);
631 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
633 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
634 struct ahci_host_priv *hpriv)
636 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
637 dev_info(&pdev->dev, "JMB361 has only one port\n");
638 hpriv->force_port_map = 1;
642 * Temporary Marvell 6145 hack: PATA port presence
643 * is asserted through the standard AHCI port
644 * presence register, as bit 4 (counting from 0)
646 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
647 if (pdev->device == 0x6121)
648 hpriv->mask_port_map = 0x3;
650 hpriv->mask_port_map = 0xf;
652 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
655 ahci_save_initial_config(&pdev->dev, hpriv);
658 static void ahci_pci_init_controller(struct ata_host *host)
660 struct ahci_host_priv *hpriv = host->private_data;
661 struct pci_dev *pdev = to_pci_dev(host->dev);
662 void __iomem *port_mmio;
666 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
667 if (pdev->device == 0x6121)
671 port_mmio = __ahci_port_base(host, mv);
673 writel(0, port_mmio + PORT_IRQ_MASK);
676 tmp = readl(port_mmio + PORT_IRQ_STAT);
677 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
679 writel(tmp, port_mmio + PORT_IRQ_STAT);
682 ahci_init_controller(host);
685 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
686 unsigned long deadline)
688 struct ata_port *ap = link->ap;
689 struct ahci_host_priv *hpriv = ap->host->private_data;
695 hpriv->stop_engine(ap);
697 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
698 deadline, &online, NULL);
700 hpriv->start_engine(ap);
702 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
704 /* vt8251 doesn't clear BSY on signature FIS reception,
705 * request follow-up softreset.
707 return online ? -EAGAIN : rc;
710 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
711 unsigned long deadline)
713 struct ata_port *ap = link->ap;
714 struct ahci_port_priv *pp = ap->private_data;
715 struct ahci_host_priv *hpriv = ap->host->private_data;
716 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
717 struct ata_taskfile tf;
721 hpriv->stop_engine(ap);
723 /* clear D2H reception area to properly wait for D2H FIS */
724 ata_tf_init(link->device, &tf);
725 tf.command = ATA_BUSY;
726 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
728 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
729 deadline, &online, NULL);
731 hpriv->start_engine(ap);
733 /* The pseudo configuration device on SIMG4726 attached to
734 * ASUS P5W-DH Deluxe doesn't send signature FIS after
735 * hardreset if no device is attached to the first downstream
736 * port && the pseudo device locks up on SRST w/ PMP==0. To
737 * work around this, wait for !BSY only briefly. If BSY isn't
738 * cleared, perform CLO and proceed to IDENTIFY (achieved by
739 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
741 * Wait for two seconds. Devices attached to downstream port
742 * which can't process the following IDENTIFY after this will
743 * have to be reset again. For most cases, this should
744 * suffice while making probing snappish enough.
747 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
750 ahci_kick_engine(ap);
756 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
758 * It has been observed with some SSDs that the timing of events in the
759 * link synchronization phase can leave the port in a state that can not
760 * be recovered by a SATA-hard-reset alone. The failing signature is
761 * SStatus.DET stuck at 1 ("Device presence detected but Phy
762 * communication not established"). It was found that unloading and
763 * reloading the driver when this problem occurs allows the drive
764 * connection to be recovered (DET advanced to 0x3). The critical
765 * component of reloading the driver is that the port state machines are
766 * reset by bouncing "port enable" in the AHCI PCS configuration
767 * register. So, reproduce that effect by bouncing a port whenever we
768 * see DET==1 after a reset.
770 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
771 unsigned long deadline)
773 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
774 struct ata_port *ap = link->ap;
775 struct ahci_port_priv *pp = ap->private_data;
776 struct ahci_host_priv *hpriv = ap->host->private_data;
777 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
778 unsigned long tmo = deadline - jiffies;
779 struct ata_taskfile tf;
785 hpriv->stop_engine(ap);
787 for (i = 0; i < 2; i++) {
790 int port = ap->port_no;
791 struct ata_host *host = ap->host;
792 struct pci_dev *pdev = to_pci_dev(host->dev);
794 /* clear D2H reception area to properly wait for D2H FIS */
795 ata_tf_init(link->device, &tf);
796 tf.command = ATA_BUSY;
797 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
799 rc = sata_link_hardreset(link, timing, deadline, &online,
802 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
803 (sstatus & 0xf) != 1)
806 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
809 pci_read_config_word(pdev, 0x92, &val);
811 pci_write_config_word(pdev, 0x92, val);
812 ata_msleep(ap, 1000);
814 pci_write_config_word(pdev, 0x92, val);
818 hpriv->start_engine(ap);
821 *class = ahci_dev_classify(ap);
823 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
829 static void ahci_pci_disable_interrupts(struct ata_host *host)
831 struct ahci_host_priv *hpriv = host->private_data;
832 void __iomem *mmio = hpriv->mmio;
835 /* AHCI spec rev1.1 section 8.3.3:
836 * Software must disable interrupts prior to requesting a
837 * transition of the HBA to D3 state.
839 ctl = readl(mmio + HOST_CTL);
841 writel(ctl, mmio + HOST_CTL);
842 readl(mmio + HOST_CTL); /* flush */
845 static int ahci_pci_device_runtime_suspend(struct device *dev)
847 struct pci_dev *pdev = to_pci_dev(dev);
848 struct ata_host *host = pci_get_drvdata(pdev);
850 ahci_pci_disable_interrupts(host);
854 static int ahci_pci_device_runtime_resume(struct device *dev)
856 struct pci_dev *pdev = to_pci_dev(dev);
857 struct ata_host *host = pci_get_drvdata(pdev);
860 rc = ahci_reset_controller(host);
863 ahci_pci_init_controller(host);
867 #ifdef CONFIG_PM_SLEEP
868 static int ahci_pci_device_suspend(struct device *dev)
870 struct pci_dev *pdev = to_pci_dev(dev);
871 struct ata_host *host = pci_get_drvdata(pdev);
872 struct ahci_host_priv *hpriv = host->private_data;
874 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
876 "BIOS update required for suspend/resume\n");
880 ahci_pci_disable_interrupts(host);
881 return ata_host_suspend(host, PMSG_SUSPEND);
884 static int ahci_pci_device_resume(struct device *dev)
886 struct pci_dev *pdev = to_pci_dev(dev);
887 struct ata_host *host = pci_get_drvdata(pdev);
890 /* Apple BIOS helpfully mangles the registers on resume */
891 if (is_mcp89_apple(pdev))
892 ahci_mcp89_apple_enable(pdev);
894 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
895 rc = ahci_reset_controller(host);
899 ahci_pci_init_controller(host);
902 ata_host_resume(host);
908 #endif /* CONFIG_PM */
910 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
915 * If the device fixup already set the dma_mask to some non-standard
916 * value, don't extend it here. This happens on STA2X11, for example.
918 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
922 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
923 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
925 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
928 "64-bit DMA enable failed\n");
933 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
935 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
938 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
941 "32-bit consistent DMA enable failed\n");
948 static void ahci_pci_print_info(struct ata_host *host)
950 struct pci_dev *pdev = to_pci_dev(host->dev);
954 pci_read_config_word(pdev, 0x0a, &cc);
955 if (cc == PCI_CLASS_STORAGE_IDE)
957 else if (cc == PCI_CLASS_STORAGE_SATA)
959 else if (cc == PCI_CLASS_STORAGE_RAID)
964 ahci_print_info(host, scc_s);
967 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
968 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
969 * support PMP and the 4726 either directly exports the device
970 * attached to the first downstream port or acts as a hardware storage
971 * controller and emulate a single ATA device (can be RAID 0/1 or some
972 * other configuration).
974 * When there's no device attached to the first downstream port of the
975 * 4726, "Config Disk" appears, which is a pseudo ATA device to
976 * configure the 4726. However, ATA emulation of the device is very
977 * lame. It doesn't send signature D2H Reg FIS after the initial
978 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
980 * The following function works around the problem by always using
981 * hardreset on the port and not depending on receiving signature FIS
982 * afterward. If signature FIS isn't received soon, ATA class is
983 * assumed without follow-up softreset.
985 static void ahci_p5wdh_workaround(struct ata_host *host)
987 static const struct dmi_system_id sysids[] = {
989 .ident = "P5W DH Deluxe",
991 DMI_MATCH(DMI_SYS_VENDOR,
992 "ASUSTEK COMPUTER INC"),
993 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
998 struct pci_dev *pdev = to_pci_dev(host->dev);
1000 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1001 dmi_check_system(sysids)) {
1002 struct ata_port *ap = host->ports[1];
1004 dev_info(&pdev->dev,
1005 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1007 ap->ops = &ahci_p5wdh_ops;
1008 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1013 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1014 * booting in BIOS compatibility mode. We restore the registers but not ID.
1016 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1020 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1022 pci_read_config_dword(pdev, 0xf8, &val);
1024 /* the following changes the device ID, but appears not to affect function */
1025 /* val = (val & ~0xf0000000) | 0x80000000; */
1026 pci_write_config_dword(pdev, 0xf8, val);
1028 pci_read_config_dword(pdev, 0x54c, &val);
1030 pci_write_config_dword(pdev, 0x54c, val);
1032 pci_read_config_dword(pdev, 0x4a4, &val);
1035 pci_write_config_dword(pdev, 0x4a4, val);
1037 pci_read_config_dword(pdev, 0x54c, &val);
1039 pci_write_config_dword(pdev, 0x54c, val);
1041 pci_read_config_dword(pdev, 0xf8, &val);
1042 val &= ~(1 << 0x1b);
1043 pci_write_config_dword(pdev, 0xf8, val);
1046 static bool is_mcp89_apple(struct pci_dev *pdev)
1048 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1049 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1050 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1051 pdev->subsystem_device == 0xcb89;
1054 /* only some SB600 ahci controllers can do 64bit DMA */
1055 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1057 static const struct dmi_system_id sysids[] = {
1059 * The oldest version known to be broken is 0901 and
1060 * working is 1501 which was released on 2007-10-26.
1061 * Enable 64bit DMA on 1501 and anything newer.
1063 * Please read bko#9412 for more info.
1066 .ident = "ASUS M2A-VM",
1068 DMI_MATCH(DMI_BOARD_VENDOR,
1069 "ASUSTeK Computer INC."),
1070 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1072 .driver_data = "20071026", /* yyyymmdd */
1075 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1076 * support 64bit DMA.
1078 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1079 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1080 * This spelling mistake was fixed in BIOS version 1.5, so
1081 * 1.5 and later have the Manufacturer as
1082 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1083 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1085 * BIOS versions earlier than 1.9 had a Board Product Name
1086 * DMI field of "MS-7376". This was changed to be
1087 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1088 * match on DMI_BOARD_NAME of "MS-7376".
1091 .ident = "MSI K9A2 Platinum",
1093 DMI_MATCH(DMI_BOARD_VENDOR,
1094 "MICRO-STAR INTER"),
1095 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1099 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1102 * This board also had the typo mentioned above in the
1103 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1104 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1107 .ident = "MSI K9AGM2",
1109 DMI_MATCH(DMI_BOARD_VENDOR,
1110 "MICRO-STAR INTER"),
1111 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1115 * All BIOS versions for the Asus M3A support 64bit DMA.
1116 * (all release versions from 0301 to 1206 were tested)
1119 .ident = "ASUS M3A",
1121 DMI_MATCH(DMI_BOARD_VENDOR,
1122 "ASUSTeK Computer INC."),
1123 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1128 const struct dmi_system_id *match;
1129 int year, month, date;
1132 match = dmi_first_match(sysids);
1133 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1137 if (!match->driver_data)
1140 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1141 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1143 if (strcmp(buf, match->driver_data) >= 0)
1146 dev_warn(&pdev->dev,
1147 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1153 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1157 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1159 static const struct dmi_system_id broken_systems[] = {
1161 .ident = "HP Compaq nx6310",
1163 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1164 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1166 /* PCI slot number of the controller */
1167 .driver_data = (void *)0x1FUL,
1170 .ident = "HP Compaq 6720s",
1172 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1173 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1175 /* PCI slot number of the controller */
1176 .driver_data = (void *)0x1FUL,
1179 { } /* terminate list */
1181 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1184 unsigned long slot = (unsigned long)dmi->driver_data;
1185 /* apply the quirk only to on-board controllers */
1186 return slot == PCI_SLOT(pdev->devfn);
1192 static bool ahci_broken_suspend(struct pci_dev *pdev)
1194 static const struct dmi_system_id sysids[] = {
1196 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1197 * to the harddisk doesn't become online after
1198 * resuming from STR. Warn and fail suspend.
1200 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1202 * Use dates instead of versions to match as HP is
1203 * apparently recycling both product and version
1206 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1211 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1212 DMI_MATCH(DMI_PRODUCT_NAME,
1213 "HP Pavilion dv4 Notebook PC"),
1215 .driver_data = "20090105", /* F.30 */
1220 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1221 DMI_MATCH(DMI_PRODUCT_NAME,
1222 "HP Pavilion dv5 Notebook PC"),
1224 .driver_data = "20090506", /* F.16 */
1229 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1230 DMI_MATCH(DMI_PRODUCT_NAME,
1231 "HP Pavilion dv6 Notebook PC"),
1233 .driver_data = "20090423", /* F.21 */
1238 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1239 DMI_MATCH(DMI_PRODUCT_NAME,
1240 "HP HDX18 Notebook PC"),
1242 .driver_data = "20090430", /* F.23 */
1245 * Acer eMachines G725 has the same problem. BIOS
1246 * V1.03 is known to be broken. V3.04 is known to
1247 * work. Between, there are V1.06, V2.06 and V3.03
1248 * that we don't have much idea about. For now,
1249 * blacklist anything older than V3.04.
1251 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1256 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1257 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1259 .driver_data = "20091216", /* V3.04 */
1261 { } /* terminate list */
1263 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1264 int year, month, date;
1267 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1270 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1271 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1273 return strcmp(buf, dmi->driver_data) < 0;
1276 static bool ahci_broken_lpm(struct pci_dev *pdev)
1278 static const struct dmi_system_id sysids[] = {
1279 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1282 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1283 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1285 .driver_data = "20180406", /* 1.31 */
1289 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1290 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1292 .driver_data = "20180420", /* 1.28 */
1296 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1297 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1299 .driver_data = "20180315", /* 1.33 */
1303 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1304 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1307 * Note date based on release notes, 2.35 has been
1308 * reported to be good, but I've been unable to get
1309 * a hold of the reporter to get the DMI BIOS date.
1312 .driver_data = "20180310", /* 2.35 */
1314 { } /* terminate list */
1316 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1317 int year, month, date;
1323 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1324 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1326 return strcmp(buf, dmi->driver_data) < 0;
1329 static bool ahci_broken_online(struct pci_dev *pdev)
1331 #define ENCODE_BUSDEVFN(bus, slot, func) \
1332 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1333 static const struct dmi_system_id sysids[] = {
1335 * There are several gigabyte boards which use
1336 * SIMG5723s configured as hardware RAID. Certain
1337 * 5723 firmware revisions shipped there keep the link
1338 * online but fail to answer properly to SRST or
1339 * IDENTIFY when no device is attached downstream
1340 * causing libata to retry quite a few times leading
1341 * to excessive detection delay.
1343 * As these firmwares respond to the second reset try
1344 * with invalid device signature, considering unknown
1345 * sig as offline works around the problem acceptably.
1348 .ident = "EP45-DQ6",
1350 DMI_MATCH(DMI_BOARD_VENDOR,
1351 "Gigabyte Technology Co., Ltd."),
1352 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1354 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1357 .ident = "EP45-DS5",
1359 DMI_MATCH(DMI_BOARD_VENDOR,
1360 "Gigabyte Technology Co., Ltd."),
1361 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1363 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1365 { } /* terminate list */
1367 #undef ENCODE_BUSDEVFN
1368 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1374 val = (unsigned long)dmi->driver_data;
1376 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1379 static bool ahci_broken_devslp(struct pci_dev *pdev)
1381 /* device with broken DEVSLP but still showing SDS capability */
1382 static const struct pci_device_id ids[] = {
1383 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1387 return pci_match_id(ids, pdev);
1390 #ifdef CONFIG_ATA_ACPI
1391 static void ahci_gtf_filter_workaround(struct ata_host *host)
1393 static const struct dmi_system_id sysids[] = {
1395 * Aspire 3810T issues a bunch of SATA enable commands
1396 * via _GTF including an invalid one and one which is
1397 * rejected by the device. Among the successful ones
1398 * is FPDMA non-zero offset enable which when enabled
1399 * only on the drive side leads to NCQ command
1400 * failures. Filter it out.
1403 .ident = "Aspire 3810T",
1405 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1406 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1408 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1412 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1413 unsigned int filter;
1419 filter = (unsigned long)dmi->driver_data;
1420 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1421 filter, dmi->ident);
1423 for (i = 0; i < host->n_ports; i++) {
1424 struct ata_port *ap = host->ports[i];
1425 struct ata_link *link;
1426 struct ata_device *dev;
1428 ata_for_each_link(link, ap, EDGE)
1429 ata_for_each_dev(dev, link, ALL)
1430 dev->gtf_filter |= filter;
1434 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1439 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1440 * as DUMMY, or detected but eventually get a "link down" and never get up
1441 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1442 * port_map may hold a value of 0x00.
1444 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1445 * and can significantly reduce the occurrence of the problem.
1447 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1449 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1450 struct pci_dev *pdev)
1452 static const struct dmi_system_id sysids[] = {
1454 .ident = "Acer Switch Alpha 12",
1456 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1457 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1463 if (dmi_check_system(sysids)) {
1464 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1465 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1466 hpriv->port_map = 0x7;
1467 hpriv->cap = 0xC734FF02;
1474 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1475 * Workaround is to make sure all pending IRQs are served before leaving
1478 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1480 struct ata_host *host = dev_instance;
1481 struct ahci_host_priv *hpriv;
1482 unsigned int rc = 0;
1484 u32 irq_stat, irq_masked;
1485 unsigned int handled = 1;
1488 hpriv = host->private_data;
1490 irq_stat = readl(mmio + HOST_IRQ_STAT);
1495 irq_masked = irq_stat & hpriv->port_map;
1496 spin_lock(&host->lock);
1497 rc = ahci_handle_port_intr(host, irq_masked);
1500 writel(irq_stat, mmio + HOST_IRQ_STAT);
1501 irq_stat = readl(mmio + HOST_IRQ_STAT);
1502 spin_unlock(&host->lock);
1506 return IRQ_RETVAL(handled);
1510 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1511 struct ahci_host_priv *hpriv)
1517 * Check if this device might have remapped nvme devices.
1519 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1520 pci_resource_len(pdev, bar) < SZ_512K ||
1521 bar != AHCI_PCI_BAR_STANDARD ||
1522 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1525 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1526 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1527 if ((cap & (1 << i)) == 0)
1529 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1530 != PCI_CLASS_STORAGE_EXPRESS)
1533 /* We've found a remapped device */
1540 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1541 dev_warn(&pdev->dev,
1542 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1545 * Don't rely on the msi-x capability in the remap case,
1546 * share the legacy interrupt across ahci and remapped devices.
1548 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1551 static int ahci_get_irq_vector(struct ata_host *host, int port)
1553 return pci_irq_vector(to_pci_dev(host->dev), port);
1556 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1557 struct ahci_host_priv *hpriv)
1561 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1565 * If number of MSIs is less than number of ports then Sharing Last
1566 * Message mode could be enforced. In this case assume that advantage
1567 * of multipe MSIs is negated and use single MSI mode instead.
1570 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1571 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1573 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1574 hpriv->get_irq_vector = ahci_get_irq_vector;
1575 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1580 * Fallback to single MSI mode if the controller
1581 * enforced MRSM mode.
1584 "ahci: MRSM is on, fallback to single MSI\n");
1585 pci_free_irq_vectors(pdev);
1590 * If the host is not capable of supporting per-port vectors, fall
1591 * back to single MSI before finally attempting single MSI-X.
1593 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1596 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1599 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1600 struct ahci_host_priv *hpriv)
1602 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1605 /* Ignore processing for non mobile platforms */
1606 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1609 /* user modified policy via module param */
1610 if (mobile_lpm_policy != -1) {
1611 policy = mobile_lpm_policy;
1616 if (policy > ATA_LPM_MED_POWER &&
1617 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1618 if (hpriv->cap & HOST_CAP_PART)
1619 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1620 else if (hpriv->cap & HOST_CAP_SSC)
1621 policy = ATA_LPM_MIN_POWER;
1626 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1627 ap->target_lpm_policy = policy;
1630 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1632 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1636 * Only apply the 6-port PCS quirk for known legacy platforms.
1638 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1641 /* Skip applying the quirk on Denverton and beyond */
1642 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1646 * port_map is determined from PORTS_IMPL PCI register which is
1647 * implemented as write or write-once register. If the register
1648 * isn't programmed, ahci automatically generates it from number
1649 * of ports, which is good enough for PCS programming. It is
1650 * otherwise expected that platform firmware enables the ports
1651 * before the OS boots.
1653 pci_read_config_word(pdev, PCS_6, &tmp16);
1654 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1655 tmp16 |= hpriv->port_map;
1656 pci_write_config_word(pdev, PCS_6, tmp16);
1660 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1662 unsigned int board_id = ent->driver_data;
1663 struct ata_port_info pi = ahci_port_info[board_id];
1664 const struct ata_port_info *ppi[] = { &pi, NULL };
1665 struct device *dev = &pdev->dev;
1666 struct ahci_host_priv *hpriv;
1667 struct ata_host *host;
1669 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1673 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1675 ata_print_version_once(&pdev->dev, DRV_VERSION);
1677 /* The AHCI driver can only drive the SATA ports, the PATA driver
1678 can drive them all so if both drivers are selected make sure
1679 AHCI stays out of the way */
1680 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1683 /* Apple BIOS on MCP89 prevents us using AHCI */
1684 if (is_mcp89_apple(pdev))
1685 ahci_mcp89_apple_enable(pdev);
1687 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1688 * At the moment, we can only use the AHCI mode. Let the users know
1689 * that for SAS drives they're out of luck.
1691 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1692 dev_info(&pdev->dev,
1693 "PDC42819 can only drive SATA devices with this driver\n");
1695 /* Some devices use non-standard BARs */
1696 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1697 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1698 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1699 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1700 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1701 if (pdev->device == 0xa01c)
1702 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1703 if (pdev->device == 0xa084)
1704 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1707 /* acquire resources */
1708 rc = pcim_enable_device(pdev);
1712 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1713 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1716 /* ICH6s share the same PCI ID for both piix and ahci
1717 * modes. Enabling ahci mode while MAP indicates
1718 * combined mode is a bad idea. Yield to ata_piix.
1720 pci_read_config_byte(pdev, ICH_MAP, &map);
1722 dev_info(&pdev->dev,
1723 "controller is in combined mode, can't enable AHCI mode\n");
1728 /* AHCI controllers often implement SFF compatible interface.
1729 * Grab all PCI BARs just in case.
1731 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1733 pcim_pin_device(pdev);
1737 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1740 hpriv->flags |= (unsigned long)pi.private_data;
1742 /* MCP65 revision A1 and A2 can't do MSI */
1743 if (board_id == board_ahci_mcp65 &&
1744 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1745 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1747 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1748 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1749 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1751 /* only some SB600s can do 64bit DMA */
1752 if (ahci_sb600_enable_64bit(pdev))
1753 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1755 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1757 /* detect remapped nvme devices */
1758 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1760 /* must set flag prior to save config in order to take effect */
1761 if (ahci_broken_devslp(pdev))
1762 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1765 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1766 hpriv->irq_handler = ahci_thunderx_irq_handler;
1769 /* save initial config */
1770 ahci_pci_save_initial_config(pdev, hpriv);
1773 * If platform firmware failed to enable ports, try to enable
1776 ahci_intel_pcs_quirk(pdev, hpriv);
1779 if (hpriv->cap & HOST_CAP_NCQ) {
1780 pi.flags |= ATA_FLAG_NCQ;
1782 * Auto-activate optimization is supposed to be
1783 * supported on all AHCI controllers indicating NCQ
1784 * capability, but it seems to be broken on some
1785 * chipsets including NVIDIAs.
1787 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1788 pi.flags |= ATA_FLAG_FPDMA_AA;
1791 * All AHCI controllers should be forward-compatible
1792 * with the new auxiliary field. This code should be
1793 * conditionalized if any buggy AHCI controllers are
1796 pi.flags |= ATA_FLAG_FPDMA_AUX;
1799 if (hpriv->cap & HOST_CAP_PMP)
1800 pi.flags |= ATA_FLAG_PMP;
1802 ahci_set_em_messages(hpriv, &pi);
1804 if (ahci_broken_system_poweroff(pdev)) {
1805 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1806 dev_info(&pdev->dev,
1807 "quirky BIOS, skipping spindown on poweroff\n");
1810 if (ahci_broken_lpm(pdev)) {
1811 pi.flags |= ATA_FLAG_NO_LPM;
1812 dev_warn(&pdev->dev,
1813 "BIOS update required for Link Power Management support\n");
1816 if (ahci_broken_suspend(pdev)) {
1817 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1818 dev_warn(&pdev->dev,
1819 "BIOS update required for suspend/resume\n");
1822 if (ahci_broken_online(pdev)) {
1823 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1824 dev_info(&pdev->dev,
1825 "online status unreliable, applying workaround\n");
1829 /* Acer SA5-271 workaround modifies private_data */
1830 acer_sa5_271_workaround(hpriv, pdev);
1832 /* CAP.NP sometimes indicate the index of the last enabled
1833 * port, at other times, that of the last possible port, so
1834 * determining the maximum port number requires looking at
1835 * both CAP.NP and port_map.
1837 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1839 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1842 host->private_data = hpriv;
1844 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1845 /* legacy intx interrupts */
1848 hpriv->irq = pci_irq_vector(pdev, 0);
1850 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1851 host->flags |= ATA_HOST_PARALLEL_SCAN;
1853 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1855 if (pi.flags & ATA_FLAG_EM)
1856 ahci_reset_em(host);
1858 for (i = 0; i < host->n_ports; i++) {
1859 struct ata_port *ap = host->ports[i];
1861 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1862 ata_port_pbar_desc(ap, ahci_pci_bar,
1863 0x100 + ap->port_no * 0x80, "port");
1865 /* set enclosure management message type */
1866 if (ap->flags & ATA_FLAG_EM)
1867 ap->em_message_type = hpriv->em_msg_type;
1869 ahci_update_initial_lpm_policy(ap, hpriv);
1871 /* disabled/not-implemented port */
1872 if (!(hpriv->port_map & (1 << i)))
1873 ap->ops = &ata_dummy_port_ops;
1876 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1877 ahci_p5wdh_workaround(host);
1879 /* apply gtf filter quirk */
1880 ahci_gtf_filter_workaround(host);
1882 /* initialize adapter */
1883 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1887 rc = ahci_reset_controller(host);
1891 ahci_pci_init_controller(host);
1892 ahci_pci_print_info(host);
1894 pci_set_master(pdev);
1896 rc = ahci_host_activate(host, &ahci_sht);
1900 pm_runtime_put_noidle(&pdev->dev);
1904 static void ahci_shutdown_one(struct pci_dev *pdev)
1906 ata_pci_shutdown_one(pdev);
1909 static void ahci_remove_one(struct pci_dev *pdev)
1911 pm_runtime_get_noresume(&pdev->dev);
1912 ata_pci_remove_one(pdev);
1915 module_pci_driver(ahci_pci_driver);
1917 MODULE_AUTHOR("Jeff Garzik");
1918 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1919 MODULE_LICENSE("GPL");
1920 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1921 MODULE_VERSION(DRV_VERSION);