1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
49 /* board IDs by feature in alphabetical order */
58 /* board IDs for specific chipsets in alphabetical order */
65 board_ahci_sb700, /* for SB700 and SB800 */
69 * board IDs for Intel chipsets that support more than 6 ports
70 * *and* end up needing the PCS quirk.
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static void ahci_remove_one(struct pci_dev *dev);
83 static void ahci_shutdown_one(struct pci_dev *dev);
84 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
90 static bool is_mcp89_apple(struct pci_dev *pdev);
91 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
94 static int ahci_pci_device_runtime_suspend(struct device *dev);
95 static int ahci_pci_device_runtime_resume(struct device *dev);
96 #ifdef CONFIG_PM_SLEEP
97 static int ahci_pci_device_suspend(struct device *dev);
98 static int ahci_pci_device_resume(struct device *dev);
100 #endif /* CONFIG_PM */
102 static struct scsi_host_template ahci_sht = {
106 static struct ata_port_operations ahci_vt8251_ops = {
107 .inherits = &ahci_ops,
108 .hardreset = ahci_vt8251_hardreset,
111 static struct ata_port_operations ahci_p5wdh_ops = {
112 .inherits = &ahci_ops,
113 .hardreset = ahci_p5wdh_hardreset,
116 static struct ata_port_operations ahci_avn_ops = {
117 .inherits = &ahci_ops,
118 .hardreset = ahci_avn_hardreset,
121 static const struct ata_port_info ahci_port_info[] = {
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
129 [board_ahci_ign_iferr] = {
130 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_mobile] = {
137 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_nomsi] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_noncq] = {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
157 [board_ahci_nosntf] = {
158 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
159 .flags = AHCI_FLAG_COMMON,
160 .pio_mask = ATA_PIO4,
161 .udma_mask = ATA_UDMA6,
162 .port_ops = &ahci_ops,
164 [board_ahci_yes_fbs] = {
165 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
166 .flags = AHCI_FLAG_COMMON,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_avn_ops,
178 [board_ahci_mcp65] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
181 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
186 [board_ahci_mcp77] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
193 [board_ahci_mcp89] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
202 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
203 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
208 [board_ahci_sb600] = {
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = { /* for SB700 and SB800 */
218 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_pmp_retry_srst_ops,
224 [board_ahci_vt8251] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
226 .flags = AHCI_FLAG_COMMON,
227 .pio_mask = ATA_PIO4,
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &ahci_vt8251_ops,
231 [board_ahci_pcs7] = {
232 .flags = AHCI_FLAG_COMMON,
233 .pio_mask = ATA_PIO4,
234 .udma_mask = ATA_UDMA6,
235 .port_ops = &ahci_ops,
239 static const struct pci_device_id ahci_pci_tbl[] = {
241 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
242 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
243 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
244 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
245 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
246 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
247 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
248 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
249 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
250 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
251 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
252 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
253 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
254 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
255 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
256 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
257 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
258 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
259 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
260 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
261 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
263 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
265 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
266 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
268 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
269 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
270 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
271 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
272 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
273 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
275 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
276 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
277 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
278 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
279 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
280 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
302 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
303 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
304 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
305 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
306 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
307 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
308 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
309 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
310 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
311 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
312 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
313 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
314 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
315 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
316 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
317 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
318 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
320 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
321 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
322 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
323 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
324 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
325 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
326 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
327 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
328 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
329 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
330 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
331 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
332 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
333 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
334 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
335 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
336 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
337 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
345 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
347 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
355 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
356 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
357 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
358 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
359 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
360 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
361 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
363 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
364 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
365 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
366 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
367 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
368 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
369 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
370 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
371 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
372 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
373 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
374 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
375 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
376 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
377 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
378 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
379 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
380 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
381 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
382 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
383 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
384 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
386 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
389 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
390 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
391 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
392 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
393 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
394 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
395 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
396 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
397 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
398 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
399 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
400 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
401 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
402 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
404 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
405 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
406 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
407 /* JMicron 362B and 362C have an AHCI function with IDE class code */
408 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
409 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
410 /* May need to update quirk_jmicron_async_suspend() for additions */
413 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
414 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
415 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
416 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
417 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
418 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
419 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
422 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
423 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
424 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
425 /* AMD is using RAID class only for ahci controllers */
426 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
427 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
430 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
431 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
434 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
437 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
438 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
439 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
440 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
441 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
442 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
461 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
462 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
463 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
464 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
465 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
466 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
467 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
468 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
469 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
470 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
493 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
494 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
502 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
504 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
505 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
506 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
508 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
509 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
510 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
511 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
512 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
513 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
514 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
515 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
516 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
517 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
520 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
521 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
522 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
524 /* ST Microelectronics */
525 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
528 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
529 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
531 .class = PCI_CLASS_STORAGE_SATA_AHCI,
532 .class_mask = 0xffffff,
533 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
534 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
535 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
536 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
537 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
538 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
540 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
542 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
544 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
545 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
546 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
547 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
548 .driver_data = board_ahci_yes_fbs },
549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
550 .driver_data = board_ahci_yes_fbs },
551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
552 .driver_data = board_ahci_yes_fbs },
553 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
554 .driver_data = board_ahci_yes_fbs },
555 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
556 .driver_data = board_ahci_yes_fbs },
557 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
558 .driver_data = board_ahci_yes_fbs },
561 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
562 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
565 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
566 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
567 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
568 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
569 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
570 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
573 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
574 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
576 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
577 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
580 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
582 /* Generic, PCI class code for AHCI */
583 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
584 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
586 { } /* terminate list */
589 static const struct dev_pm_ops ahci_pci_pm_ops = {
590 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
591 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
592 ahci_pci_device_runtime_resume, NULL)
595 static struct pci_driver ahci_pci_driver = {
597 .id_table = ahci_pci_tbl,
598 .probe = ahci_init_one,
599 .remove = ahci_remove_one,
600 .shutdown = ahci_shutdown_one,
602 .pm = &ahci_pci_pm_ops,
606 #if IS_ENABLED(CONFIG_PATA_MARVELL)
607 static int marvell_enable;
609 static int marvell_enable = 1;
611 module_param(marvell_enable, int, 0644);
612 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
614 static int mobile_lpm_policy = -1;
615 module_param(mobile_lpm_policy, int, 0644);
616 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
618 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
619 struct ahci_host_priv *hpriv)
621 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
622 dev_info(&pdev->dev, "JMB361 has only one port\n");
623 hpriv->force_port_map = 1;
627 * Temporary Marvell 6145 hack: PATA port presence
628 * is asserted through the standard AHCI port
629 * presence register, as bit 4 (counting from 0)
631 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
632 if (pdev->device == 0x6121)
633 hpriv->mask_port_map = 0x3;
635 hpriv->mask_port_map = 0xf;
637 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
640 ahci_save_initial_config(&pdev->dev, hpriv);
643 static int ahci_pci_reset_controller(struct ata_host *host)
645 struct pci_dev *pdev = to_pci_dev(host->dev);
646 struct ahci_host_priv *hpriv = host->private_data;
649 rc = ahci_reset_controller(host);
654 * If platform firmware failed to enable ports, try to enable
657 ahci_intel_pcs_quirk(pdev, hpriv);
662 static void ahci_pci_init_controller(struct ata_host *host)
664 struct ahci_host_priv *hpriv = host->private_data;
665 struct pci_dev *pdev = to_pci_dev(host->dev);
666 void __iomem *port_mmio;
670 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
671 if (pdev->device == 0x6121)
675 port_mmio = __ahci_port_base(host, mv);
677 writel(0, port_mmio + PORT_IRQ_MASK);
680 tmp = readl(port_mmio + PORT_IRQ_STAT);
681 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
683 writel(tmp, port_mmio + PORT_IRQ_STAT);
686 ahci_init_controller(host);
689 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
690 unsigned long deadline)
692 struct ata_port *ap = link->ap;
693 struct ahci_host_priv *hpriv = ap->host->private_data;
699 hpriv->stop_engine(ap);
701 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
702 deadline, &online, NULL);
704 hpriv->start_engine(ap);
706 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
708 /* vt8251 doesn't clear BSY on signature FIS reception,
709 * request follow-up softreset.
711 return online ? -EAGAIN : rc;
714 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
715 unsigned long deadline)
717 struct ata_port *ap = link->ap;
718 struct ahci_port_priv *pp = ap->private_data;
719 struct ahci_host_priv *hpriv = ap->host->private_data;
720 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
721 struct ata_taskfile tf;
725 hpriv->stop_engine(ap);
727 /* clear D2H reception area to properly wait for D2H FIS */
728 ata_tf_init(link->device, &tf);
729 tf.command = ATA_BUSY;
730 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
732 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
733 deadline, &online, NULL);
735 hpriv->start_engine(ap);
737 /* The pseudo configuration device on SIMG4726 attached to
738 * ASUS P5W-DH Deluxe doesn't send signature FIS after
739 * hardreset if no device is attached to the first downstream
740 * port && the pseudo device locks up on SRST w/ PMP==0. To
741 * work around this, wait for !BSY only briefly. If BSY isn't
742 * cleared, perform CLO and proceed to IDENTIFY (achieved by
743 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
745 * Wait for two seconds. Devices attached to downstream port
746 * which can't process the following IDENTIFY after this will
747 * have to be reset again. For most cases, this should
748 * suffice while making probing snappish enough.
751 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
754 ahci_kick_engine(ap);
760 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
762 * It has been observed with some SSDs that the timing of events in the
763 * link synchronization phase can leave the port in a state that can not
764 * be recovered by a SATA-hard-reset alone. The failing signature is
765 * SStatus.DET stuck at 1 ("Device presence detected but Phy
766 * communication not established"). It was found that unloading and
767 * reloading the driver when this problem occurs allows the drive
768 * connection to be recovered (DET advanced to 0x3). The critical
769 * component of reloading the driver is that the port state machines are
770 * reset by bouncing "port enable" in the AHCI PCS configuration
771 * register. So, reproduce that effect by bouncing a port whenever we
772 * see DET==1 after a reset.
774 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
775 unsigned long deadline)
777 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
778 struct ata_port *ap = link->ap;
779 struct ahci_port_priv *pp = ap->private_data;
780 struct ahci_host_priv *hpriv = ap->host->private_data;
781 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
782 unsigned long tmo = deadline - jiffies;
783 struct ata_taskfile tf;
789 hpriv->stop_engine(ap);
791 for (i = 0; i < 2; i++) {
794 int port = ap->port_no;
795 struct ata_host *host = ap->host;
796 struct pci_dev *pdev = to_pci_dev(host->dev);
798 /* clear D2H reception area to properly wait for D2H FIS */
799 ata_tf_init(link->device, &tf);
800 tf.command = ATA_BUSY;
801 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
803 rc = sata_link_hardreset(link, timing, deadline, &online,
806 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
807 (sstatus & 0xf) != 1)
810 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
813 pci_read_config_word(pdev, 0x92, &val);
815 pci_write_config_word(pdev, 0x92, val);
816 ata_msleep(ap, 1000);
818 pci_write_config_word(pdev, 0x92, val);
822 hpriv->start_engine(ap);
825 *class = ahci_dev_classify(ap);
827 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
833 static void ahci_pci_disable_interrupts(struct ata_host *host)
835 struct ahci_host_priv *hpriv = host->private_data;
836 void __iomem *mmio = hpriv->mmio;
839 /* AHCI spec rev1.1 section 8.3.3:
840 * Software must disable interrupts prior to requesting a
841 * transition of the HBA to D3 state.
843 ctl = readl(mmio + HOST_CTL);
845 writel(ctl, mmio + HOST_CTL);
846 readl(mmio + HOST_CTL); /* flush */
849 static int ahci_pci_device_runtime_suspend(struct device *dev)
851 struct pci_dev *pdev = to_pci_dev(dev);
852 struct ata_host *host = pci_get_drvdata(pdev);
854 ahci_pci_disable_interrupts(host);
858 static int ahci_pci_device_runtime_resume(struct device *dev)
860 struct pci_dev *pdev = to_pci_dev(dev);
861 struct ata_host *host = pci_get_drvdata(pdev);
864 rc = ahci_pci_reset_controller(host);
867 ahci_pci_init_controller(host);
871 #ifdef CONFIG_PM_SLEEP
872 static int ahci_pci_device_suspend(struct device *dev)
874 struct pci_dev *pdev = to_pci_dev(dev);
875 struct ata_host *host = pci_get_drvdata(pdev);
876 struct ahci_host_priv *hpriv = host->private_data;
878 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
880 "BIOS update required for suspend/resume\n");
884 ahci_pci_disable_interrupts(host);
885 return ata_host_suspend(host, PMSG_SUSPEND);
888 static int ahci_pci_device_resume(struct device *dev)
890 struct pci_dev *pdev = to_pci_dev(dev);
891 struct ata_host *host = pci_get_drvdata(pdev);
894 /* Apple BIOS helpfully mangles the registers on resume */
895 if (is_mcp89_apple(pdev))
896 ahci_mcp89_apple_enable(pdev);
898 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
899 rc = ahci_pci_reset_controller(host);
903 ahci_pci_init_controller(host);
906 ata_host_resume(host);
912 #endif /* CONFIG_PM */
914 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
916 const int dma_bits = using_dac ? 64 : 32;
920 * If the device fixup already set the dma_mask to some non-standard
921 * value, don't extend it here. This happens on STA2X11, for example.
923 * XXX: manipulating the DMA mask from platform code is completely
924 * bogus, platform code should use dev->bus_dma_mask instead..
926 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
929 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
931 dev_err(&pdev->dev, "DMA enable failed\n");
935 static void ahci_pci_print_info(struct ata_host *host)
937 struct pci_dev *pdev = to_pci_dev(host->dev);
941 pci_read_config_word(pdev, 0x0a, &cc);
942 if (cc == PCI_CLASS_STORAGE_IDE)
944 else if (cc == PCI_CLASS_STORAGE_SATA)
946 else if (cc == PCI_CLASS_STORAGE_RAID)
951 ahci_print_info(host, scc_s);
954 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
955 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
956 * support PMP and the 4726 either directly exports the device
957 * attached to the first downstream port or acts as a hardware storage
958 * controller and emulate a single ATA device (can be RAID 0/1 or some
959 * other configuration).
961 * When there's no device attached to the first downstream port of the
962 * 4726, "Config Disk" appears, which is a pseudo ATA device to
963 * configure the 4726. However, ATA emulation of the device is very
964 * lame. It doesn't send signature D2H Reg FIS after the initial
965 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
967 * The following function works around the problem by always using
968 * hardreset on the port and not depending on receiving signature FIS
969 * afterward. If signature FIS isn't received soon, ATA class is
970 * assumed without follow-up softreset.
972 static void ahci_p5wdh_workaround(struct ata_host *host)
974 static const struct dmi_system_id sysids[] = {
976 .ident = "P5W DH Deluxe",
978 DMI_MATCH(DMI_SYS_VENDOR,
979 "ASUSTEK COMPUTER INC"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
985 struct pci_dev *pdev = to_pci_dev(host->dev);
987 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
988 dmi_check_system(sysids)) {
989 struct ata_port *ap = host->ports[1];
992 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
994 ap->ops = &ahci_p5wdh_ops;
995 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1000 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1001 * booting in BIOS compatibility mode. We restore the registers but not ID.
1003 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1007 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1009 pci_read_config_dword(pdev, 0xf8, &val);
1011 /* the following changes the device ID, but appears not to affect function */
1012 /* val = (val & ~0xf0000000) | 0x80000000; */
1013 pci_write_config_dword(pdev, 0xf8, val);
1015 pci_read_config_dword(pdev, 0x54c, &val);
1017 pci_write_config_dword(pdev, 0x54c, val);
1019 pci_read_config_dword(pdev, 0x4a4, &val);
1022 pci_write_config_dword(pdev, 0x4a4, val);
1024 pci_read_config_dword(pdev, 0x54c, &val);
1026 pci_write_config_dword(pdev, 0x54c, val);
1028 pci_read_config_dword(pdev, 0xf8, &val);
1029 val &= ~(1 << 0x1b);
1030 pci_write_config_dword(pdev, 0xf8, val);
1033 static bool is_mcp89_apple(struct pci_dev *pdev)
1035 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1036 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1037 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1038 pdev->subsystem_device == 0xcb89;
1041 /* only some SB600 ahci controllers can do 64bit DMA */
1042 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1044 static const struct dmi_system_id sysids[] = {
1046 * The oldest version known to be broken is 0901 and
1047 * working is 1501 which was released on 2007-10-26.
1048 * Enable 64bit DMA on 1501 and anything newer.
1050 * Please read bko#9412 for more info.
1053 .ident = "ASUS M2A-VM",
1055 DMI_MATCH(DMI_BOARD_VENDOR,
1056 "ASUSTeK Computer INC."),
1057 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1059 .driver_data = "20071026", /* yyyymmdd */
1062 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1063 * support 64bit DMA.
1065 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1066 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1067 * This spelling mistake was fixed in BIOS version 1.5, so
1068 * 1.5 and later have the Manufacturer as
1069 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1070 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1072 * BIOS versions earlier than 1.9 had a Board Product Name
1073 * DMI field of "MS-7376". This was changed to be
1074 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1075 * match on DMI_BOARD_NAME of "MS-7376".
1078 .ident = "MSI K9A2 Platinum",
1080 DMI_MATCH(DMI_BOARD_VENDOR,
1081 "MICRO-STAR INTER"),
1082 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1086 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1089 * This board also had the typo mentioned above in the
1090 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1091 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1094 .ident = "MSI K9AGM2",
1096 DMI_MATCH(DMI_BOARD_VENDOR,
1097 "MICRO-STAR INTER"),
1098 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1102 * All BIOS versions for the Asus M3A support 64bit DMA.
1103 * (all release versions from 0301 to 1206 were tested)
1106 .ident = "ASUS M3A",
1108 DMI_MATCH(DMI_BOARD_VENDOR,
1109 "ASUSTeK Computer INC."),
1110 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1115 const struct dmi_system_id *match;
1116 int year, month, date;
1119 match = dmi_first_match(sysids);
1120 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1124 if (!match->driver_data)
1127 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1128 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1130 if (strcmp(buf, match->driver_data) >= 0)
1133 dev_warn(&pdev->dev,
1134 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1140 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1144 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1146 static const struct dmi_system_id broken_systems[] = {
1148 .ident = "HP Compaq nx6310",
1150 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1151 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1153 /* PCI slot number of the controller */
1154 .driver_data = (void *)0x1FUL,
1157 .ident = "HP Compaq 6720s",
1159 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1160 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1162 /* PCI slot number of the controller */
1163 .driver_data = (void *)0x1FUL,
1166 { } /* terminate list */
1168 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1171 unsigned long slot = (unsigned long)dmi->driver_data;
1172 /* apply the quirk only to on-board controllers */
1173 return slot == PCI_SLOT(pdev->devfn);
1179 static bool ahci_broken_suspend(struct pci_dev *pdev)
1181 static const struct dmi_system_id sysids[] = {
1183 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1184 * to the harddisk doesn't become online after
1185 * resuming from STR. Warn and fail suspend.
1187 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1189 * Use dates instead of versions to match as HP is
1190 * apparently recycling both product and version
1193 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1198 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1199 DMI_MATCH(DMI_PRODUCT_NAME,
1200 "HP Pavilion dv4 Notebook PC"),
1202 .driver_data = "20090105", /* F.30 */
1207 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1208 DMI_MATCH(DMI_PRODUCT_NAME,
1209 "HP Pavilion dv5 Notebook PC"),
1211 .driver_data = "20090506", /* F.16 */
1216 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1217 DMI_MATCH(DMI_PRODUCT_NAME,
1218 "HP Pavilion dv6 Notebook PC"),
1220 .driver_data = "20090423", /* F.21 */
1225 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1226 DMI_MATCH(DMI_PRODUCT_NAME,
1227 "HP HDX18 Notebook PC"),
1229 .driver_data = "20090430", /* F.23 */
1232 * Acer eMachines G725 has the same problem. BIOS
1233 * V1.03 is known to be broken. V3.04 is known to
1234 * work. Between, there are V1.06, V2.06 and V3.03
1235 * that we don't have much idea about. For now,
1236 * blacklist anything older than V3.04.
1238 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1243 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1244 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1246 .driver_data = "20091216", /* V3.04 */
1248 { } /* terminate list */
1250 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1251 int year, month, date;
1254 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1257 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1258 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1260 return strcmp(buf, dmi->driver_data) < 0;
1263 static bool ahci_broken_lpm(struct pci_dev *pdev)
1265 static const struct dmi_system_id sysids[] = {
1266 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1269 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1270 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1272 .driver_data = "20180406", /* 1.31 */
1276 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1277 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1279 .driver_data = "20180420", /* 1.28 */
1283 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1284 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1286 .driver_data = "20180315", /* 1.33 */
1290 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1291 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1294 * Note date based on release notes, 2.35 has been
1295 * reported to be good, but I've been unable to get
1296 * a hold of the reporter to get the DMI BIOS date.
1299 .driver_data = "20180310", /* 2.35 */
1301 { } /* terminate list */
1303 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1304 int year, month, date;
1310 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1311 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1313 return strcmp(buf, dmi->driver_data) < 0;
1316 static bool ahci_broken_online(struct pci_dev *pdev)
1318 #define ENCODE_BUSDEVFN(bus, slot, func) \
1319 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1320 static const struct dmi_system_id sysids[] = {
1322 * There are several gigabyte boards which use
1323 * SIMG5723s configured as hardware RAID. Certain
1324 * 5723 firmware revisions shipped there keep the link
1325 * online but fail to answer properly to SRST or
1326 * IDENTIFY when no device is attached downstream
1327 * causing libata to retry quite a few times leading
1328 * to excessive detection delay.
1330 * As these firmwares respond to the second reset try
1331 * with invalid device signature, considering unknown
1332 * sig as offline works around the problem acceptably.
1335 .ident = "EP45-DQ6",
1337 DMI_MATCH(DMI_BOARD_VENDOR,
1338 "Gigabyte Technology Co., Ltd."),
1339 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1341 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1344 .ident = "EP45-DS5",
1346 DMI_MATCH(DMI_BOARD_VENDOR,
1347 "Gigabyte Technology Co., Ltd."),
1348 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1350 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1352 { } /* terminate list */
1354 #undef ENCODE_BUSDEVFN
1355 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1361 val = (unsigned long)dmi->driver_data;
1363 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1366 static bool ahci_broken_devslp(struct pci_dev *pdev)
1368 /* device with broken DEVSLP but still showing SDS capability */
1369 static const struct pci_device_id ids[] = {
1370 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1374 return pci_match_id(ids, pdev);
1377 #ifdef CONFIG_ATA_ACPI
1378 static void ahci_gtf_filter_workaround(struct ata_host *host)
1380 static const struct dmi_system_id sysids[] = {
1382 * Aspire 3810T issues a bunch of SATA enable commands
1383 * via _GTF including an invalid one and one which is
1384 * rejected by the device. Among the successful ones
1385 * is FPDMA non-zero offset enable which when enabled
1386 * only on the drive side leads to NCQ command
1387 * failures. Filter it out.
1390 .ident = "Aspire 3810T",
1392 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1393 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1395 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1399 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1400 unsigned int filter;
1406 filter = (unsigned long)dmi->driver_data;
1407 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1408 filter, dmi->ident);
1410 for (i = 0; i < host->n_ports; i++) {
1411 struct ata_port *ap = host->ports[i];
1412 struct ata_link *link;
1413 struct ata_device *dev;
1415 ata_for_each_link(link, ap, EDGE)
1416 ata_for_each_dev(dev, link, ALL)
1417 dev->gtf_filter |= filter;
1421 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1426 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1427 * as DUMMY, or detected but eventually get a "link down" and never get up
1428 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1429 * port_map may hold a value of 0x00.
1431 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1432 * and can significantly reduce the occurrence of the problem.
1434 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1436 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1437 struct pci_dev *pdev)
1439 static const struct dmi_system_id sysids[] = {
1441 .ident = "Acer Switch Alpha 12",
1443 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1444 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1450 if (dmi_check_system(sysids)) {
1451 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1452 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1453 hpriv->port_map = 0x7;
1454 hpriv->cap = 0xC734FF02;
1461 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1462 * Workaround is to make sure all pending IRQs are served before leaving
1465 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1467 struct ata_host *host = dev_instance;
1468 struct ahci_host_priv *hpriv;
1469 unsigned int rc = 0;
1471 u32 irq_stat, irq_masked;
1472 unsigned int handled = 1;
1475 hpriv = host->private_data;
1477 irq_stat = readl(mmio + HOST_IRQ_STAT);
1482 irq_masked = irq_stat & hpriv->port_map;
1483 spin_lock(&host->lock);
1484 rc = ahci_handle_port_intr(host, irq_masked);
1487 writel(irq_stat, mmio + HOST_IRQ_STAT);
1488 irq_stat = readl(mmio + HOST_IRQ_STAT);
1489 spin_unlock(&host->lock);
1493 return IRQ_RETVAL(handled);
1497 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1498 struct ahci_host_priv *hpriv)
1504 * Check if this device might have remapped nvme devices.
1506 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1507 pci_resource_len(pdev, bar) < SZ_512K ||
1508 bar != AHCI_PCI_BAR_STANDARD ||
1509 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1512 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1513 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1514 if ((cap & (1 << i)) == 0)
1516 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1517 != PCI_CLASS_STORAGE_EXPRESS)
1520 /* We've found a remapped device */
1527 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1528 dev_warn(&pdev->dev,
1529 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1532 * Don't rely on the msi-x capability in the remap case,
1533 * share the legacy interrupt across ahci and remapped devices.
1535 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1538 static int ahci_get_irq_vector(struct ata_host *host, int port)
1540 return pci_irq_vector(to_pci_dev(host->dev), port);
1543 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1544 struct ahci_host_priv *hpriv)
1548 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1552 * If number of MSIs is less than number of ports then Sharing Last
1553 * Message mode could be enforced. In this case assume that advantage
1554 * of multipe MSIs is negated and use single MSI mode instead.
1557 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1558 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1560 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1561 hpriv->get_irq_vector = ahci_get_irq_vector;
1562 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1567 * Fallback to single MSI mode if the controller
1568 * enforced MRSM mode.
1571 "ahci: MRSM is on, fallback to single MSI\n");
1572 pci_free_irq_vectors(pdev);
1577 * If the host is not capable of supporting per-port vectors, fall
1578 * back to single MSI before finally attempting single MSI-X.
1580 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1583 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1586 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1587 struct ahci_host_priv *hpriv)
1589 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1592 /* Ignore processing for non mobile platforms */
1593 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1596 /* user modified policy via module param */
1597 if (mobile_lpm_policy != -1) {
1598 policy = mobile_lpm_policy;
1603 if (policy > ATA_LPM_MED_POWER &&
1604 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1605 if (hpriv->cap & HOST_CAP_PART)
1606 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1607 else if (hpriv->cap & HOST_CAP_SSC)
1608 policy = ATA_LPM_MIN_POWER;
1613 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1614 ap->target_lpm_policy = policy;
1617 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1619 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1623 * Only apply the 6-port PCS quirk for known legacy platforms.
1625 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1628 /* Skip applying the quirk on Denverton and beyond */
1629 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1633 * port_map is determined from PORTS_IMPL PCI register which is
1634 * implemented as write or write-once register. If the register
1635 * isn't programmed, ahci automatically generates it from number
1636 * of ports, which is good enough for PCS programming. It is
1637 * otherwise expected that platform firmware enables the ports
1638 * before the OS boots.
1640 pci_read_config_word(pdev, PCS_6, &tmp16);
1641 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1642 tmp16 |= hpriv->port_map;
1643 pci_write_config_word(pdev, PCS_6, tmp16);
1647 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1649 unsigned int board_id = ent->driver_data;
1650 struct ata_port_info pi = ahci_port_info[board_id];
1651 const struct ata_port_info *ppi[] = { &pi, NULL };
1652 struct device *dev = &pdev->dev;
1653 struct ahci_host_priv *hpriv;
1654 struct ata_host *host;
1656 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1660 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1662 ata_print_version_once(&pdev->dev, DRV_VERSION);
1664 /* The AHCI driver can only drive the SATA ports, the PATA driver
1665 can drive them all so if both drivers are selected make sure
1666 AHCI stays out of the way */
1667 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1670 /* Apple BIOS on MCP89 prevents us using AHCI */
1671 if (is_mcp89_apple(pdev))
1672 ahci_mcp89_apple_enable(pdev);
1674 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1675 * At the moment, we can only use the AHCI mode. Let the users know
1676 * that for SAS drives they're out of luck.
1678 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1679 dev_info(&pdev->dev,
1680 "PDC42819 can only drive SATA devices with this driver\n");
1682 /* Some devices use non-standard BARs */
1683 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1684 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1685 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1686 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1687 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1688 if (pdev->device == 0xa01c)
1689 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1690 if (pdev->device == 0xa084)
1691 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1694 /* acquire resources */
1695 rc = pcim_enable_device(pdev);
1699 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1700 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1703 /* ICH6s share the same PCI ID for both piix and ahci
1704 * modes. Enabling ahci mode while MAP indicates
1705 * combined mode is a bad idea. Yield to ata_piix.
1707 pci_read_config_byte(pdev, ICH_MAP, &map);
1709 dev_info(&pdev->dev,
1710 "controller is in combined mode, can't enable AHCI mode\n");
1715 /* AHCI controllers often implement SFF compatible interface.
1716 * Grab all PCI BARs just in case.
1718 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1720 pcim_pin_device(pdev);
1724 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1727 hpriv->flags |= (unsigned long)pi.private_data;
1729 /* MCP65 revision A1 and A2 can't do MSI */
1730 if (board_id == board_ahci_mcp65 &&
1731 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1732 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1734 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1735 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1736 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1738 /* only some SB600s can do 64bit DMA */
1739 if (ahci_sb600_enable_64bit(pdev))
1740 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1742 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1744 /* detect remapped nvme devices */
1745 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1747 /* must set flag prior to save config in order to take effect */
1748 if (ahci_broken_devslp(pdev))
1749 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1752 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1753 pdev->device == 0xa235 &&
1754 pdev->revision < 0x30)
1755 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1757 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1758 hpriv->irq_handler = ahci_thunderx_irq_handler;
1761 /* save initial config */
1762 ahci_pci_save_initial_config(pdev, hpriv);
1765 if (hpriv->cap & HOST_CAP_NCQ) {
1766 pi.flags |= ATA_FLAG_NCQ;
1768 * Auto-activate optimization is supposed to be
1769 * supported on all AHCI controllers indicating NCQ
1770 * capability, but it seems to be broken on some
1771 * chipsets including NVIDIAs.
1773 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1774 pi.flags |= ATA_FLAG_FPDMA_AA;
1777 * All AHCI controllers should be forward-compatible
1778 * with the new auxiliary field. This code should be
1779 * conditionalized if any buggy AHCI controllers are
1782 pi.flags |= ATA_FLAG_FPDMA_AUX;
1785 if (hpriv->cap & HOST_CAP_PMP)
1786 pi.flags |= ATA_FLAG_PMP;
1788 ahci_set_em_messages(hpriv, &pi);
1790 if (ahci_broken_system_poweroff(pdev)) {
1791 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1792 dev_info(&pdev->dev,
1793 "quirky BIOS, skipping spindown on poweroff\n");
1796 if (ahci_broken_lpm(pdev)) {
1797 pi.flags |= ATA_FLAG_NO_LPM;
1798 dev_warn(&pdev->dev,
1799 "BIOS update required for Link Power Management support\n");
1802 if (ahci_broken_suspend(pdev)) {
1803 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1804 dev_warn(&pdev->dev,
1805 "BIOS update required for suspend/resume\n");
1808 if (ahci_broken_online(pdev)) {
1809 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1810 dev_info(&pdev->dev,
1811 "online status unreliable, applying workaround\n");
1815 /* Acer SA5-271 workaround modifies private_data */
1816 acer_sa5_271_workaround(hpriv, pdev);
1818 /* CAP.NP sometimes indicate the index of the last enabled
1819 * port, at other times, that of the last possible port, so
1820 * determining the maximum port number requires looking at
1821 * both CAP.NP and port_map.
1823 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1825 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1828 host->private_data = hpriv;
1830 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1831 /* legacy intx interrupts */
1834 hpriv->irq = pci_irq_vector(pdev, 0);
1836 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1837 host->flags |= ATA_HOST_PARALLEL_SCAN;
1839 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1841 if (pi.flags & ATA_FLAG_EM)
1842 ahci_reset_em(host);
1844 for (i = 0; i < host->n_ports; i++) {
1845 struct ata_port *ap = host->ports[i];
1847 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1848 ata_port_pbar_desc(ap, ahci_pci_bar,
1849 0x100 + ap->port_no * 0x80, "port");
1851 /* set enclosure management message type */
1852 if (ap->flags & ATA_FLAG_EM)
1853 ap->em_message_type = hpriv->em_msg_type;
1855 ahci_update_initial_lpm_policy(ap, hpriv);
1857 /* disabled/not-implemented port */
1858 if (!(hpriv->port_map & (1 << i)))
1859 ap->ops = &ata_dummy_port_ops;
1862 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1863 ahci_p5wdh_workaround(host);
1865 /* apply gtf filter quirk */
1866 ahci_gtf_filter_workaround(host);
1868 /* initialize adapter */
1869 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1873 rc = ahci_pci_reset_controller(host);
1877 ahci_pci_init_controller(host);
1878 ahci_pci_print_info(host);
1880 pci_set_master(pdev);
1882 rc = ahci_host_activate(host, &ahci_sht);
1886 pm_runtime_put_noidle(&pdev->dev);
1890 static void ahci_shutdown_one(struct pci_dev *pdev)
1892 ata_pci_shutdown_one(pdev);
1895 static void ahci_remove_one(struct pci_dev *pdev)
1897 pm_runtime_get_noresume(&pdev->dev);
1898 ata_pci_remove_one(pdev);
1901 module_pci_driver(ahci_pci_driver);
1903 MODULE_AUTHOR("Jeff Garzik");
1904 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1905 MODULE_LICENSE("GPL");
1906 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1907 MODULE_VERSION(DRV_VERSION);